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WO2020098023A1 - 显示面板的制作方法及显示面板的检测方法 - Google Patents

显示面板的制作方法及显示面板的检测方法 Download PDF

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Publication number
WO2020098023A1
WO2020098023A1 PCT/CN2018/119705 CN2018119705W WO2020098023A1 WO 2020098023 A1 WO2020098023 A1 WO 2020098023A1 CN 2018119705 W CN2018119705 W CN 2018119705W WO 2020098023 A1 WO2020098023 A1 WO 2020098023A1
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Prior art keywords
short
area
manufacturing
circuit
substrate
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Application number
PCT/CN2018/119705
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English (en)
French (fr)
Inventor
韩建坤
Original Assignee
惠科股份有限公司
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Priority to US17/265,100 priority Critical patent/US11967259B2/en
Publication of WO2020098023A1 publication Critical patent/WO2020098023A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/69—Arrangements or methods for testing or calibrating a device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the present application relates to the field of display technology, and in particular, to a method for manufacturing a display panel and a method for detecting the display panel.
  • Liquid crystal display is an important part of liquid crystal display, which usually includes oppositely arranged color filter substrate (Color Filter Substrate, CF substrate) and thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array substrate), and a liquid crystal layer (Liquid Crystal) disposed between the two substrates.
  • the array substrate is provided with scanning lines and data lines that cross each other to define a plurality of pixel units.
  • the TFT is turned on or off according to the scanning line signals to transmit the data line signals to the pixel units.
  • the liquid crystal molecules of the liquid crystal layer are based on different data.
  • the voltage signal rotates to transmit or block light to refract the light provided by the backlight module to form an image corresponding to the data signal.
  • HSD Half Source Double Gate design is to double the number of gate drive circuits (Gate IC) and scan lines, and reduce the number of source drive circuits (Source IC) and data lines by half, that is, a row
  • the pixel is connected to two adjacent scan lines, and one data line is connected to the left and right columns of sub-pixels at the same time. Due to the lower cost of the Gate IC, this design can save costs and achieve the purpose of reducing costs. However, this design brings trouble to the array test.
  • the non-contact array test is to add a signal to one end of a scanning line and receive the signal at the other end, and detect whether the scanning line is open through the change of the signal.
  • An object of the present application is to provide a method for manufacturing a display panel, including but not limited to improving the accuracy of performing open-circuit detection on scan lines in a half-source driving design.
  • a method for manufacturing a display panel includes manufacturing a first substrate.
  • the manufacturing of the first substrate includes:
  • a first mother board is provided.
  • the first mother board includes a plurality of first effective areas arranged at intervals, and a first cutting area arranged around the first effective area.
  • Each of the first effective areas includes a A display area and a first peripheral wiring area provided at the periphery of the first display area;
  • a plurality of parallel scan lines and short-circuit bars are formed on the first motherboard; the scan lines are located in the first display area and extend to the first peripheral wiring area; the short-circuit bars Located in the first cutting area, the short-circuit bar is connected to the odd-numbered scan lines, so that each odd-numbered scan line is short-circuited with at least one other odd-numbered scan line, or the short-circuit bar and the even-numbered scan line
  • the scanning lines are connected to short-circuit each even-numbered scanning line with at least one other even-numbered scanning line;
  • the second metal layer includes a plurality of parallel and spaced-apart data lines, and performs open-circuit detection and short-circuit detection on the data lines.
  • Another object of the present application is to provide a method for manufacturing a display panel, which includes manufacturing a first substrate.
  • the manufacturing of the first substrate includes:
  • a first mother board is provided.
  • the first mother board includes a plurality of first effective areas arranged at intervals, and a first cutting area arranged around the first effective area.
  • Each of the first effective areas includes a A display area and a first peripheral wiring area provided at the periphery of the first display area;
  • first metal material layer on the first mother board, patterning the first metal material layer through a photomask process to form multiple parallel and spaced scan lines, and shorting bars; the scan lines Located in the first display area and extending to the first peripheral wiring area; the short-circuit bar is located in the first cutting area, the short-circuit bar is connected to the odd-numbered scan lines, so that each odd-numbered line The scan line is short-circuited with at least one other odd-numbered scan line, or the shorting bar is connected with the even-numbered scan line, so that each even-numbered scan line is short-circuited with the other at least one even-numbered scan line;
  • the thickness of the first metal material layer is 2000-5500 angstroms;
  • Forming an insulating layer on the scanning line depositing a second metal material layer on the insulating layer, patterning the second metal material layer to form a plurality of parallel and spaced data lines; performing open circuit detection on the data lines and Short circuit detection.
  • Still another object of the present application is to provide a display panel detection method for detecting an open circuit defect and a short circuit defect of a scanning line of an array substrate, including:
  • the manufacturing method of the display panel provided by the embodiment of the present application is to form short-circuit bars connecting multiple odd-numbered scan lines or multiple even-numbered scan lines at both ends of the scan line while manufacturing the scan lines of the first substrate , So that the electrical connection between the spaced scan lines is formed, when the detection signal is added to the two ends of each scan line to perform an open circuit detection, no capacitance effect will be formed between the two adjacent scan lines, especially for design Even if the distance between two adjacent scan lines is very small, it will not interfere with the open detection of the scan lines, which improves the detection yield of the scan lines on the first substrate of the display panel and the production yield of the display panel. Avoid waste of time and cost caused by late rework.
  • the manufacturing method of the display panel and the detection method of the display panel can avoid the capacitance effect formed between two adjacent scanning lines, and improve the accuracy of the detection of the open circuit of the scanning lines.
  • FIG. 1 is a flowchart of manufacturing an array substrate in the method for manufacturing a display panel provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of step a of manufacturing an array substrate in the method of manufacturing a display panel provided by an embodiment of the present application;
  • step d of manufacturing an array substrate in the method of manufacturing a display panel provided by an embodiment of the present application is a schematic diagram of step d of manufacturing an array substrate in the method of manufacturing a display panel provided by an embodiment of the present application;
  • 5 and 6 are schematic diagrams of steps e and f of the manufacturing method for manufacturing an array substrate in the manufacturing method provided by an embodiment of the present application;
  • FIGS 8 and 9 are schematic diagrams of the array substrate and the opposing substrate aligning and cutting in the method for manufacturing the display panel provided by the embodiment of the present application;
  • FIG. 10 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the manufacturing method of the display panel of this embodiment includes manufacturing a first substrate and a second substrate opposite to the first substrate.
  • the first substrate is an array substrate.
  • the fabrication of the array substrate includes:
  • Step a please refer to FIG. 2, a first mother board 1 is provided.
  • the first mother board 1 includes a plurality of first effective regions 10 arranged at intervals, and a first cutting region 11 arranged around the first effective region 10, each The effective area includes a first display area 101 and a first peripheral wiring area 102 provided on the periphery of the first display area.
  • the first motherboard 1 is a transparent substrate, such as a glass substrate or a transparent plastic substrate.
  • Each first effective area 10 is used to form an array substrate 100 (refer to FIGS. 5 and 6), wherein the first display area 101 is used to form a pixel unit for displaying a picture, and the first peripheral wiring area 102 is used to form Provide signal traces to the pixel units in the first display area 101 and space for providing chips or circuit boards.
  • the array substrate 100 is used to form a display panel 900, and the first cutting region 11 is located between the two first effective regions 10, that is, between the two display panels 900, for subsequent cutting and removal.
  • Step b a plurality of parallel scan lines 31 and short-circuit bars 32 are formed on the first motherboard 1; the scan lines 31 are located in the first display area 101 and extend to the first peripheral wiring area 102.
  • the short-circuit bar 32 is located in the first cutting area 11, and the short-circuit bar 32 is connected to the multiple odd-numbered scan lines 31, thereby short-circuiting the multiple odd-numbered scan lines 31, or the short-circuit bar 32 and the multiple even-numbered lines
  • the scan lines 31 are connected to short-circuit the multiple even-numbered scan lines 31.
  • a first metal material layer is deposited on the first mother board 1 by sputtering coating or the like, a photoresist layer is formed on the first metal material layer, and the photoresist layer is exposed through a mask.
  • the mask plate has a hollow pattern area corresponding to a plurality of scan lines 31 and shorting bars 32, and ultraviolet light exposes the photoresist layer through the hollow pattern area. After development, the photoresist layer corresponds to the scanning line 31 and the shorting bar 32.
  • the area remains, other areas are removed, and then the first metal material layer is wet-etched using the pattern of the photoresist layer as a mask, and at the same time a plurality of scan lines 31 in the first effective area 10 and the first cut are obtained
  • the shorting bar 32 in the area 11 is connected to a plurality of odd-numbered scanning lines 31 or a plurality of even-numbered scanning lines 31.
  • the patterning of the first metal material layer also simultaneously forms a plurality of gates 51 (not shown in FIG. 3, see FIG. 6) in the first display area 101, and the gates 51 are connected to the scanning line 31.
  • the first metal material layer may be chromium (Cr), molybdenum (Mo), copper (Cu), titanium (Ti), molybdenum / aluminum (Mo / Al) composite layer or molybdenum / aluminum / molybdenum (Mo / Al / Mo)
  • the thickness of the first metal material layer is 2000-8000 angstroms, optionally 2000-5500 angstroms.
  • a shorting bar 32 is formed in the first cutting area 11 on one side of the first effective area 10.
  • the shorting bar 32 includes a shorting portion 321 and a connecting portion 322 that are perpendicular to the scanning line 31.
  • the connecting portion 322 One end is connected to the short-circuit part 321, and the other end is connected to an odd-numbered scan line 31 or an even-numbered scan line 31, that is, the connection part 322 is connected to the odd-numbered scan line 32 in one-to-one correspondence, or to the even-numbered scan line 31 one-to-one connection.
  • the short-circuit portion 321 connects the connection portions 322 to short-circuit the multiple odd-numbered scan lines 31 or short-circuit the multiple even-numbered scan lines 31.
  • Each first effective area 10 may correspond to one or more short-circuit bars 32.
  • the following description uses a first effective area 10 as an example to illustrate the short-circuit bar 32.
  • the number of short-circuit parts 321 is one, and the one short-circuit part 321 is simultaneously connected to all odd-numbered scan lines 31 or all even-numbered scan lines 31 in the first effective area 10 through a plurality of connecting parts 322 .
  • the number of the short-circuit portions 321 is multiple, and each short-circuit portion 321 is connected to at least two even-numbered scan lines 31 or at least two odd-numbered scan lines 31 through a plurality of connecting portions 322, such as a short circuit
  • the part 321 is connected to the first, third, fifth, and seventh scanning lines 31 through four connecting parts 322, that is, one short-circuit bar 32 can be connected to the four odd-numbered scan lines 31, and similarly, another short-circuit bar 32 can be connected to the , 11, 13, 15 scan lines 31 ...
  • each odd-numbered scan line 31 is connected to at least one other odd-numbered scan line 31, or each even-numbered scan line 31 is connected to at least one other even-numbered scan line 31.
  • connection between the shorting bar 32 and the scanning line 31 is not limited to the connection in odd order or in even order, but may be other connection methods.
  • one short bar 32 is connected to the fourth and sixth scan lines 31, and the other short bar 32 is connected to the second and eighth scan lines 31.
  • connection portion 322 may extend in parallel from the scan line 31 so as to be perpendicular to the short-circuit portion 321.
  • connection portion 322 and the scanning line 31 may be connected obliquely. This application does not limit this.
  • Step c perform open detection on each scan line 31.
  • non-contact detection is used for the detection of the open circuit of the scanning line.
  • An AC voltage of 200 KHz is applied at a position about 150 ⁇ m above one end of the scanning line 31, and a capacitance is formed between the power-on position and the scanning line, which can reduce the AC voltage.
  • the signal is transmitted to the scanning line and finally detected by the receiving sensor at the other end of the scanning line 31.
  • a capacitance is also formed between the receiving sensor and the scanning line 31. Since the electrical signal is very small and is an AC signal, an amplifier can be used to amplify and filter the AC signal of the receiving sensor, and convert the AC signal into a DC signal for detection.
  • a scanning line 31 is connected to the spaced scanning line 31 through the shorting bar 32, when a signal is applied to both sides of each scanning line 31, even if the distance between the scanning line 31 and the adjacent scanning line 31 is too small No capacitance effect is formed, and no interference is caused to signal detection. If the scanning line 31 has an open defect, an abnormal signal can be detected, thereby accurately detecting the open defect of the scanning line 31, which improves the array substrate Detection yield and production yield to avoid rework due to poor display after subsequent array substrate fabrication or box formation.
  • step d as shown in FIG. 4, the electrical connection between the shorting bar 32 and the scanning line 31 is cut, and a short circuit is detected for each scanning line 31.
  • the scanning line 31 and the connecting portion 322 are laser cut Cut off between each other, so that each scan line 31 is set independently and no longer electrically connected. At this time, short circuit detection is performed on each scan line 31.
  • both ends of the scan line 31 may be cut in the first peripheral wiring area 102, and the cut scanning line 31 extends from the first display area 101 to the first peripheral wiring area 102 near the outside At the edge.
  • Step e referring to FIG. 5 and FIG. 6, in the first effective region 10, a gate insulating layer 52, an active layer 53 and a source / drain metal layer 54 are formed on the scan line 31, and the source / drain metal layer 54 It includes a source / drain and a plurality of parallel and spaced-apart data lines 4 connected to the source.
  • the data lines 4 are respectively subjected to open circuit detection and short circuit detection.
  • a chemical vapor deposition method is used to form the gate insulating layer 52, and the material of the gate insulating layer 52 is at least one of silicon oxide (SiOx) and silicon nitride (SiNx).
  • the thickness of the gate insulating layer 52 is 1000-3000 angstroms.
  • the active layer 53 includes a channel region and ohmic contact layers connected to both sides of the channel region.
  • a second metal material layer is deposited on the active layer 53 by sputter coating, and the second metal material layer is patterned through exposure, development and etching processes to obtain the source / drain and the connection in the first display area 101 A plurality of data lines 4 extending from the first display area 101 to the first peripheral trace area 102 at the source.
  • the second metal material layer may be chromium (Cr), molybdenum (Mo), copper (Cu), titanium (Ti), molybdenum / aluminum (Mo / Al) composite layer or molybdenum / aluminum / molybdenum (Mo / Al / Mo)
  • the thickness of the second metal material layer is 2000-8000 angstroms, specifically 2000-5500 angstroms.
  • Step f as shown in FIG. 6, in the first effective region 10, a passivation layer 55 is formed on the source / drain metal layer, a transparent conductive layer is formed on the passivation layer 55, and the transparent conductive layer is patterned A plurality of pixel electrodes 6 are obtained; an array substrate 100 is obtained in each first effective area 10.
  • a thin film transistor is formed by the gate 51, the gate insulating layer 52, the active layer 53 and the source / drain, and each thin film transistor is connected to a pixel electrode 6 to form a sub-pixel.
  • a row of sub-pixels is driven by two adjacent scanning lines 31, and two adjacent columns of sub-pixels are simultaneously connected to one data line 4, driven by one data, and become an HSD design.
  • the distance between the two scanning lines 31 between the two rows of sub-pixels is small, because in steps 2 and 3 of this embodiment, multiple odd-numbered scan lines 31 are connected or multiple even-numbered lines are scanned by the shorting bar 32
  • the lines 31 are connected to achieve accurate detection of the open defects of each scan line 31.
  • a COA (Color On Array) array substrate can be manufactured by manufacturing an array substrate in the method for manufacturing a display panel provided by the present application, which is the same as the first embodiment Steps a to e are not repeated here, the difference is:
  • step f ′ in the first effective region 10, a passivation layer 55 is formed on the source / drain metal layer, a color resist layer 7 is formed on the passivation layer 55, and the color resist layer 7 A flat layer is formed thereon, a transparent conductive layer is formed on the flat layer, and the transparent conductive layer is patterned to obtain a plurality of pixel electrodes 6, the pixel electrodes 6 are connected to the drain through the via holes in the flat layer and the color resist layer 7, An array substrate 100 is obtained in each first effective area 10.
  • the step of forming the color resist layer 7 includes: depositing a red color resist layer on the passivation layer 55 and patterning to obtain a red color resist block 71, the red color resist block 71 corresponds to a pixel electrode 6 to obtain a red sub-pixel 710 ; Depositing a green color block layer on the red color block 71 and the passivation layer 55 and patterning to obtain a green color block 72, the green color block 72 corresponds to a pixel electrode 6, to obtain a green color block 72; in the red color block A blue color resist layer is deposited on the block 71, the green color resist block 72 and the passivation layer 55 and patterned to obtain a blue color resist block 73.
  • the blue color resist block 73 corresponds to a pixel electrode 6 to obtain a blue sub-pixel 730, as shown in FIG. 7 As shown.
  • the manufacturing method of the display panel of the present application further includes a step of manufacturing the second substrate 200 opposite to the array substrate 100 and a step of boxing and cutting the array substrate 100 and the second substrate 200.
  • the second substrate 200 is a color filter substrate including a color resist layer 7, and the steps of the color filter substrate may specifically include:
  • a second mother board 2 is provided.
  • the second mother board 2 includes a plurality of second effective regions 20 disposed at intervals, and a second cutting region 21 disposed around the second effective region 20.
  • the second cutting region 21 is the same as the first Corresponding to the cutting area 11, it is also used for cutting and removing after the first mother board 1 and the second mother board 2 are subsequently aligned.
  • the second effective area 20 includes a second display area 201 and a second peripheral wiring area 202 provided around the second display area 201; the second effective area 20 corresponds to the first effective area 10, and the second cutting area 21 corresponds to the first One cutting area 11 corresponds.
  • a black matrix layer 80, a color resist layer 7 and a common electrode layer 81 are formed in the second effective area 20.
  • the second peripheral wiring area 202 corresponds to the first peripheral wiring area 201 and is used to form a wiring that provides a signal to the common electrode layer 81 and to provide a package or support between the first motherboard 1 and the second motherboard 2 Structure provides space.
  • the color resist layer 7 includes a plurality of red color resist blocks 71, a green color resist block 72 and a blue color resist block 73 which are arranged at intervals, respectively corresponding to a plurality of sub-pixels on the array substrate 100.
  • the forming steps of the color resist layer 7 include: depositing a red color resist layer on the black matrix layer 80 and the first motherboard 1 in the second effective area 20 and patterning to obtain a red color resist block 71, which corresponds to the array A pixel electrode 6 on the substrate 100; a green color resist layer is deposited on the red color resist block 71 and the black matrix layer 80 and patterned to obtain a green color resist block 72, which corresponds to a pixel electrode on the array substrate 100 6; deposit a blue color resist layer on the red color resist block 71, the green color resist block 72 and the black matrix layer 80 and pattern to obtain a blue color resist block 73, the blue color resist block 73 corresponds to a pixel electrode on an array substrate 100 6.
  • the array substrate 100 and the second substrate 200 that is, the color filter substrates are boxed and cut, which specifically includes: dropping liquid crystal into the first display area 101 on the first motherboard 1 and placing it in the first peripheral wiring area Apply a sealant inside 102, apply UV irradiation curing treatment to the first mother board 1 and the second mother board 2, and cut the first along the outer edges of the first peripheral wiring area 102 and the second peripheral wiring area 202
  • the mother board 1 and the second mother board 2 obtain a plurality of display panels 900, as shown in FIGS. 8 and 9.
  • the manufacturing of the second substrate 200 specifically includes: providing a second mother board 2, the second mother board 2 includes a plurality of second effective regions 20 arranged at intervals, and a second mother region disposed around the second effective region 20
  • Two cutting areas 21, the second effective area 20 includes a second display area 201 and a second peripheral wiring area 202 provided on the periphery of the second display area 201; the second effective area 20 corresponds to the first effective area 10, the second cutting area
  • the area 21 corresponds to the first cutting area 11.
  • the common electrode layer 81 is formed in the second effective region 20, and the alignment layer is formed on the common electrode layer 81, which is not shown in the figure.
  • the array substrate 100 and the second substrate 200 are boxed and cut to obtain a plurality of display panels 900 including the COA type array substrate 100.
  • the present application also provides a display panel 900, which is manufactured using the manufacturing method of the display panel described above, as shown in FIG.
  • the display panel 900 includes an array substrate 100 and a second substrate 200.
  • the second substrate 200 may be a color filter substrate including a color resist layer.
  • the array substrate includes a plurality of scanning lines, a plurality of data lines, and a plurality of sub-pixels, each row of sub-pixels is driven by two adjacent scanning lines, and two adjacent columns of the sub-pixels are simultaneously connected to one of the data lines, Become an HSD design.
  • a scanning line 31 is connected to the interval scanning line 31 through the shorting bar 32, when a signal is applied to both sides of each scanning line 31, the scanning line 31 is adjacent to the adjacent scanning line 31 Even if the distance between the scanning lines 31 is too small, it will not form a capacitive effect and will not interfere with the signal detection. If the scanning line 31 has an open defect, it can detect the abnormality of the signal, thereby accurately detecting the scanning The open defect of the line 31 improves the detection yield and fabrication yield of the display panel, thereby helping to ensure the yield of the display panel 900.
  • the present application also provides a display device (not shown) including the above-mentioned display panel 900 and a backlight module provided on the display panel 900 side.
  • the present application also provides a detection method for a display panel, which is used to detect an open defect and a short defect of a scan line of an array substrate, including:
  • the electrical connection between the even-numbered scan lines or the electrical connection between the odd-numbered scan lines is implemented by short-circuit bars formed on the same layer as the scan lines and formed at the same time, ie, A scanning process and a short-circuit bar are formed at the same time by a photolithography process.
  • the short-circuit bar is connected to a plurality of odd-numbered scan lines and even-numbered scan lines to avoid the formation of a capacitive effect between two adjacent scan lines.
  • the electrical connection between the short-circuit bar and the scanning line is cut by a laser cutting method, and the short-circuit bar and the area where it is located are cut off after the fabrication of multiple display panels is completed.
  • the detection method of the display panel provided by the embodiment of the present application is implemented in step c of the method for manufacturing the display panel described above.
  • step c the method for manufacturing the display panel described above.

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Abstract

一种显示面板的制作方法，包括制作第一基板，在第一母板（1）上形成多条扫描线（31）以及短路棒（32），扫描线（31）位于第一显示区（101）并延伸至第一外围走线区（102），短路棒（32）位于第一切割区（11），短路棒（32）与多条第奇数条扫描线（31）连接，或者短路棒（32）与多条第偶数条扫描线（31）连接，以使每一第奇数条扫描线（31）与其他至少一第奇数条扫描线（31）之间短路，或者所述短路棒（32）与第偶数条扫描线（31）连接，以使每一第偶数条扫描线（31）与其他至少一第偶数条扫描线（31）之间短路。

Description

显示面板的制作方法及显示面板的检测方法
本申请要求于2018年11月14日提交中国专利局，申请号为201811351378.0，发明名称为“显示面板的制作方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的制作方法及显示面板的检测方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。液晶显示面板(Liquid Crystal Display，LCD)是液晶显示器的重要组成部分，其通常包括相对设置的彩色滤光片基板(Color Filter Substrate，CF基板)和薄膜晶体管阵列基板(Thin Film Transistor Array Substrate,TFT阵列基板)，以及配置于该两基板之间的液晶层(Liquid Crystal Layer)构成。阵列基板上设有相互交叉用于限定多个像素单元的扫描线和数据线，TFT根据扫描线的信号打开或关闭，以将数据线的信号传递至像素单元，液晶层的液晶分子根据不同数据电压信号旋转，以透光或遮光，将背光模组所提供的光线折射出来以形成对应数据信号的图像。
HSD(Half Source Double Gate，半源极驱动)设计是增加一倍栅极驱动电路(Gate IC)和扫描线的数量，减少一半源极驱动电路(Source IC)和数据线的数量，即一行子像素连接至两条相邻的扫描线，一条数据线同时连接至左右两列子像素，由于Gate IC成本更低，所以该设计可以节省成本，达到降低成 本的目的。但是该设计给阵列测试带来了困扰，非接触式的阵列测试为在一条扫描线的一端加信号，另一端接收信号，通过信号的变化，检测该条扫描线是否开路。但是，由于相邻两行子像素之间的两条扫描线的距离太近，当第2条扫描线发生开路时，第2条扫描线与第3条扫描线之间形成电容效应，第2条扫描线另一端的电压信号检测不到异常，从而不能准确检测到该第2条扫描线的开路缺陷。
申请内容
本申请一目的在于提供一种显示面板的制作方法，包括但不限于提高在半源极驱动设计中对扫描线进行开路检测的准确性。
本申请实施例采用的技术方案是：一种显示面板的制作方法，包括制作第一基板，所述制作第一基板包括：
提供第一母板，所述第一母板上包括间隔设置的多个第一有效区，以及围绕于所述第一有效区设置的第一切割区，每一所述第一有效区包括第一显示区和设于所述第一显示区外围的第一外围走线区；
在所述第一母板上形成多条平行且间隔设置的扫描线，以及短路棒；所述扫描线位于所述第一显示区并延伸至所述第一外围走线区；所述短路棒位于所述第一切割区，所述短路棒与第奇数条扫描线连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路，或者所述短路棒与第偶数条扫描线连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；
对每一所述扫描线进行开路检测；
将所述短路棒与所述扫描线之间切断，对每一所述扫描线进行短路检测；以及
在所述扫描线上形成绝缘层及第二金属层，所述第二金属层包括多条平行且间隔设置的数据线，对所述数据线进行开路检测和短路检测。
本申请的另一目的在于提供一种显示面板的制作方法，包括制作第一基板，所述制作第一基板包括：
提供第一母板，所述第一母板上包括间隔设置的多个第一有效区，以及围绕于所述第一有效区设置的第一切割区，每一所述第一有效区包括第一显示区和设于所述第一显示区外围的第一外围走线区；
在所述第一母板上沉积第一金属材料材料层，通过一道光罩制程将该第一金属材料层图案化同时形成多条平行且间隔设置的扫描线，以及短路棒；所述扫描线位于所述第一显示区并延伸至所述第一外围走线区；所述短路棒位于所述第一切割区，所述短路棒与第奇数条扫描线连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路，或者所述短路棒与第偶数条扫描线连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；所述第一金属材料层的厚度为2000-5500埃；
对每一所述扫描线采用非接触式检测进行开路检测；
将所述短路棒与所述扫描线之间切断，对每一所述扫描线进行短路检测；以及
在所述扫描线上形成绝缘层，在绝缘层上沉积第二金属材料层，将该第二金属材料层图案化形成多条平行且间隔设置的数据线；对所述数据线进行开路检测和短路检测。
本申请的再一目的在于提供一种显示面板的检测方法，用于对阵列基板的扫描线的开路缺陷和短路缺陷进行检测，包括：
将多条第偶数条扫描线之间进行电性连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路；或者将多条第奇数条扫描线之间进行连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；
对每一扫描线进行开路检测；
将多条第偶数条扫描线之间的电性连接断开或将多条第奇数条扫描线之间的电性连接断开，对每一扫描线进行短路检测。
本申请实施例提供的显示面板的制作方法，通过在制作第一基板的扫描线 的同时在扫描线的两端形成连接多条第奇数条扫描线或连接多条第偶数条扫描线的短路棒，使得间隔的扫描线之间形成电性连接，当在每一扫描线两端加检测信号对其进行开路检测时，相邻两条扫描线之间不会形成电容效应，尤其对于设计而言，即使相邻两条扫描线之间的距离很小，也不会对扫描线的开路检测造成干扰，提高了显示面板的第一基板上扫描线的检测良率以及显示面板的制作良率，避免了后期返工造成时间和成本的浪费。显示面板的制作方法和显示面板的检测方法，能够避免相邻两条扫描线之间形成电容效应，提高对扫描线的开路检测的准确性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的显示面板的制作方法中制作阵列基板的流程图；
图2是本申请实施例提供的显示面板的制作方法中制作阵列基板的步骤a的示意图；
图3是本申请实施例提供的显示面板的制作方法中制作阵列基板的步骤b的示意图；
图4是本申请实施例提供的显示面板的制作方法中制作阵列基板的步骤d的示意图；
图5和图6是本申请实施例提供的制作方法中制作阵列基板的制作方法的步骤e和f的示意图；
图7本申请实施例提供的显示面板的制作方法中制作阵列基板的步骤f'的示意图；
图8和图9是本申请实施例提供的显示面板的制作方法中阵列基板与对置 基板对盒并切割的示意图；
图10是本申请实施例提供的显示面板的一种结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请的技术方案，以下结合具体附图及实施例进行详细说明。
请参阅图1至图6，本申请提供的一种显示面板的制作方法。应理解的是，图1及本实施例中各步骤的序号的顺序并不意味着必定按照该顺序执行，各步骤的执行顺序应基于实际制程而定，不应对本申请实施例的实施过程构成任何限定，在本申请的任意两步骤之间可以包含任何不影响本申请的技术方案实施的其他步骤。本实施例的显示面板的制作方法包括制作第一基板和与第一基板对置的第二基板。在一实施例中，第一基板为阵列基板，具体地，阵列基板的制作包括：
步骤a，请参阅图2，提供第一母板1，第一母板1包括间隔设置的多个第一有效区10，以及围绕于第一有效区10设置的第一切割区11，每一有效区包括第 一显示区101和设于第一显示区外围的第一外围走线区102。
第一母板1为透明基板，如玻璃基板、透明塑料基板等。每一第一有效区10用于形成一阵列基板100(参考图5和图6)，其中，第一显示区101用于形成供显示画面的像素单元，第一外围走线区102用于形成向第一显示区101内的像素单元提供信号的走线，以及用于提供芯片或者电路板等的设置空间。阵列基板100用于形成显示面板900，第一切割区11位于两个第一有效区10之间，也即位于两个显示面板900之间，用于后续切割去掉。
步骤b，请参阅图3，在第一母板1上形成多条平行且间隔设置的扫描线31，以及短路棒32；扫描线31位于第一显示区101并延伸至第一外围走线区102，短路棒32位于第一切割区11，该短路棒32与多条第奇数条扫描线31连接，从而使多条第奇数条扫描线31短路，或者，短路棒32与多条第偶数条扫描线31连接，而使多条第偶数条扫描线31短路。
具体来说，在第一母板1上通过溅射镀膜等方式沉积第一金属材料层，在第一金属材料层上形成光阻层，通过一掩模板对该光阻层进行曝光。该掩模板上具有对应多条扫描线31以及短路棒32的镂空图案区，紫外光通过该镂空图案区对光阻层进行曝光，显影后，光阻层上对应扫描线31和短路棒32的区域保留，其他区域被去除，然后，以该光阻层的图案作为掩模对第一金属材料层进行湿蚀刻，同时得到位于第一有效区10的多条扫描线31，以及位于第一切割区11内的短路棒32，该短路棒与多条第奇数条扫描线31连接，或者与多条第偶数条扫描线31连接。
由第一金属材料层的图案化还同时在第一显示区101内形成了多个栅极51(图3中未示出，参见图6)，栅极51连接至扫描线31。
第一金属材料层可以为铬(Cr)、钼(Mo)、铜(Cu)、钛(Ti)、钼/铝(Mo/Al)复合层或钼/铝/钼(Mo/Al/Mo)复合层等，第一金属材料层的厚度为2000-8000埃，可选为2000-5500埃。
图3中，在第一有效区10的一侧的第一切割区11内形成了短路棒32，该短 路棒32包括垂直于扫描线31设置的短路部321以及连接部322，该连接部322的一端连接于短路部321，另一端连接于一条第奇数条扫描线31或一条第偶数条扫描线31，即，连接部322与奇数条扫描线32一一对应连接，或者与偶数条扫描线31一一对应连接。短路部321将该些连接部322之间连接起来，从而使多条第奇数条扫描线31之间实现短路，或者使多条第偶数条扫描线31之间实现短路。
每一第一有效区10可对应一个或多个短路棒32。并且，每一第一有效区10对应的短路棒32与其他第一有效区10对应的短路棒32之间没有任何电性连接关系，当一个第一有效区10对应设置多个短路棒32时，该多个短路棒32之间可以有电连接关系，也可以没有电连接关系。以下描述均以一个第一有效区10为例对短路棒32进行说明。
在一实施例中，短路部321的数量为一个，该一个短路部321通过多个连接部322同时连接至第一有效区10内的所有第奇数条扫描线31或所有第偶数条扫描线31。
在一实施例中，短路部321的数量为多个，每一短路部321通过多个连接部322与至少两条第偶数条扫描线31或至少两条第奇数条扫描线31连接，如一短路部321通过4个连接部322连接第1、3、5、7条扫描线31，即一短路棒32可以连接4条第奇数条扫描线31，同样地，另一短路棒32可以连接第9、11、13、15条扫描线31……。这样，使得每一奇数条扫描线31都与其他的至少一条奇数条扫描线31实现了连接，或者每一偶数条扫描线31都与其他的至少一条偶数条扫描线31实现了连接。
当然，短路棒32与扫描线31的连接不限于按照奇数顺序连接或者按照偶数顺序连接，还可以是其他连接方式。如一短路棒32与第4条和第6条扫描线31连接，另一短路棒32与第2条和第8条扫描线31连接。
连接部322可以从扫描线31平行延伸而出，从而与短路部321相垂直。当然，连接部322与扫描线31之间也可倾斜连接。本申请对此不作限制。
步骤c，对每一扫描线31进行开路检测。
具体来说，对扫描线的开路检测采用非接触式检测，在扫描线31的一端上方约150μm的位置处，施加200KHz的交流电压，加电位置与扫描线之间形成电容，能够把交流电压的信号传递至扫描线上，最后由扫描线31另一端的接收传感器检出。接收传感器与扫描线31之间也形成电容，由于电信号非常小且为交流信号，可以采用放大器对接收传感器的交流信号进行放大和过滤处理，并将交流信号转化为直流信号进行检测。
由于一扫描线31通过短路棒32连接至间隔的扫描线31，当在每一扫描线31的两侧加信号时，该条扫描线31与相邻的扫描线31之间即使距离过小也不会形成电容效应，不会对信号检测造成干扰，若该条扫描线31存在开路缺陷，则能够检测到信号的异常，从而准确检测到该条扫描线31的开路缺陷，提高了阵列基板的检测良率及制作良率，避免后续阵列基板制作完成或成盒后检测到显示不良而造成返工。
步骤d，如图4所示，将短路棒32与扫描线31之间的电性连接切断，对每一扫描线31进行短路检测。
如图4所示，沿着第一外围走线区102的外边缘，也即第一外围走线区102与第一切割区11之间，用激光切割的方式将扫描线31与连接部322之间切断，使每一扫描线31之间独立设置，不再电性连接，此时，对每一扫描线31进行短路检测。
在其他实施例中，还可以在第一外围走线区102内将扫描线31的两端切断，切断后的扫描线31从第一显示区101延伸至第一外围走线区102内靠近外边缘处。
步骤e，参见图5和图6，于第一有效区10内，在扫描线31上形成栅极绝缘层52、有源层53及源/漏极金属层54，源/漏极金属层54包括源/漏极以及与源极连接的多条平行且间隔设置的数据线4，对数据线4分别进行开路检测和短路检测。
在该步骤e中，采用化学气相沉积法形成栅极绝缘层52，栅极绝缘层52的材料为氧化硅(SiOx)和氮化硅(SiNx)的至少一种。栅极绝缘层52的厚度为1000-3000埃。
采用化学气相沉积法沉积一层非晶硅层，经曝光、显影及蚀刻制程后，得到位于第一显示区101内的有源层53。有源层53包括沟道区以及连接于沟道区两侧的欧姆接触层。
通过溅射镀膜方式在有源层53上沉积第二金属材料层，经曝光、显影及蚀刻制程使该第二金属材料层图案化，得到位于第一显示区101内的源/漏极以及连接于源极并由第一显示区101延伸至第一外围走线区102的多条数据线4。第二金属材料层可以为铬(Cr)、钼(Mo)、铜(Cu)、钛(Ti)、钼/铝(Mo/Al)复合层或钼/铝/钼(Mo/Al/Mo)复合层等，第二金属材料层的厚度为2000-8000埃，具体可以为2000-5500埃。
步骤f，如图6所示，于第一有效区10内，在源/漏极金属层上形成钝化层55，在钝化层55上形成透明导电层，并将该透明导电层图案化得到多个像素电极6；每一第一有效区10内得到一阵列基板100。
由栅极51、栅极绝缘层52、有源层53和源/漏极形成一薄膜晶体管，每一薄膜晶体管连接一像素电极6，构成一个子像素。如图5所示，一行子像素由相邻两条扫描线31驱动，相邻两列子像素同时连接至一条数据线4，由一条数据驱动，成为HSD设计。两行子像素之间的两条扫描线31的距离较小，由于本实施例步骤2和3中通过短路棒32将多条第奇数条扫描线31进行了连接或将多条第偶数条扫描线31进行了连接，实现了对每一扫描线31的开路缺陷进行准确检测。
在一实施例中，本申请提供的显示面板的制作方法中的阵列基板的制作可以制作一种COA(Color on Array，阵列上彩色滤光片)型阵列基板，与第一实施例相同之处为步骤a至e，不再赘述，不同之处在于：
请参阅图7，步骤f'：于第一有效区10内，在源/漏极金属层上形成钝化层 55，在钝化层55上形成彩色色阻层7，在彩色色阻层7上形成平坦层，在平坦层上形成透明导电层，并将该透明导电层图案化得到多个像素电极6，像素电极6经过平坦层和彩色色阻层7上的过孔与漏极连接，每一第一有效区10内得到一阵列基板100。
具体地，形成彩色色阻层7的步骤包括：在钝化层55上沉积红色色阻层并图案化得到红色色阻块71，红色色阻块71对应一像素电极6，得到红色子像素710；在红色色阻块71和钝化层55上沉积绿色色阻层并图案化得到绿色色阻块72，绿色色阻块72对应一像素电极6，得到绿色色阻块72；在红色色阻块71、绿色色阻块72和钝化层55上沉积蓝色色阻层并图案化得到蓝色色阻块73，蓝色色阻块73对应一像素电极6，得到蓝色子像素730，如图7所示。
请参见图8和图9，本申请的显示面板的制作方法还包括制作与阵列基板100相对的第二基板200的步骤以及将阵列基板100与第二基板200对盒并切割的步骤。
在一实施例中，第二基板200为包括彩色色阻层7的彩膜基板，该彩膜基板的步骤具体可包括：
提供第二母板2，第二母板2上包括间隔设置的多个第二有效区20，以及围绕于第二有效区20设置的第二切割区21，第二切割区21是与第一切割区11对应的，同样在后续第一母板1和第二母板2对齐后用于切割去掉。第二有效区20包括第二显示区201和设于第二显示区201外围的第二外围走线区202；第二有效区20与第一有效区10对应，第二切割区21与述第一切割区11对应。于第二有效区20内形成黑矩阵层80、彩色色阻层7以及公共电极层81。在公共电极层81上形成配向层。第二外围走线区202与第一外围走线区201对应，用于形成向公共电极层81提供信号的走线，以及为第一母板1和第二母板2之间设置封装或支撑结构等提供空间。
彩色色阻层7包括多个间隔设置的红色色阻块71、绿色色阻块72和蓝色色阻块73，分别对应阵列基板100上的多个子像素。
彩色色阻层7的形成步骤包括：于第二有效区20内在黑矩阵层80和第一母板1上沉积红色色阻层并图案化得到红色色阻块71，红色色阻块71对应阵列基板100上的一像素电极6；在红色色阻块71和黑矩阵层80上沉积绿色色阻层并图案化得到绿色色阻块72，绿色色阻块72对应阵列基板100上的一像素电极6；在红色色阻块71、绿色色阻块72和黑矩阵层80上沉积蓝色色阻层并图案化得到蓝色色阻块73，蓝色色阻块73对应一阵列基板100上的一像素电极6。
然后，将阵列基板100与第二基板200也即彩膜基板对盒并切割，具体包括：在第一母板1上的第一显示区101内滴入液晶，并在第一外围走线区102内涂覆框胶，将第一母板1与第二母板2对盒后进行紫外照射固化处理，沿第一外围走线区102和第二外围走线区202的外边缘切割第一母板1和第二母板2，得到多个显示面板900，如图8和9所示。
在一实施例中，制作第二基板200具体包括：提供第二母板2，第二母板2上包括间隔设置的多个第二有效区20，以及围绕于第二有效区20设置的第二切割区21，第二有效区20包括第二显示区201和设于第二显示区201外围的第二外围走线区202；第二有效区20与第一有效区10对应，第二切割区21与第一切割区11对应。于第二有效区20内形成公共电极层81，以及在公共电极层81上形成配向层，不再图示。
然后，将阵列基板100与第二基板200进行对盒并切割，得到多个包括COA型阵列基板100的显示面板900。
本申请还提供一种显示面板900，即采用上述所说的显示面板的制作方法制作得到，参考图10所示。
在一实施例中，显示面板900包括阵列基板100和第二基板200，第二基板200可以为包括色阻层的彩膜基板。阵列基板上包括多条扫描线、多条数据线以及多个子像素，每一行子像素由相邻两条所述扫描线驱动，相邻两列所述子像素同时连接至一条所述数据线，成为HSD设计。而在该显示面板900的制作过程中，由于一扫描线31通过短路棒32连接至间隔的扫描线31，当在每一扫描 线31的两侧加信号时，该条扫描线31与相邻的扫描线31之间即使距离过小也不会形成电容效应，不会对信号检测造成干扰，若该条扫描线31存在开路缺陷，则能够检测到信号的异常，从而准确检测到该条扫描线31的开路缺陷，提高了显示面板的检测良率及制作良率，从而有利于保证显示面板900的良率。
本申请还提供一种显示装置(未图示)，包括上述所说的显示面板900，以及设于显示面板900一侧的背光模组。
本申请还提供一种显示面板的检测方法，用于对阵列基板的扫描线的开路缺陷和短路缺陷进行检测，包括：
将多条第偶数条扫描线之间进行电性连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路；或将多条第奇数条扫描线之间进行连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；
对每一扫描线进行开路检测；
将多条第偶数条扫描线之间的电性连接断开或将多条第奇数条扫描线之间的电性连接断开，对每一扫描线进行短路检测。
在一实施例中，多条第偶数条扫描线之间的电性连接或多条第奇数条扫描线之间的电性连接由与扫描线同层设置且同时形成的短路棒实现，即，由一道光刻制程同时形成扫描线和短路棒，短路棒与多条第奇数条扫描线和第偶数条扫描线连接，避免相邻两条扫描线之间形成电容效应，完成开路检测后，将该短路棒与扫描线之间的电性连接通过激光切割法切断，并在完成多个显示面板的制作后将短路棒及其所位于的区域切除。
本申请实施例提供的显示面板的检测方法，实施于上述的显示面板的制作方法的步骤c中，短路棒的制作及特征参见上述实施例的描述，不再赘述。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (18)

  1. 一种显示面板的制作方法，包括制作第一基板，所述制作第一基板包括：
    提供第一母板，所述第一母板包括间隔设置的多个第一有效区，以及围绕于所述第一有效区设置的第一切割区，所述第一有效区包括第一显示区和设于所述第一显示区外围的第一外围走线区；
    在所述第一母板上形成多条间隔设置的扫描线，以及多个短路棒；所述扫描线位于所述第一显示区并延伸至所述第一外围走线区；所述短路棒位于所述第一切割区，所述短路棒与第奇数条扫描线连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路，或者所述短路棒与第偶数条扫描线连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；
    对每一所述扫描线进行开路检测；
    将所述短路棒与所述扫描线之间切断，对所述扫描线进行短路检测；以及
    在所述扫描线上形成绝缘层及第二金属层，所述第二金属层包括多条间隔设置的数据线，对所述数据线进行开路检测和短路检测。
  2. 如权利要求1所述的显示面板的制作方法，其中，沿所述第一外围走线区与所述第一切割区之间将所述短路棒与所述扫描线之间切断。
  3. 如权利要求1所述的显示面板的制作方法，其中，所述短路棒包括短路部以及连接于所述短路部与所述扫描线之间的多个连接部；一所述连接部与一条第奇数条扫描线对应连接，或者一所述连接部与一条第偶数条扫描线对应连接。
  4. 如权利要求3所述的显示面板的制作方法，其中，所述连接部沿所述扫描线平行延伸，所述短路部与所述连接部和扫描线均垂直。
  5. 如权利要求3所述的显示面板的制作方法，其中，所述连接部与所述扫描线倾斜连接。
  6. 如权利要求3所述的显示面板的制作方法，其中，每一所述第一有效区对应一所述短路部；所述短路部与位于该第一有效区内的所有第偶数条扫描线连接，或者所述短路部与位于该第一有效区内的所有第奇数条扫描线连接。
  7. 如权利要求3所述的显示面板的制作方法，其中，每一所述第一有效区对应多个所述短路部；每一所述短路部与多条第偶数条扫描线连接，或者每一所述短路部与多条第奇数条扫描线连接。
  8. 如权利要求5所述的显示面板的制作方法，其中，所述短路部按照奇数顺序连接多条第奇数条扫描线，或者按照偶数顺序连接多条第偶数条扫描线。
  9. 如权利要求1所述的显示面板的制作方法，其中，所述制作第一基板还包括：于所述第一有效区内，在所述第二金属层上形成钝化层；
    在所述钝化层上形成透明导电层，将所述透明导电层图案化得到多个像素电极。
  10. 如权利要求1所述的显示面板的制作方法，其中，所述制作第一基板还包括：于所述第一有效区内，在所述第二金属层上形成所述钝化层；
    在所述钝化层上形成彩色色阻层；
    在所述彩色色阻层上形成平坦层；
    在所述平坦层上形成透明导电层，将所述透明导电层图案化得到多个像素电极。
  11. 如权利要求10所述的显示面板的制作方法，其中，还包括制作与所述第一基板对置的第二基板；所述制作与所述第一基板对置的第二基板包括：
    提供第二母板，所述第二母板包括间隔设置的多个第二有效区，以及围绕于所述第二有效区设置的第二切割区，所述第二有效区包括第二显示区和设于所述第二显示区外围的第二外围走线区；所述第二有效区与所述第一有效区对应，所述第二切割区与所述第一切割区对应；以及
    于所述第二有效区内形成公共电极层。
  12. 如权利要求9所述的显示面板的制作方法，其中，还包括制作与所述第一基板对置的第二基板；所述制作与所述第一基板对置的第二基板包括：
    提供第二母板，所述第二母板上包括间隔设置的多个第二有效区，以及围绕于所述第二有效区设置的第二切割区，所述第二有效区包括第二显示区和设于所述第二显示区外围的第二外围走线区；所述第二有效区与所述第一有效区对应，所述第二切割区与所述第一切割区对应；
    于所述第二母板的第二有效区内形成黑矩阵层；
    于所述黑矩阵层上形成彩色色阻层；以及
    于所述彩色色阻层上形成公共电极层。
  13. 如权利要求11所述的显示面板的制作方法，其中，还包括将所述第一基板与所述第二基板对盒并切割；
    所述将所述第一基板与所述第二基板对盒并切割包括：将所述第一母板与第二母板对盒后进行固化处理，沿所述第一外围走线区和第二外围走线区的外边缘切割所述第一母板和第二母板，得到多个显示面板。
  14. 如权利要求12所述的显示面板的制作方法，其中，还包括将所述第一基板与所述第二基板对盒并切割；
    所述将所述第一基板与所述第二基板对盒并切割包括：将所述第一母板与第二母板对盒后进行固化处理，沿所述第一外围走线区和第二外围走线区的外边缘切割所述第一母板和第二母板，得到多个显示面板。
  15. 一种显示面板的制作方法，包括制作第一基板，其中，所述制作第一基板包括：
    提供第一母板，所述第一母板包括间隔设置的多个第一有效区，以及围绕于所述第一有效区设置的第一切割区，所述第一有效区包括第一显示区和设于所述第一显示区外围的第一外围走线区；
    在所述第一母板上沉积第一金属材料材料层，通过一道光罩制程将该第一 金属材料层图案化同时形成多条平行且间隔设置的扫描线，以及短路棒；所述扫描线位于所述第一显示区并延伸至所述第一外围走线区；所述短路棒位于所述第一切割区，所述短路棒与多条第奇数条扫描线连接，或者所述短路棒与多条第偶数条扫描线连接；所述第一金属材料层的厚度为2000-5500埃；
    对每一所述扫描线采用非接触式检测进行开路检测；
    将所述短路棒与所述扫描线之间切断，对每一所述扫描线进行短路检测；以及
    在所述扫描线上形成绝缘层，在绝缘层上沉积第二金属材料层，将该第二金属材料层图案化形成多条平行且间隔设置的数据线；对所述数据线进行开路检测和短路检测。
  16. 一种显示面板的检测方法，用于对阵列基板的扫描线的开路缺陷和短路缺陷进行检测，包括：
    将多条第奇数条扫描线之间进行电性连接，以使每一第奇数条扫描线与其他至少一第奇数条扫描线之间短路；或者将多条第偶数条扫描线之间进行连接，以使每一第偶数条扫描线与其他至少一第偶数条扫描线之间短路；
    对每一扫描线进行开路检测；
    将多条第偶数条扫描线之间的电性连接断开或将多条第奇数条扫描线之间的电性连接断开，对每一扫描线进行短路检测。
  17. 如权利要求16所述的显示面板的检测方法，其中，多条第偶数条扫描线之间或者多条第奇数条扫描线之间由短路棒连接实现电性连接。
  18. 如权利要求17所述的显示面板的检测方法，其中，所述短路棒与所述扫描线同层设置。
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