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WO2018214277A1 - 显示装置的驱动电路及显示装置 - Google Patents

显示装置的驱动电路及显示装置 Download PDF

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Publication number
WO2018214277A1
WO2018214277A1 PCT/CN2017/094546 CN2017094546W WO2018214277A1 WO 2018214277 A1 WO2018214277 A1 WO 2018214277A1 CN 2017094546 W CN2017094546 W CN 2017094546W WO 2018214277 A1 WO2018214277 A1 WO 2018214277A1
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Prior art keywords
gate
output module
signal output
pixel unit
lines
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PCT/CN2017/094546
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English (en)
French (fr)
Inventor
陈猷仁
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US15/744,250 priority Critical patent/US20190005905A1/en
Publication of WO2018214277A1 publication Critical patent/WO2018214277A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure shows a drive circuit and a display device of the device.
  • the display device can be widely used and studied by being able to visually display characters, numerals, symbols, images, and the like.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the driving of the TFT-LCD is mainly to connect the color resistance compression signal, the control signal and the power through the wire to the connector on the control board through the motherboard, and to pass each data through the timing controller (TCON) on the control board.
  • the flexible circuit board, the source-chip on film (S-COF) and the gate-chip on film (G-COF) are connected to the display area, so that the LCD obtains the required Gate drive signal and data signal.
  • the opening of the TFT in each row/column pixel unit is sequentially controlled by S-COF and G-COF, so that the picture is revealed.
  • the requirements for display screen resolution are getting higher and higher, and the above-mentioned driving method cannot meet the requirements of display image quality.
  • the refresh rate of the display device cannot be further improved due to problems such as the temperature of the COF.
  • the present disclosure provides a driving circuit, a driving method, and a display device of a display device to solve a low screen refresh rate of a display panel, thereby improving display quality.
  • the driving circuit of the display device includes: a first gate signal output module electrically connected to the first pixel unit group through the first group of gate lines;
  • a second gate signal output module electrically connected to the second pixel unit group through the second group of gate lines;
  • the first data signal output module is electrically connected to the first pixel unit group through the first group of data lines, and is configured to output a data signal to the data lines in the first group of data lines;
  • the second data signal output module is electrically connected to the second pixel unit group through the second group of data lines, and is configured to output a data signal to the data lines in the second group of data lines,
  • the first gate signal output module is configured to sequentially output a gate driving signal to the gate lines in the first group of gate lines in each frame display image; the second gate signal output module The method is configured to: when the first gate signal output module sequentially outputs a gate driving signal to a gate line in the first group of gate lines, to a gate line in the second group of gate lines The gate drive signals are sequentially output.
  • the display device provided by the present disclosure includes a display panel and a driving circuit of the above display device.
  • the display device is a liquid crystal display device or an organic light emitting diode display device.
  • the present disclosure also provides another display device including a display panel and a driving circuit.
  • the display panel includes: m gate lines including i first gate lines and j second gate lines; 2n data lines including n first data lines, n second data lines, and m Rows of pixel cells in n columns,
  • the driving circuit includes: a first gate signal output module electrically connected to the i first gate lines; and a second gate signal output module electrically connected to the j first gate lines; a data signal output module electrically connected to the n first data lines; and a second data signal output module electrically connected to the n second data lines.
  • FIG. 1 is a block diagram showing the basic structure of a driving circuit of a display device according to an embodiment of the present disclosure
  • 2A is a flowchart of a driving method of a driving circuit of a display device according to an embodiment of the present disclosure
  • 2B is a timing chart of charging of a driving method of a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display area in a display device according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of dividing a display area pixel unit group by a row in a display device according to an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of dividing a display area pixel unit group by columns in a display device according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a display device and a driving circuit thereof according to an embodiment of the present disclosure
  • FIG. 7 is a driving structural diagram of a thin film transistor liquid crystal display according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another display device according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of another display device according to an embodiment of the present disclosure.
  • Fig. 11 is a timing chart showing the driving of the display device of Fig. 10.
  • FIG. 1 is a structural block diagram of a driving circuit of a display device according to an embodiment of the present disclosure. As shown in FIG. 1 , the driving circuit includes a first gate signal output module 11 , a second gate signal output module 12 , a first data signal output module 21 , and a second data signal output module 22 .
  • a display panel of a Thin Film Transistor Liquid Crystal Display includes a display area and a non-display area.
  • a trace, a detection point, a driving circuit, and the like may be disposed in the non-display area, and the display area has a plurality of gate lines and a plurality of data lines arranged in a cross, and a plurality of pixel units arranged in a row and a column.
  • the gate is in the pixel unit, and a Thin Film Transistor (TFT) is used as a pixel switch.
  • the gate driving circuit sequentially outputs gate driving signals to the plurality of gate line gates, and each row of gate lines transmits the gate driving signals to the gates of the TFTs of the corresponding row of pixel units, so that the TFTs are turned on.
  • the storage capacitance of the pixel unit is charged through the data line via the turned-on TFT to write a gray scale voltage.
  • the storage capacitor continues to maintain the gray scale voltage until the TFT of the pixel unit is turned on again, and the gray scale voltage is updated to update the display screen.
  • the driving circuit of the display device of the embodiment of the present disclosure is for driving the display area 100 for image display.
  • the display area has a plurality of data lines and a plurality of scanning lines electrically connected to the plurality of pixel units.
  • the first gate signal output module 11 of the driving circuit is electrically connected to the first pixel unit group through the first group of gate lines, and is arranged to sequentially output gate driving signals to the first group of gate lines.
  • the second gate signal output module 12 is electrically connected to the second pixel unit group through the second group of gate lines, and is configured to sequentially output the gate driving signals to the second group of gate lines.
  • the first data signal output module 21 is electrically connected to the first pixel unit group through the first group of data lines, and is arranged to sequentially output the data signals to the first group of data lines.
  • the second data signal output module 22 is electrically connected to the second pixel unit group through the second data line, and is configured to sequentially output the data signal to the second data line.
  • the first gate signal output module 11 and the second gate signal output module 12 simultaneously output gate drive signals
  • the first data signal output module 21 and the second data signal output module 22 simultaneously output data signals.
  • the first gate signal output module is electrically connected to the first pixel unit group through the first gate line
  • the second gate signal output module passes through the second gate line and the second
  • the pixel unit group is electrically connected
  • the data signal output module is electrically connected to the first pixel unit group through the first data line
  • the second data signal output module is electrically connected to the second pixel unit group through the second data line, and displays the image in each frame.
  • the gate driving signal and the data signal are simultaneously outputted to the first pixel unit group and the second pixel unit group, thereby reducing the scanning time of the display image per frame, improving the refresh rate of the display device, and further improving the display quality of the display screen.
  • FIG. 2A is a flowchart of a driving method of a driving circuit of a display device according to an embodiment of the present disclosure, the driving method includes:
  • the first gate signal output module sequentially outputs a gate driving signal to the first group of gate lines
  • the second gate signal output module sequentially outputs a gate to the second group of gate lines.
  • the first data signal output module outputs a data signal to the first group of data lines
  • the second data signal output module outputs a data signal to the second group of data lines.
  • FIG. 2B is a charging timing diagram of a driving method of a display panel according to an embodiment of the present disclosure.
  • the first gate signal output module 11 and the second gate signal output module 12 simultaneously output the gate drive signals S1 and S2, so that the first gate signal output module 11 is sequentially Outputting a gate driving signal to the first group of gate lines, and the second gate signal outputting module 12 sequentially outputting a gate driving signal to the second group of gate lines, and the first pixel electrically connected to the first group of gate lines Single The tuple and the TFTs in the second pixel unit group electrically connected to the second group of gate lines are simultaneously turned on at the same time.
  • the first data signal output module 21 and the second data signal output module 22 simultaneously output the data signals D1 and D2 such that the first data signal output module 21 outputs a data signal to the first group of data signal lines, and the second data signal output module 22
  • the second group of data signal lines outputs a data signal, and at this time, sequentially writes to the TFTs in the first pixel unit group electrically connected to the first group of data signal lines and the second pixel unit group electrically connected to the second group of data signal lines. Enter the pixel grayscale voltage. In this way, the TFTs of the pixel units of two or two columns are simultaneously turned on, and the gray scale voltage of the pixels is simultaneously written, thereby improving the refresh rate of the display screen.
  • a driving circuit of a display device is electrically connected to a pixel unit of a display device through a gate line and a data line.
  • the first gate signal output module 11 of the driving circuit is electrically connected to the first pixel unit group through the first gate line
  • the second gate signal output module 12 passes through the second gate line and the second pixel unit.
  • the first data signal output module 21 is electrically connected to the first pixel unit group through the first group of data lines
  • the second data signal output module 22 is electrically connected to the second pixel unit group through the second group of data lines.
  • the first pixel unit group may be an odd row pixel unit
  • the second pixel unit group may be an even row pixel unit.
  • FIG. 3 is a schematic structural diagram of a display area in a display device according to an embodiment of the present disclosure.
  • M is an odd number, as shown in FIG. 3, the first group of gate lines S11, S12, ..., S1N-1, S1N are sequentially electrically connected to the odd-numbered rows of pixel units, and the first group of data lines D11, D12, D13, ...
  • D1n is electrically connected to odd-numbered row pixel units of each column in turn, where the odd-numbered row of pixel units is the first pixel unit group;
  • the second group of gate lines S21, S22, ..., S2N-1 are sequentially and even-numbered rows of pixel units Connected, the second set of data lines D21, D22, D23, ..., D2n are electrically connected to the even-numbered row of pixel units of each column, where the even-numbered rows of pixel units are the second pixel unit group, where N is (M+1) )/2.
  • the first gate signal output module is electrically connected to the odd-numbered row of pixel units through the first group of gate lines S11, S12, . . .
  • the first data signal output module passes the first group.
  • the data lines D11, D12, D13, ..., D1n are sequentially electrically connected to the odd-line pixel units of each column; the second gate signal output module sequentially and even-numbered lines through the second group of gate lines S21, S22, ..., S2N-1
  • the pixel unit is electrically connected, and the second data signal output module is electrically connected to the even-numbered row of pixel units of each column through the second group of data lines D21, D22, D23, ..., D2n.
  • the number of rows M of the pixel unit may also be an even number, and the connection mode and the driving principle are similar to those when M is an odd number, and details are not described herein again.
  • each odd-line pixel unit simultaneously opens and writes a data signal to the TFT of the even-numbered row pixel unit immediately below it.
  • the TFTs in the first row of pixel cells electrically connected to the gate line S11 and the TFTs in the second row of pixel cells electrically connected to the gate line S21 are simultaneously turned on, and then the odd and even rows are sequentially passed through the data lines.
  • the pixel unit writes the data signal such that the first row of pixel cells and the second row of pixel cells simultaneously display pixel grayscales.
  • the first pixel unit group and the second pixel unit group are further divided into two regions according to a row or a column of the pixel unit in the display region of the display device, that is, the first pixel unit group may be the first N rows of pixel units. Or the first N columns of pixel units, and the second group of pixel units may be the last M rows of pixel cells or the last M columns of pixel cells.
  • FIG. 4 is a schematic structural diagram of dividing a display area pixel unit group by a row in a display device according to an embodiment of the present disclosure.
  • the display area of the display device has N+M rows and n columns of pixel units.
  • the first group of gate lines S11, S12, ..., S1N-1, S1N are sequentially electrically connected to the first N rows of pixel units, and the first group of data lines D11, D12, ..., D1n-1, D1n are sequentially connected to the first N rows.
  • the column pixel units are electrically connected; the second group of gate lines S21, S22, S23, ..., S2M are sequentially electrically connected to the rear M rows of pixel units, and the second group of data lines D21, D22, ..., D2n-1, D2n are sequentially followed by Each column of pixel cells of the M row is electrically connected.
  • the first N rows of pixel units are the first pixel unit 41, and the last M rows of pixel units are the second pixel unit group 42.
  • the first gate signal output module is electrically connected to the first N rows of pixel units in sequence through the first group of gate lines S11, S12, . . .
  • S1N-1, S1N, and the first data signal output module passes through the first group of data lines.
  • D11, D12, ..., D1n-1, D1n are sequentially electrically connected to each column of pixel units of the first N rows;
  • the second gate signal output module is sequentially and subsequently passed through the second group of gate lines S21, S22, S23, ..., S2M
  • the M rows of pixel cells are electrically connected, and the second data signal output module is electrically connected to each column of pixel cells of the last M rows by the second set of data lines D21, D22, ..., D2n-1, D2n.
  • the first gate signal output module opens the TFT of the first row of pixel units through the gate line S11, while the second gate signal output module turns on the N+1 through the gate line S21.
  • One row of pixel units writes corresponding grayscale voltages such that the first row of pixel cells and the (N+1th)th row of pixel cells simultaneously display pixel grayscales.
  • the pixel gray scale display principle of the remaining row pixel units is similar to this, and will not be described herein.
  • FIG. 5 is a schematic structural diagram of dividing a display area pixel unit group by columns in a display device according to an embodiment of the present disclosure. Wherein, the display area of the display device has n rows of N+M column pixel units.
  • the first set of gate lines S11, S12, ..., S1n-1, S1n are sequentially electrically connected to the first N columns of pixel cells of each row, and the first set of data lines D11, D12, ..., D1n-1, D1n are sequentially and front N
  • the first N columns of pixel units are the first pixel unit 51, and the last M columns of pixel units are the second pixel unit group 52.
  • the first gate signal output module is electrically connected to the first N columns of pixel units of each row through the first group of gate lines S11, S12, ..., S1n-1, S1n, and the first data signal output module passes the first The group data lines D11, D12, ..., D1n-1, D1n are sequentially electrically connected to the first N columns of pixel units;
  • the second gate signal output module is sequentially passed through the second group of gate lines S21, S22, ..., S2n-1, S2n Electrically connected to the rear M columns of pixel units of each row, and the second data signal output module passes through the second set of data lines D21, D22, ..., D2M-1 and D2M are electrically connected to the rear M columns of pixel units in sequence.
  • the driving principle is similar to that in the case of row division, and will not be described here.
  • the gate lines extend along the first direction and are arranged along the second direction
  • the data lines extend along the second direction and are arranged along the first direction.
  • the first direction here may be the same direction as the row of the pixel unit
  • the second direction may be the same direction as the column of the pixel unit.
  • FIG. 6 is a schematic structural diagram of a display device and a driving circuit thereof according to an embodiment of the present disclosure.
  • the first gate signal output module 11 and the second gate signal output module 12 are disposed on both sides of the display device in the first direction, and the first direction in FIG. 6 is the row direction of the pixel unit.
  • the left side of the display area 100 is the first gate signal output module 11 and the right side is the second gate signal output module 12.
  • the first data signal output module 21 and the second data signal output module 22 are disposed on both sides of the display device in the second direction.
  • the display area 100 is above.
  • the first data signal output module 21 and the second data signal output module 22 are below.
  • FIG. 7 is a driving structural diagram of a thin film transistor liquid crystal display provided by an embodiment of the present disclosure.
  • the first gate signal output module 11 is disposed on the first gate flip chip region 71
  • the second gate signal output module 12 is disposed on the second gate flip chip region 72
  • the output module 21 is disposed on the first source flip chip region 73
  • the second data signal output module 22 is disposed on the second source flip chip region 74.
  • the signal output module is disposed in the flip chip area to realize the setting of the narrow border of the display panel.
  • the first source flip chip region 73 may be electrically connected to the first flexible circuit board 75
  • the second source flip chip region 74 may be electrically connected to the second flexible circuit board 76.
  • the first flexible circuit board 75 and the second flexible circuit board 76 are connected to the system main board 78 through a flexible flat cable 77 (FFC), and a timing control signal or the like is issued by the system main board, so that the display area of the display device is displayed correspondingly. Picture.
  • FFC flexible flat cable 77
  • FIG. 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device 80 includes a display panel 82 and a driving circuit 81 of the display device provided by the embodiment of the present disclosure.
  • the display panel 82 includes a plurality of gate lines 823 and a plurality of data lines 822.
  • the plurality of scan lines 823 are intersected with the plurality of data lines 822 to form a plurality of pixel units.
  • display device 80 can be, for example, an LCD display device, an OLED display device, a QLED display device, a curved display device, or other display device.
  • the present disclosure also provides another display device.
  • the display device includes a display panel and a driving circuit.
  • the display panel includes: m gate lines, 2n data lines, and m*n pixel units.
  • a plurality of pixel units are arranged in an array of m rows and n columns.
  • Each pixel unit includes a thin film transistor.
  • the driving circuit includes a first gate signal output module, a second gate signal output module, a first data signal output module, and a second data signal output module.
  • the m gate lines are in one-to-one correspondence with the m rows of the pixel unit array.
  • Each of the gate lines is electrically connected to a gate of n pixel unit thin film transistors of a corresponding row.
  • the m gate lines include i gate lines, first gate lines, and j second gate lines.
  • the i first gate lines are electrically connected to the first gate signal output module, and the j second gate lines are electrically connected to the second gate signal output module.
  • the 2n data lines include n first data lines and n second data lines.
  • the n first data lines are electrically connected to the first data signal output module.
  • the n second data lines are electrically connected to the second data signal output module.
  • Each column of pixel units corresponds to one first data line and one second data line.
  • the source of the thin film transistor of the i pixel unit is electrically connected to the corresponding first data line
  • the source of the thin film transistor of the j pixel unit is electrically connected to the corresponding second data line.
  • the first gate signal output module sequentially outputs a gate driving signal to the i first gate lines
  • the first gate signal output module is disposed to sequentially to the i First grid While the polar line outputs the gate driving signal
  • the second gate signal output module sequentially outputs the gate signals to the j second gate lines.
  • the i first pixel unit groups are i rows of the pixel unit array, and the j two pixel unit groups are the remaining j rows of the pixel unit array.
  • Fig. 9 shows an example of a display device. As shown in FIG. 9, the display device includes a display panel 100 and a driving circuit.
  • the driving circuit includes a first gate signal output module 11, a second gate signal output module 12, a first data signal output module 21, and a second data signal output module 22.
  • the display panel 100 includes four gate lines, six data lines, and twelve pixel units.
  • the 12 pixel units are arranged in an array of 4 rows and 3 columns.
  • the four gate lines include a gate line G1, a gate line G2, a gate line G3, and a gate line G4.
  • the gate line G1 and the gate line G3 are the first gate lines, and the gate line G2 and the gate line G4 are the second gate lines.
  • the six data lines include a data line D11, a data line D12, a data line D13, a data line D21, a data line D22, and a data line D23.
  • the data line D11, the data line D12, and the data line D13 are first data lines, and the data line D21, the data line D22, and the data line D23 are second data lines.
  • the gate line G1 and the gate line G3 are electrically connected to the first gate signal output module 11, respectively.
  • the gate line G2 and the gate line G4 are electrically connected to the second gate signal output module 12, respectively.
  • the data line D11, the data line D12, and the data line D13 are electrically connected to the first data signal output module 21, respectively.
  • the data line D21, the data line D22, and the data line D23 are electrically connected to the second data signal output module 22, respectively.
  • Each of the pixel units is provided with a thin film transistor having a source, a drain and a gate.
  • 12 pixel units include pixel unit P11, pixel unit P12, pixel unit P13, pixel list The element P21, the pixel unit P22, the pixel unit P23, the pixel unit P31, the pixel unit P32, the pixel unit P33, the pixel unit P41, the pixel unit P42, and the pixel unit P43.
  • the gates of the thin film transistors of the pixel units (pixel unit P11, pixel unit P12, and pixel unit P13) of the first row are electrically connected to the gate line G1, and the source is electrically connected to the data line D11, the data line D12, and the data line D13, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P21, pixel unit P22, and pixel unit P23) of the second row are all electrically connected to the gate line G2, and the source is electrically connected to the data line D21, the data line D22, and the data line D23, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P31, pixel unit P32, and pixel unit P33) of the third row are all electrically connected to the gate line G3, and the source is electrically connected to the data line D11, the data line D12, and the data line D13, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P41, pixel unit P42, and pixel unit P43) of the fourth row are all electrically connected to the gate line G4, and the sources are electrically connected to the data line D21, the data line D22, and the data line D23, respectively. .
  • the first gate signal output module 11 outputs a gate driving signal to the gate line G1
  • the second gate signal output module 12 outputs a gate driving signal to the gate line G2
  • the first data signal output module 21 outputs data signals to the pixel units (pixel unit P11, pixel unit P12, and pixel unit P13) of the first row through the data lines D11, D12, and D13, respectively
  • the second data line signal output module 22 passes the data lines D21, D22, and D23.
  • Data signals are output to the pixel units of the second row (pixel unit P21, pixel unit P22, and pixel unit P23), respectively.
  • the pixel unit of the first row and the pixel unit of the second row are simultaneously driven.
  • the first gate signal output module 11 outputs a gate driving signal to the gate line G3, and the second gate signal output module 12 outputs a gate driving signal to the gate line G4, and the first data signal is output.
  • the module 21 outputs data signals to the pixel units (pixel unit P31, pixel unit P32, and pixel unit P33) of the third row through the data lines D11, D12, and D13, respectively, and the second data line signal output module 22 passes through the data lines D21, D22, and D23 outputs data signals to the pixel units (pixel unit P41, pixel unit P42, and pixel unit P43) of the second row, respectively.
  • the pixel unit of the third row and the pixel unit of the fourth row are simultaneously driven.
  • Fig. 10 shows another example of the display device.
  • the display device includes a display panel 100 and a driving circuit.
  • the driving circuit includes a first gate signal output module 11, a second gate signal output module 12, a first data signal output module 21, and a second data signal output module 22.
  • the display panel 100 includes five gate lines, six data lines, and 15 pixel units.
  • the 15 pixel units are arranged in an array of 5 rows and 3 columns.
  • the five gate lines include a gate line G1, a gate line G2, a gate line G3, a gate line G4, and a gate line G5.
  • the gate line G1, the gate line G3, and the gate line G5 are first gate lines, and the gate line G2 and the gate line G4 are second gate lines.
  • the six data lines include a data line D11, a data line D12, a data line D13, a data line D21, a data line D22, and a data line D23.
  • the data line D11, the data line D12, and the data line D13 are first data lines, and the data line D21, the data line D22, and the data line D23 are second data lines.
  • the first gate lines (the gate line G1, the gate line G3, and the gate line G5) are electrically connected to the first gate signal output module 11, respectively.
  • the second gate lines (the gate line G2 and the gate line G4) are electrically connected to the second gate signal output module 12, respectively.
  • the first data lines (data line D11, data line D12, and data line D13) are electrically connected to the first data signal output module 21, respectively.
  • the second data lines (data line D21, data line D22, and data line D23) are electrically connected to the second data signal output module 22, respectively.
  • Each pixel unit is provided with a thin film transistor having a source, a drain, and Gate.
  • 15 pixel units include pixel unit P11, pixel unit P12, pixel unit P13, pixel unit P21, pixel unit P22, pixel unit P23, pixel unit P31, pixel unit P32, pixel unit P33, pixel unit P41, pixel unit P42, pixel The unit P43, the pixel unit P51, the pixel unit P52, and the pixel unit P53.
  • the gates of the thin film transistors of the pixel units (pixel unit P11, pixel unit P12, and pixel unit P13) of the first row are electrically connected to the gate line G1, and the source is electrically connected to the data line D11, the data line D12, and the data line D13, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P21, pixel unit P22, and pixel unit P23) of the second row are all electrically connected to the gate line G2, and the source is electrically connected to the data line D21, the data line D22, and the data line D23, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P31, pixel unit P32, and pixel unit P33) of the third row are all electrically connected to the gate line G3, and the source is electrically connected to the data line D11, the data line D12, and the data line D13, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P41, pixel unit P42, and pixel unit P43) of the fourth row are all electrically connected to the gate line G4, and the sources are electrically connected to the data line D21, the data line D22, and the data line D23, respectively. .
  • the gates of the thin film transistors of the pixel units (pixel unit P51, pixel unit P52, and pixel unit P53) of the fifth row are all electrically connected to the gate line G5, and the sources are electrically connected to the data line D11, the data line D12, and the data line D13, respectively.
  • Fig. 11 is a timing chart showing the display device displaying one frame of image.
  • the display device In order to display one frame of image, the display device requires time T.
  • the time T can be divided into three time periods t11, t12 and t13.
  • the time T is also divided into two time periods t21 and t22.
  • the first gate signal output module 11 outputs a gate driving signal to the gate line G1.
  • the first data signal output module 21 outputs data signals to the pixel units (pixel unit P11, pixel unit P12, and pixel unit P13) of the first row through the data lines D11, D12, and D13, respectively.
  • the first gate signal output module 11 outputs a gate driving signal to the gate line G3, and the first data signal output module 21 respectively goes to the pixel unit of the third row through the data lines D11, D12 and D13 (pixel unit P31, pixel unit P32, and pixel unit P33) output data signals.
  • the first gate signal output module 11 outputs a gate driving signal to the gate line G5, and the first data signal output module 21 respectively goes to the pixel unit of the fifth row through the data lines D11, D12 and D13 (pixel unit P51).
  • the pixel unit P52 and the pixel unit P53) output a data signal.
  • the second gate signal output module 12 outputs a gate driving signal to the gate line G2, and the second data signal output module 22 respectively goes to the pixel unit of the second row through the data lines D21, D22 and D23 (pixel unit P21, pixel unit P22, and pixel unit P23) output a data signal.
  • the second gate signal output module 12 outputs a gate driving signal to the gate line G2, and the second data signal output module 22 respectively goes to the pixel unit of the fourth row through the data lines D21, D22 and D23 (pixel unit P41, pixel unit P42, and pixel unit P43) output data signals.
  • the display device of the present embodiment reduces the scan time of each frame of image and improves the refresh rate of the display device.

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Abstract

一种显示装置（80）的驱动电路（81）及显示装置（80），该驱动电路（81）的第一栅极信号输出模块（11）通过第一栅极线与第一像素单元组电连接，第二栅极信号输出模块（12）通过第二栅极线与第二像素单元组电连接，第一数据信号输出模块（21）通过第一数据线与第一像素单元组电连接，第二数据信号输出模块（22）通过第二数据线与第二像素单元组电连接，且在每帧显示图像中，同时向第一像素单元组与第二像素单元组输出栅极驱动信号和数据信号。

Description

显示装置的驱动电路及显示装置 技术领域
本公开显示装置的驱动电路及显示装置。
背景技术
显示装置能够直观地显示文字、数字、符号、图像等，而被广泛地应用和研究。薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)作为当前平板显示的主要品种之一，已经成为了现代IT、视讯产品中重要的显示平台。
TFT-LCD的驱动主要是通过系统主板将色阻压缩信号、控制信号及动力通过线材与控制板上的连接器相连接，并将各数据经控制板上的时序控制器(Timing Controller，TCON)经柔性电路板、源极覆晶薄膜(Source-Chip on Film，S-COF)和栅极覆晶薄膜(Gate-Chip on Film，G-COF)与显示区连接，从而使得LCD获得所需的栅极驱动信号和数据信号。相关技术中，通过S-COF和G-COF依次控制每行/列像素单元中TFT的打开，从而使得画面得以显现。
但是，随着显示技术的发展，对显示画面分辨率的要求越来越高，上述的驱动方式已无法满足显示画质的要求。同时由于COF的温度等问题，显示装置的刷新率无法进一步提高。
发明内容
本公开提供一种显示装置的驱动电路、驱动方法及显示装置，以解决显示面板的画面刷新率较低，从而提高显示质量。
本公开提供的显示装置的驱动电路，包括：第一栅极信号输出模块，通过第一组栅极线与第一像素单元组电连接；
第二栅极信号输出模块，通过第二组栅极线与第二像素单元组电连接；
第一数据信号输出模块，通过第一组数据线与所述第一像素单元组电连接，并设置为向所述第一组数据线中的数据线输出数据信号；以及
第二数据信号输出模块，通过第二组数据线与所述第二像素单元组电连接，并设置为向所述第二组数据线中的数据线输出数据信号，
其中，在每帧显示图像中，所述第一栅极信号输出模块设置为向所述第一组栅极线中的栅极线依次输出栅极驱动信号；所述第二栅极信号输出模块设置为：在所述第一栅极信号输出模块向所述第一组栅极线中的栅极线依次输出栅极驱动信号的同时，向所述第二组栅极线中的栅极线依次输出栅极驱动信号。
本公开提供的显示装置，包括显示面板、以及上述的显示装置的驱动电路。
所述显示装置为液晶显示装置或者有机发光二极管显示装置。
本公开还提供另一种显示装置，包括显示面板和驱动电路。
所述显示面板包括：m条栅极线，包括i条第一栅极线和j条第二栅极线；2n条数据线，包括n条第一数据线、n条第二数据线以及m行n列的像素单元阵列，
所述驱动电路包括：第一栅极信号输出模块，与所述i条第一栅极线电连接；第二栅极信号输出模块，与所述j条第一栅极线电连接；第一数据信号输出模块，与所述n条第一数据线电连接；以及第二数据信号输出模块，与所述n条第二数据线电连接。
所述像素单元阵列包括i个第一像素单元组和j个第二像素单元组；每个第一像素单元组与i条第一栅极线中的对应一条电连接，并与n条第一数据线电连接；每个第二像素单元组与j条第二栅极线中的对应一条电连接，并与n条第二数据线 电连接，其中，i、j、m、n均为大于1的正整数，并且i+j＝m。
附图说明
图1是本公开实施例提供的显示装置的驱动电路的基本结构框图；
图2A是本公开实施例提供的显示装置的驱动电路的驱动方法的流程图；
图2B是本公开实施例提供的一种显示面板的驱动方法的充电时序图；
图3是本公开实施例提供的显示装置中显示区域的结构示意图；
图4为本公开实施例提供的显示装置中以行划分显示区域像素单元组的结构示意图；
图5是本公开实施例提供的显示装置中以列划分显示区域像素单元组的结构示意图；
图6是本公开实施例提供的一种显示装置及其驱动电路的结构示意图；
图7是本公开实施例提供的一种薄膜晶体管液晶显示器的驱动结构图；
图8是本公开实施例提供的一种显示装置的结构示意图；
图9是本公开实施例提供的另一种显示装置的结构示意图；
图10是本公开实施例提供的另一种显示装置的结构示意图；以及
图11是图10中的显示装置的驱动时序图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
本公开提供一种显示装置的驱动电路。图1是本公开实施例提供的显示装置的驱动电路的结构框图。如图1所示，该驱动电路包括：第一栅极信号输出模块11、第二栅极信号输出模块12、第一数据信号输出模块21、以及第二数据信号输出模块22。
示例性的，薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)的显示面板包括显示区域和非显示区域。通常在非显示区域中可设置走线、检测点、以及驱动电路等，而显示区域具有交叉设置的多条栅极线和多条数据线，以及行列排布的多个像素单元。栅极在像素单元中，薄膜晶体管(Thin Film Transistor，TFT)作为像素开关。栅极驱动电路依次向多条栅极线栅极输出栅极驱动信号，每行栅极线将栅极驱动信号传递到对应一行像素单元的TFT的栅极，使得TFT被导通，此时，通过数据线经由导通的TFT对像素单元的储存电容充电，以写入一灰阶电压。当TFT被关闭后，存储电容继续维持该灰阶电压，直至该像素单元的TFT再次被开启时，才会更新灰阶电压，从而更新显示画面。
由此，本公开实施例显示装置的驱动电路用于驱动显示区域100进行图像显示。该显示区域中具有多条数据线和多条扫面线与多个像素单元电连接。该驱动电路中第一栅极信号输出模块11通过第一组栅极线与第一像素单元组电连接，设置为向第一组栅极线依次输出栅极驱动信号。第二栅极信号输出模块12通过第二组栅极线与第二像素单元组电连接，设置为向第二组栅极线依次输出栅极驱动信号。第一数据信号输出模块21通过第一组数据线与第一像素单元组电连接，设置为向第一组数据线依次输出数据信号。第二数据信号输出模块22通过第二数据线与第二像素单元组电连接，设置为向第二数据线依次输出数据信号。
在每帧显示图像中，第一栅极信号输出模块11和第二栅极信号输出模块12同时输出栅极驱动信号，第一数据信号输出模块21和第二数据信号输出模块22同时输出数据信号。
本公开实施例提供的显示装置的驱动电路中第一栅极信号输出模块通过第一栅极线与第一像素单元组电连接，第二栅极信号输出模块通过第二栅极线与第二像素单元组电连接，数据信号输出模块通过第一数据线与第一像素单元组电连接，第二数据信号输出模块通过第二数据线与第二像素单元组电连接，且在每帧显示图像中，同时向第一像素单元组与第二像素单元组输出栅极驱动信号和数据信号，从而减少每帧显示图像的扫描时间，提高显示装置的刷新率，进一步提高显示画面的显示质量。
该显示装置的驱动电路通过将显示区域100中各个像素单元中TFT的开启以更新显示画面，该驱动电路的驱动方法如图2A所示。图2A是本公开实施例提供的显示装置的驱动电路的驱动方法的流程图，该驱动方法包括：
S201、在每帧显示图像中，第一栅极信号输出模块依次向第一组栅极线输出栅极驱动信号，同时，第二栅极信号输出模块依次向第二组栅极线输出栅极驱动信号；
S202、第一数据信号输出模块向第一组数据线输出数据信号，同时第二数据信号输出模块向第二组数据线输出数据信号。
示例性的，图2B是本公开实施例提供的一种显示面板的驱动方法的充电时序图。如图2B所示，在每帧显示图像中，第一栅极信号输出模块11和第二栅极信号输出模块12同时输出栅极驱动信号S1和S2，使得第一栅极信号输出模块11依次向第一组栅极线输出栅极驱动信号，第二栅极信号输出模块12依次向第二组栅极线输出栅极驱动信号，此时与第一组栅极线电连接的第一像素单 元组和与第二组栅极线电连接的第二像素单元组中的TFT同时依次开启。第一数据信号输出模块21和第二数据信号输出模块22同时输出数据信号D1和D2，使得第一数据信号输出模块21向第一组数据信号线输出数据信号，第二数据信号输出模块22向第二组数据信号线输出数据信号，此时同时依次向与第一组数据信号线电连接的第一像素单元组和与第二组数据信号线电连接的第二像素单元组中的TFT写入像素灰阶电压。以此，使得两行或两列的像素单元的TFT同时开启，并同时写入像素灰阶电压，进而提高显示画面的刷新率。
本公开实施例提供的显示装置的驱动电路通过栅极线和数据线与显示装置的像素单元电连接。参照图1，该驱动电路的第一栅极信号输出模块11通过第一栅极线与第一像素单元组电连接，第二栅极信号输出模块12通过第二栅极线与第二像素单元组电连接，第一数据信号输出模块21通过第一组数据线与第一像素单元组电连接，第二数据信号输出模块22通过第二组数据线与第二像素单元组电连接。其中，第一像素单元组可以为奇数行像素单元，第二像素单元组可以为偶数行像素单元。
图3是本公开实施例提供的显示装置中显示区域的结构示意图。其中，显示装置的显示区域中有M行n列像素单元。当M为奇数时，如图3所示，第一组栅极线S11、S12、…、S1N-1、S1N依次与奇数行像素单元电连接，第一组数据线D11、D12、D13、…、D1n依次与每列的奇数行像素单元电连接，此处奇数行像素单元即为第一像素单元组；第二组栅极线S21、S22、…、S2N-1依次与偶数行像素单元电连接，第二组数据线D21、D22、D23、…、D2n依次与每列的偶数行像素单元电连接，此处偶数行像素单元即为第二像素单元组，其中，N为(M+1)/2。此时，第一栅极信号输出模块通过第一组栅极线S11、S12、…、S1N-1、S1N依次与奇数行像素单元电连接，第一数据信号输出模块通过第一组 数据线D11、D12、D13、…、D1n依次与每列的奇数行像素单元电连接；第二栅极信号输出模块通过第二组栅极线S21、S22、…、S2N-1依次与偶数行像素单元电连接，第二数据信号输出模块通过第二组数据线D21、D22、D23、…、D2n依次与每列的偶数行像素单元电连接。此外，像素单元的行数M也可以为偶数，其连接方式及驱动原理与M为奇数时相类似，在此不再赘述。
此时，在每帧显示图像中，每一奇数行像素单元均与其下方紧邻的偶数行像素单元的TFT同时打开和写入数据信号。例如，与栅极线S11电连接的第一行像素单元中的TFT和与栅极线S21电连接的第二行像素单元中的TFT同时打开，再通过数据线依次为奇数行和偶数行的像素单元写入数据信号，使得第一行像素单元和第二行像素单元同时显示像素灰阶。
可选的，第一像素单元组与第二像素单元组在显示装置的显示区域中还可以根据像素单元的行或列分为两个区域，即第一像素单元组可以为前N行像素单元或前N列像素单元，而第二像素单元组可以为后M行像素单元或后M列像素单元。
参照图4，图4为本公开实施例提供的显示装置中以行划分显示区域像素单元组的结构示意图。其中，显示装置的显示区域中有N+M行n列像素单元。第一组栅极线S11、S12、…、S1N-1、S1N依次与前N行像素单元电连接，第一组数据线D11、D12、…、D1n-1、D1n依次与前N行的每列像素单元电连接；第二组栅极线S21、S22、S23、…、S2M依次与后M行像素单元电连接，第二组数据线D21、D22、…、D2n-1、D2n依次与后M行的每列像素单元电连接。此处，前N行像素单元即为第一像素单元41，后M行像素单元即为第二像素单元组42。此时，第一栅极信号输出模块通过第一组栅极线S11、S12、…、S1N-1、S1N依次与前N行像素单元电连接，第一数据信号输出模块通过第一组数据线 D11、D12、…、D1n-1、D1n依次与前N行的每列像素单元电连接；第二栅极信号输出模块通过第二组栅极线S21、S22、S23、…、S2M依次与后M行像素单元电连接，第二数据信号输出模块通过第二组数据线D21、D22、…、D2n-1、D2n依次与后M行的每列像素单元电连接。
示例性的，在每帧显示图像中，第一栅极信号输出模块通过栅极线S11打开第一行像素单元的TFT，同时第二栅极信号输出模块通过栅极线S21打开第N+1行像素单元的TFT，而第一数据信号输出模块通过第一组数据线向第一行像素单元写入相应的灰阶电压，同时第二数据信号输出模块通过第二组数据线向第N+1行像素单元写入相应的灰阶电压，以使得第一行像素单元与第N+1行像素单元同时显示像素灰阶。其余行像素单元的像素灰阶显示原理与此类似，在此不再赘述。
参照图5，图5是本公开实施例提供的显示装置中以列划分显示区域像素单元组的结构示意图。其中，显示装置的显示区域中有n行N+M列像素单元。第一组栅极线S11、S12、…、S1n-1、S1n依次与每行的前N列像素单元电连接，第一组数据线D11、D12、…、D1n-1、D1n依次与前N列像素单元电连接；第二组栅极线S21、S22、…、S2n-1、S2n依次与每行的后M列像素单元电连接，第二组数据线D21、D22、…、D2M-1、D2M依次与后M列像素单元电连接。此处，前N列像素单元即为第一像素单元51，后M列像素单元即为第二像素单元组52。此时，第一栅极信号输出模块通过第一组栅极线S11、S12、…、S1n-1、S1n依次与每行的前N列像素单元电连接，第一数据信号输出模块通过第一组数据线D11、D12、…、D1n-1、D1n依次与前N列像素单元电连接；第二栅极信号输出模块通过第二组栅极线S21、S22、…、S2n-1、S2n依次与每行的后M列像素单元电连接，第二数据信号输出模块通过第二组数据线D21、D22、…、 D2M-1、D2M依次与后M列像素单元电连接。其驱动原理与按行划分时类似，在此不再赘述。
可选的，栅极线沿第一方向延伸，沿第二方向排列，数据线沿第二方向延伸，沿第一方向排列。此处的第一方向可以为与像素单元的行相同的方向，第二方向可以为与像素单元的列相同的方向。
图6是本公开实施例提供的一种显示装置及其驱动电路的结构示意图。参照图6，第一栅极信号输出模块11和第二栅极信号输出模块12设置在所述显示装置沿所述第一方向的两侧，如图6中第一方向为像素单元的行方向时，显示区域100的左侧为第一栅极信号输出模块11、以及右侧为第二栅极信号输出模块12。而第一数据信号输出模块21和第二数据信号输出模块22设置在所述显示装置沿第二方向的两侧，如图6中第二方向为像素单元的列方向时，显示区域100的上方为第一数据信号输出模块21、以及下方为第二数据信号输出模块22。
可选的，图7是本公开实施例提供的一种薄膜晶体管液晶显示器的驱动结构图。如图7所示，第一栅极信号输出模块11设置于第一栅极覆晶薄膜区域71，第二栅极信号输出模块12设置于第二栅极覆晶薄膜区域72；第一数据信号输出模块21设置于第一源极覆晶薄膜区域73，第二数据信号输出模块22设置于第二源极覆晶薄膜区域74。将信号输出模块设置于覆晶薄膜区域，以实现显示面板的窄边框的设置。
此时，第一源极覆晶薄膜区域73可与第一柔性电路板75电连接，第二源极覆晶薄膜区域74与第二柔性电路板76电连接。第一柔性电路板75和第二柔性电路板76通过软排线77(Flexible Flat Cable，FFC)连接于系统主板78，并由系统主板发出时序控制信号等，以使得显示装置的显示区域显示相应的画面。
图8是本公开实施例提供的一种显示装置的结构示意图，该显示装置80包括显示面板82、以及本公开实施例提供的显示装置的驱动电路81。所述显示面板82包括多条栅极线823和多条数据线822，其中，多条扫描线823与多条数据线822交叉设置构成多个像素单元。
在某些实施方式中，显示装置80例如可以为LCD显示装置、OLED显示装置、QLED显示装置、曲面显示装置或其他显示装置。
本公开还提供另一种显示装置。该显示装置包括显示面板和驱动电路。
显示面板包括：m条栅极线，2n条数据线和m*n像素单元。多个像素单元设置为m行n列的阵列。每个像素单元包括一个薄膜晶体管。
驱动电路包括第一栅极信号输出模块、第二栅极信号输出模块、第一数据信号输出模块以及第二数据信号输出模块。
m条栅极线与像素单元阵列的m行一一对应。每条栅极线与对应一行的n个像素单元薄膜晶体管的栅极电连接。
m条栅极线包括i条栅极线第一栅极线和j条第二栅极线。i条第一栅极线与第一栅极信号输出模块电连接，j条第二栅极线与第二栅极信号输出模块电连接。i和j均为大于等于1的正整数，并且i+j＝m。
2n条数据线包括n条第一数据线和n条第二数据线。n条第一数据线与第一数据信号输出模块电连接。n条第二数据线与第二数据信号输出模块电连接。
每列像素单元对应一条第一数据线和一条第二数据线。在每列的m个像素单元中，其中i个像素单元的薄膜晶体管的源极与对应的第一数据线电连接，j个像素单元的薄膜晶体管的源极与对应的第二数据线电连接。
在每帧显示图像中，所述第一栅极信号输出模块依次向所述i条第一栅极线输出栅极驱动信号，在所述第一栅极信号输出模块设置为依次向所述i条第一栅 极线输出栅极驱动信号的同时，所述第二栅极信号输出模块依次向所述j条第二栅极线输出栅极信号。
可选地，i＝j，所述i个第一像素单元组为所述像素单元阵列的奇数行，所述j个第二像素单元组为所述像素单元阵列的偶数行。
可选地，所述i个第一像素单元组为所述像素单元阵列的i行，所述j个二像素单元组为所述像素单元阵列的其余j行。
图9示出了显示装置的一个示例。如图9所示，该显示装置包括显示面板100和驱动电路。
驱动电路包括第一栅极信号输出模块11、第二栅极信号输出模块12、第一数据信号输出模块21以及第二数据信号输出模块22。
显示面板100包括4条栅极线、6条数据线和12个像素单元。该12个像素单元设置为4行3列的阵列。
4条栅极线包括栅极线G1、栅极线G2、栅极线G3和栅极线G4。其中，栅极线G1和栅极线G3为第一栅极线，栅极线G2和栅极线G4为第二栅极线。
6条数据线包括数据线D11、数据线D12、数据线D13、数据线D21、数据线D22和数据线D23。数据线D11、数据线D12和数据线D13为第一数据线，数据线D21、数据线D22和数据线D23为第二数据线。
栅极线G1和栅极线G3分别与第一栅极信号输出模块11电连接。栅极线G2和栅极线G4分别与第二栅极信号输出模块12电连接。数据线D11、数据线D12和数据线D13分别与第一数据信号输出模块21电连接。数据线D21、数据线D22和数据线D23分别与第二数据信号输出模块22电连接。
每个像素单元设置有一个薄膜晶体管，所述薄膜晶体管具有源极、漏极和栅极。12个像素单元包括像素单元P11、像素单元P12、像素单元P13、像素单 元P21、像素单元P22、像素单元P23、像素单元P31、像素单元P32、像素单元P33、像素单元P41、像素单元P42和像素单元P43。
第一行的像素单元(像素单元P11、像素单元P12和像素单元P13)的薄膜晶体管的栅极都电连接到栅极线G1，源极分别电连接数据线D11、数据线D12和数据线D13。
第二行的像素单元(像素单元P21、像素单元P22和像素单元P23)的薄膜晶体管的栅极都电连接到栅极线G2，源极分别电连接数据线D21、数据线D22和数据线D23。
第三行的像素单元(像素单元P31、像素单元P32和像素单元P33)的薄膜晶体管的栅极都电连接到栅极线G3，源极分别电连接数据线D11、数据线D12和数据线D13。
第四行的像素单元(像素单元P41、像素单元P42和像素单元P43)的薄膜晶体管的栅极都电连接到栅极线G4，源极分别电连接数据线D21、数据线D22和数据线D23。
在第一时间段，第一栅极信号输出模块11向栅极线G1输出栅极驱动信号，第二栅极信号输出模块12向栅极线G2输出栅极驱动信号，第一数据信号输出模块21通过数据线D11、D12和D13分别向第一行的像素单元(像素单元P11、像素单元P12和像素单元P13)输出数据信号，第二数据线信号输出模块22通过数据线D21、D22和D23分别向第二行的像素单元(像素单元P21、像素单元P22和像素单元P23)输出数据信号。在第一时间段内，第一行的像素单元和第二行的像素单元同时被驱动。
在第二时间段，第一栅极信号输出模块11向栅极线G3输出栅极驱动信号，第二栅极信号输出模块12向栅极线G4输出栅极驱动信号，第一数据信号输出 模块21通过数据线D11、D12和D13分别向第三行的像素单元(像素单元P31、像素单元P32和像素单元P33)输出数据信号，第二数据线信号输出模块22通过数据线D21、D22和D23分别向第二行的像素单元(像素单元P41、像素单元P42和像素单元P43)输出数据信号。在第二时间段内，第三行的像素单元和第四行的像素单元同时被驱动。
图10示出了显示装置的另一个示例。如图10所示，该显示装置包括显示面板100和驱动电路。
驱动电路包括第一栅极信号输出模块11、第二栅极信号输出模块12、第一数据信号输出模块21以及第二数据信号输出模块22。
显示面板100包括5条栅极线、6条数据线和15个像素单元。该15个像素单元设置为5行3列的阵列。
5条栅极线包括栅极线G1、栅极线G2、栅极线G3、栅极线G4和栅极线G5。其中，栅极线G1、栅极线G3和栅极线G5为第一栅极线，栅极线G2和栅极线G4为第二栅极线。
6条数据线包括数据线D11、数据线D12、数据线D13、数据线D21、数据线D22和数据线D23。数据线D11、数据线D12和数据线D13为第一数据线，数据线D21、数据线D22和数据线D23为第二数据线。
第一栅极线(栅极线G1、栅极线G3和栅极线G5)分别与第一栅极信号输出模块11电连接。第二栅极线(栅极线G2和栅极线G4)分别与第二栅极信号输出模块12电连接。第一数据线(数据线D11、数据线D12和数据线D13)分别与第一数据信号输出模块21电连接。第二数据线(数据线D21、数据线D22和数据线D23)分别与第二数据信号输出模块22电连接。
每个像素单元设置有一个薄膜晶体管，所述薄膜晶体管具有源极、漏极和 栅极。15个像素单元包括像素单元P11、像素单元P12、像素单元P13、像素单元P21、像素单元P22、像素单元P23、像素单元P31、像素单元P32、像素单元P33、像素单元P41、像素单元P42、像素单元P43、像素单元P51、像素单元P52和像素单元P53。
第一行的像素单元(像素单元P11、像素单元P12和像素单元P13)的薄膜晶体管的栅极都电连接到栅极线G1，源极分别电连接数据线D11、数据线D12和数据线D13。
第二行的像素单元(像素单元P21、像素单元P22和像素单元P23)的薄膜晶体管的栅极都电连接到栅极线G2，源极分别电连接数据线D21、数据线D22和数据线D23。
第三行的像素单元(像素单元P31、像素单元P32和像素单元P33)的薄膜晶体管的栅极都电连接到栅极线G3，源极分别电连接数据线D11、数据线D12和数据线D13。
第四行的像素单元(像素单元P41、像素单元P42和像素单元P43)的薄膜晶体管的栅极都电连接到栅极线G4，源极分别电连接数据线D21、数据线D22和数据线D23。
第五行的像素单元(像素单元P51、像素单元P52和像素单元P53)的薄膜晶体管的栅极都电连接到栅极线G5，源极分别电连接数据线D11、数据线D12和数据线D13。
图11示出了该显示装置显示一帧图像的时序图。为了显示一帧图像，该显示装置需要时间T。时间T可分为三个时间段t11、t12和t13。时间T也分为两个时间段t21和t22。
在时间段t11，第一栅极信号输出模块11向栅极线G1输出栅极驱动信号， 第一数据信号输出模块21通过数据线D11、D12和D13分别向第一行的像素单元(像素单元P11、像素单元P12和像素单元P13)输出数据信号。
在时间段t12，第一栅极信号输出模块11向栅极线G3输出栅极驱动信号，第一数据信号输出模块21通过数据线D11、D12和D13分别向第三行的像素单元(像素单元P31、像素单元P32和像素单元P33)输出数据信号。
在时间段t13，第一栅极信号输出模块11向栅极线G5输出栅极驱动信号，第一数据信号输出模块21通过数据线D11、D12和D13分别向第五行的像素单元(像素单元P51、像素单元P52和像素单元P53)输出数据信号。
在时间段t21，第二栅极信号输出模块12向栅极线G2输出栅极驱动信号，第二数据信号输出模块22通过数据线D21、D22和D23分别向第二行的像素单元(像素单元P21、像素单元P22和像素单元P23)输出数据信号。
在时间段t22，第二栅极信号输出模块12向栅极线G2输出栅极驱动信号，第二数据信号输出模块22通过数据线D21、D22和D23分别向第四行的像素单元(像素单元P41、像素单元P42和像素单元P43)输出数据信号。
本实施例的显示装置减少每帧图像的扫描时间，提高显示装置的刷新率。注意，上述仅为本公开的较佳实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种显示装置的驱动电路，包括：
    第一栅极信号输出模块，通过第一组栅极线与第一像素单元组电连接；
    第二栅极信号输出模块，通过第二组栅极线与第二像素单元组电连接；
    第一数据信号输出模块，通过第一组数据线与所述第一像素单元组电连接，并设置为向所述第一组数据线中的数据线输出数据信号；以及
    第二数据信号输出模块，通过第二组数据线与所述第二像素单元组电连接，并设置为向所述第二组数据线中的数据线输出数据信号；
    其中，在每帧显示图像中，所述第一栅极信号输出模块设置为向所述第一组栅极线中的栅极线依次输出栅极驱动信号；所述第二栅极信号输出模块设置为：在所述第一栅极信号输出模块向所述第一组栅极线中的栅极线依次输出栅极驱动信号的同时，向所述第二组栅极线中的栅极线依次输出栅极驱动信号。
  2. 根据权利要求1所述驱动电路，其中，所述显示装置包括多条栅极线，所述第一组栅极线为所述多条栅极线的奇数栅极线，所述第二组栅极线为所述多条栅极线的偶数栅极线，
    所述第一栅极信号输出模块设置为向所述多条栅极线的奇数栅极线依次输出栅极驱动信号；所述第二栅极信号输出模块设置：在所述第一栅极信号输出模块向所述多条栅极线的奇数栅极线依次输出栅极驱动信号的同时，向所述多条栅极线的偶数栅极线依次输出栅极驱动信号。
  3. 根据权利要求1所述的驱动电路，其中，所述显示装置包括阵列排布的多个像素单元，所述第一像素单元组为所述多个像素单元的前N行，所述第二像素单元组为所述多个像素单元的后M行像素单元，其中M，N均为大于或等于1的正整数，且M+N等于多个像素单元的总行数。
  4. 根据权利要求1所述的驱动电路，其中，所述显示装置包括阵列排布的 多个像素单元，所述第一像素单元组为多个像素单元的前N列，所述第二像素单元组为多个像素单元的后M列，其中M，N均为大于或等于1的正整数，且M+N等于多个像素单元的总列数。
  5. 根据权利要求1所述的驱动电路，其中，所述第一组栅极线和第二组栅极线中的栅极线均沿第一方向延伸，第一组栅极线和第二组栅极线中的栅极线沿第二方向排列，所述第一组数据线和第二组数据线中的数据线均沿第二方向延伸，所述第一组数据线和第二组数据线中的数据线沿第一方向排列；
    所述第一栅极信号输出模块和所述第二栅极信号输出模块设置在所述显示装置沿所述第一方向的两侧，所述第一数据信号输出模块和所述第二数据信号输出模块设置在所述显示装置沿第二方向的两侧。
  6. 根据权利要求1所述的驱动电路，其中，所述第一栅极信号输出模块设置于第一栅极覆晶薄膜区域，所述第二栅极信号输出模块设置于第二栅极覆晶薄膜区域。
  7. 根据权利要求1所述的驱动电路，其中，所述第一数据信号输出模块设置于第一源极覆晶薄膜区域，所述第二数据信号输出模块设置于第二源极覆晶薄膜区域。
  8. 根据权利要求7所述的驱动电路，其中，所述第一源极覆晶薄膜区域与第一柔性电路板电连接；所述第二源极覆晶薄膜区域与第二柔性电路板电连接。
  9. 一种显示装置，包括显示面板和驱动电路，其中，
    所述显示面板包括：
    多条栅极线，包括第一组栅极线和第二组栅极线；
    多条数据线，包括第一组数据线和第二组数据线；以及
    行列排布的多个像素单元，包括第一像素单元组和第二像素单元组，
    所述驱动电路包括：
    第一栅极信号输出模块，通过第一组栅极线与第一像素单元组电连接；
    第二栅极信号输出模块，通过第二组栅极线与第二像素单元组电连接；
    第一数据信号输出模块，通过第一组数据线与所述第一像素单元组电连接；以及
    第二数据信号输出模块，通过第二组数据线与所述第二像素单元组电连接；
    其中，在每帧显示图像中，第一栅极信号输出模块依次向第一组栅极线输出栅极驱动信号，第一数据信号输出模块向第一组数据线输出数据信号；同时，第二栅极信号输出模块依次向第二组栅极线输出栅极驱动信号，第二数据信号输出模块向第二组数据线输出数据信号。
  10. 根据权利要求9所述的显示装置，其中，所述第一像素单元组为所述多个像素单元的奇数行，所述第二像素单元组为所述多个像素单元的偶数行。
  11. 根据权利要求9所述的显示装置，其中，所述第一像素单元组为所述多个像素单元的前N行，所述第二像素单元组为所述多个像素单元的后M行像素单元，其中M，N均为大于或等于1的正整数，且M+N等于多个像素单元的总行数。
  12. 根据权利要求9所述的显示装置，其中，所述第一像素单元组为多个像素单元的前N列，所述第二像素单元组为多个像素单元的后M列，其中M，N均为大于或等于1的正整数，且M+N等于多个像素单元的总列数。
  13. 根据权利要求9所述的显示装置，其中，所述多条栅极线均沿第一方向延伸，所述多条栅极线沿第二方向排列，所述多条数据线均沿第二方向延伸，所述多条数据线沿第一方向排列；
    所述第一栅极信号输出模块和所述第二栅极信号输出模块设置在所述显示装置沿所述第一方向的两侧，所述第一数据信号输出模块和所述第二数据信号输出模块设置在所述显示装置沿第二方向的两侧。
  14. 根据权利要求9所述的显示装置，其中，所述第一栅极信号输出模块设置于第一栅极覆晶薄膜区域，所述第二栅极信号输出模块设置于第二栅极覆晶薄膜区域。
  15. 根据权利要求9所述的显示装置，其中，所述第一数据信号输出模块设置于第一源极覆晶薄膜区域，所述第二数据信号输出模块设置于第二源极覆晶薄膜区域。
  16. 根据权利要求15所述的显示装置，其中，所述第一源极覆晶薄膜区域与第一柔性电路板电连接；所述第二源极覆晶薄膜区域与第二柔性电路板电连接。
  17. 一种显示装置，包括显示面板和驱动电路，其中，
    所述显示面板包括：
    m条栅极线，包括i条第一栅极线和j条第二栅极线；
    2n条数据线，包括n条第一数据线和n条第二数据线；以及
    m行n列的像素单元阵列，
    所述驱动电路包括：
    第一栅极信号输出模块，与所述i条第一栅极线电连接；
    第二栅极信号输出模块，与所述j条第一栅极线电连接；
    第一数据信号输出模块，与所述n条第一数据线电连接；以及
    第二数据信号输出模块，与所述n条第二数据线电连接，
    其中，所述像素单元阵列包括i个第一像素单元组和j个第二像素单元组； 每个第一像素单元组与i条第一栅极线中的对应一条电连接，并与n条第一数据线电连接；每个第二像素单元组与j条第二栅极线中的对应一条电连接，并与n条第二数据线电连接，其中，i、j、m、n均为大于1的正整数，并且i+j＝m。
  18. 根据权利要求17所述的显示装置，其中，i＝j，所述i个第一像素单元组为所述像素单元阵列的奇数行，所述j个第二像素单元组为所述像素单元阵列的偶数行。
  19. 根据权利要求17所述的显示装置，其中，所述i个第一像素单元组为所述像素单元阵列的i行，所述j个二像素单元组为所述像素单元阵列的其余j行。
  20. 根据权利要求17所述的显示装置，其中，所述第一栅极信号输出模块设置为依次向所述i条第一栅极线输出栅极驱动信号；所述第二栅极信号输出模块设置为：在所述第一栅极信号输出模块依次向所述i条第一栅极线输出栅极驱动信号的同时，依次向所述j条第二栅极线输出栅极信号。
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CN101726955A (zh) * 2009-12-30 2010-06-09 友达光电股份有限公司 有源矩阵显示器
CN103065575A (zh) * 2011-10-20 2013-04-24 乐金显示有限公司 数字全息图像再现装置及其同步控制方法
CN103185976A (zh) * 2011-12-31 2013-07-03 上海中航光电子有限公司 液晶显示装置及其驱动方法

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