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WO2008117431A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2008117431A1
WO2008117431A1 PCT/JP2007/056369 JP2007056369W WO2008117431A1 WO 2008117431 A1 WO2008117431 A1 WO 2008117431A1 JP 2007056369 W JP2007056369 W JP 2007056369W WO 2008117431 A1 WO2008117431 A1 WO 2008117431A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
field effect
effect transistor
forming
Prior art date
Application number
PCT/JP2007/056369
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English (en)
French (fr)
Inventor
Tamotsu Owada
Hirofumi Watatani
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to PCT/JP2007/056369 priority Critical patent/WO2008117431A1/ja
Priority to JP2009506144A priority patent/JP5310543B2/ja
Publication of WO2008117431A1 publication Critical patent/WO2008117431A1/ja
Priority to US12/567,972 priority patent/US8604552B2/en
Priority to US13/598,010 priority patent/US20120322272A1/en

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
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    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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  • Engineering & Computer Science (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

（課題）チャネル領域に引っ張りストレスを与える応力膜が分断することを抑制し、信頼性の高い半導体装置及びその製造方法を提供する。 （解決手段）本発明は、高いキャリア移動特性を有し、電界効果トランジスタ上に応力膜を有する半導体装置及びその製造方法に関するものであり、上記課題を解決するために、シリコン基板にｎチャネル型電界効果トランジスタを形成する工程と、前記電界効果トランジスタを覆う絶縁膜を成膜する第１の工程と、前記絶縁膜を収縮させる第２の工程とを有し、前記第１の工程と前記第２の工程とを複数回繰り返す。  
PCT/JP2007/056369 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法 WO2008117431A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2007/056369 WO2008117431A1 (ja) 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法
JP2009506144A JP5310543B2 (ja) 2007-03-27 2007-03-27 半導体装置の製造方法
US12/567,972 US8604552B2 (en) 2007-03-27 2009-09-28 Semiconductor device and method for fabricating semiconductor device
US13/598,010 US20120322272A1 (en) 2007-03-27 2012-08-29 Semiconductor device and method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056369 WO2008117431A1 (ja) 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法

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US12/567,972 Continuation US8604552B2 (en) 2007-03-27 2009-09-28 Semiconductor device and method for fabricating semiconductor device

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WO2008117431A1 true WO2008117431A1 (ja) 2008-10-02

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JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
JP2012164869A (ja) * 2011-02-08 2012-08-30 Renesas Electronics Corp 半導体装置およびその製造方法
JP2013511850A (ja) * 2009-11-19 2013-04-04 クアルコム，インコーポレイテッド 歪み材料を有する半導体デバイス
CN103904055A (zh) * 2014-03-20 2014-07-02 上海华力微电子有限公司 一种接触孔刻蚀阻挡层结构及其制备方法

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CN102386087B (zh) * 2010-08-27 2016-03-16 中芯国际集成电路制造(上海)有限公司 一种改进的金属前介质层的构造方法
CN103346080A (zh) * 2013-07-09 2013-10-09 上海华力微电子有限公司 减少金属硅化物掩模层缺陷的方法
FR3076077B1 (fr) * 2017-12-22 2020-02-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation de transistors a canaux contraints

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* Cited by examiner, † Cited by third party
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JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
JP2013511850A (ja) * 2009-11-19 2013-04-04 クアルコム，インコーポレイテッド 歪み材料を有する半導体デバイス
KR101350846B1 (ko) * 2009-11-19 2014-01-13 퀄컴 인코포레이티드 스트레인 물질을 가지는 반도체 디바이스
JP2012164869A (ja) * 2011-02-08 2012-08-30 Renesas Electronics Corp 半導体装置およびその製造方法
CN103904055A (zh) * 2014-03-20 2014-07-02 上海华力微电子有限公司 一种接触孔刻蚀阻挡层结构及其制备方法

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US20100012991A1 (en) 2010-01-21

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