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US8243175B2 - Solid-state imaging device - Google Patents

Solid-state imaging device Download PDF

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Publication number
US8243175B2
US8243175B2 US10/554,106 US55410604A US8243175B2 US 8243175 B2 US8243175 B2 US 8243175B2 US 55410604 A US55410604 A US 55410604A US 8243175 B2 US8243175 B2 US 8243175B2
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Prior art keywords
solid
state imaging
planar portion
imaging element
package
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US10/554,106
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US20070064134A1 (en
Inventor
Hiroya Kobayashi
Hiroshi Akahori
Masaharu Muramatsu
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Hamamatsu Photonics KK
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Hamamatsu Photonics KK
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Assigned to HAMAMATSU PHOTONICS K.K. reassignment HAMAMATSU PHOTONICS K.K. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AKAHORI, HIROSHI, MURAMATSU, MASAHARU, KOBAYASHI, HIROYA
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/804—Containers or encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to a solid-state imaging apparatus.
  • a solid-state imaging apparatus comprising: a solid-state imaging element, having an energy ray sensitive portion; and a package, housing the solid-state imaging element; and having signal processing circuits, which process signals output from the above-mentioned solid-state imaging element and are disposed at the exterior of the package (see, for example, Patent Document 1).
  • Patent Document 1 Japanese Published Unexamined Patent Application No. H4-317280
  • the signal transmission paths (electrical wirings) from the solid-state imaging element to the signal processing circuits become long and the parasitic capacitance of the signal transmission paths becomes large.
  • the waveforms of the signals output from the solid-state imaging element become damped and high-speed response properties are degraded.
  • the present invention has been accomplished in view of the above point and an object of the invention is to provide a solid-state imaging apparatus, with which the parasitic capacitance of signal transmission paths is reduced to enable restraining of the damping of the waveforms of signals output from a solid-state imaging element and improvement of the high-speed response properties.
  • a solid-state imaging apparatus comprises: a solid-state imaging element; having an energy ray sensitive portion, a signal processing circuit, processing signals output from the solid-state imaging element; and a package, housing the solid-state imaging element and the signal processing circuit; wherein the signal processing circuit is positioned at a planar portion of the package that differ from a planar portion at which the solid-state imaging element is positioned.
  • the solid-state imaging element and the signal processing circuit are positioned proximally with respect to each other.
  • Signal transmission path from the solid-state imaging element to the signal processing circuit is thereby made short and the parasitic capacitance of the signal transmission path is made small.
  • the damping of the waveforms of the signal output from the solid-state imaging element can be restrained and the high-speed response properties can be improved.
  • a solid-state imaging apparatus comprises: a solid-state imaging element, having an energy ray sensitive portion; a signal processing circuit, processing signals output from the solid-state imaging element; and a package, housing the solid-state imaging element and the signal processing circuit; wherein the package has a first planar portion and a second planar portions, formed to be stepped with respect to the first planar portion, and wherein the solid-state imaging element is positioned at the first planar portion while the signal processing circuit is positioned at the second planar portion.
  • the signal processing circuit is positioned proximally to the solid-state imaging element by making use of the step difference between the first planar portion and the second planar portion.
  • Signal transmission path from the solid-state imaging element to the signal processing circuit is thereby made short and the parasitic capacitance of the signal transmission path is made small.
  • the damping of the waveforms of the signal output from the solid-state imaging element can be restrained and the high-speed response properties can be improved.
  • the solid-state imaging apparatus is provided with which the parasitic capacitance of the signal transmission path is reduced to enable restraining of the damping of the waveforms of the signal output from the solid-state imaging element and improvement of the high-speed response properties.
  • the signal processing circuit includes a load resistor that is electrically connected to an output terminal of the solid-state imaging element.
  • a load resistor that is electrically connected to an output terminal of the solid-state imaging element.
  • the signal processing circuit includes a load resistor, with which one end is electrically connected to an output terminal of the solid-state imaging element and the other end is grounded, and a buffer amplifier, having a bipolar transistor that is electrically connected to the output terminal of the solid-state imaging element.
  • a load resistor with which one end is electrically connected to an output terminal of the solid-state imaging element and the other end is grounded
  • a buffer amplifier having a bipolar transistor that is electrically connected to the output terminal of the solid-state imaging element.
  • FIG. 1 is a schematic view for describing the sectional composition of a solid-state imaging apparatus of a first embodiment.
  • FIG. 2 is a plan view of the solid-state imaging apparatus of the first embodiment.
  • FIG. 3 is a circuit diagram for describing the composition of a signal processing circuit.
  • FIG. 4A is a schematic view showing a solid-state imaging apparatus of a conventional art.
  • FIG. 4B is a schematic view showing the solid-state imaging apparatus of the first embodiment.
  • FIG. 5 is a schematic view for describing the sectional composition of a solid-state imaging apparatus of a second embodiment.
  • FIG. 6 is a plan view of the solid-state imaging apparatus of the second embodiment.
  • FIG. 7 is a plan view showing the composition of the vicinity of the buffer amplifier module shown in FIG. 6 .
  • FIG. 8 is a circuit diagram for describing the composition of the buffer amplifier module.
  • FIG. 9A is a schematic view showing a solid-state imaging apparatus of a conventional art.
  • FIG. 9B is a schematic view showing the solid-state imaging apparatus of the second embodiment.
  • FIG. 10 is a schematic view for describing the sectional composition of a modification example of the solid-state imaging apparatus of the second embodiment.
  • FIG. 1 is a schematic view for describing the sectional composition of the solid-state imaging apparatus of the first embodiment.
  • FIG. 2 is a plan view of the same solid-state imaging apparatus of the first embodiment.
  • FIG. 3 is a circuit diagram for describing the composition of a signal processing circuit.
  • FIG. 2 is a view viewed from a back surface (side opposite the side onto which energy rays are made incident) of the solid-state imaging apparatus.
  • a solid-state imaging apparatus IS 1 of the first embodiment comprises a ceramic package P 1 , a back-illuminated CCD chip 11 (solid-state imaging element), chip resistor arrays 21 , etc.
  • a hollow portion 1 which extends in a predetermined direction of package P 1 .
  • a mounting portion 2 for mounting CCD chip 11 and chip resistor arrays 21 , is disposed so as to protrude into hollow portion 1 .
  • Mounting portion 2 has a first planar portion 3 for positioning of CCD chip 11 and second planar portions 4 for positioning of chip resistor arrays 21 .
  • First planar portion 3 and second planar portions 4 are formed to be stepped with respect to each other.
  • Mounting portion 2 furthermore has a third planar portion 5 and a fourth planar portion 6 .
  • Third planar portion 5 is positioned between first planar portion 3 and second planar portions 4 and is formed to be stepped with respect to first planar portion 3 and second planar portions 4 .
  • Fourth planar portion 6 is positioned between a back surface 7 of package P 1 and second planar portions 4 and is formed to be stepped with respect to back surface 7 of package P 1 and second planar portions 4 .
  • a plurality of electrode pins 27 for external connection are positioned on back surface 7 of package P 1 .
  • CCD chip 11 has an energy ray sensitive portion 12 , which converts incident energy rays into charges.
  • CCD chip 11 is mounted on first planar portion 3 of mounting portion 2 via a spacer 13 so that the back surface will be the energy ray incident surface and is fixed onto the mounting portion 2 (package P 1 ).
  • CCD chip 11 is formed of a silicon substrate of a thickness of approximately 300 ⁇ m. With back-illuminated CCD chip 11 , the substrate must be made thin and a potential slope must be formed from the incident surface (back surface) side.
  • a thin portion 14 which is thinned to a thickness of approximately 10 to 30 ⁇ m (that is, etched to a depth of approximately 270 to 290 ⁇ m), is formed.
  • a structure having such a thin portion 14 is formed by depositing a silicon nitride film onto the silicon substrate, patterning the film to a desired shape by a photolithography process, and using the film as a mask to etch the silicon substrate using an etching solution, comprising KOH, while leaving the peripheral portion of the substrate, which is covered by the silicon nitride film, in the thick state.
  • Spacer 13 is formed of a material that has a higher thermal expansion coefficient at a predetermined temperature range (for example, 133° C.) than the thermal expansion coefficient of CCD chip 11 (silicon), and in the present embodiment, is formed of alumina or other ceramic material.
  • the thermal expansion coefficient of silicon at 133° C. is 2.5 ⁇ 10 ⁇ 6 (/° C.) and the thermal expansion coefficient of alumina at 133° C. is 6.5 ⁇ 10 ⁇ 6 (/° C.).
  • Spacer 13 is adhered and fixed to package P 1 by an adhesive agent (not shown). Also, the back surface side of a frame portion 15 of CCD chip 11 is adhered and fixed to spacer 13 by an adhesive agent (not shown).
  • a seal ring 31 is fixed by brazing, etc., so as to surround hollow portion 1 (CCD chip 11 ).
  • a cap 32 is seam-welded to seal ring 31 .
  • cap 32 has its outer peripheral portion mounted on and seam-welded to seal ring 31 and has an opening portion 33 , provided at a position opposing thin portion 14 of CCD chip 11 .
  • Cap 32 is formed integrally of kovar (fernico) and a gold plating is applied to its front surface 8 .
  • a window member 34 which allows the transmission of energy rays (light, electron beam, etc.), is fixed to cap 32 so as to cover opening portion 33 .
  • Window member 34 is formed of a plate-like quartz glass base material, is arranged to transmit ultraviolet rays, and its energy ray incident surface and energy ray exit surface are polished. Also, window member 34 is fixed to cap 32 by the end portions of the energy ray incident surface being fixed across the entire periphery onto the upper surface (the surface at the side opposite the surface opposing CCD chip 11 ) of cap 32 via an adhesive layer (not shown).
  • portion of hollow portion 1 of package P 1 at the opposite side of the energy ray incident side portion may be sealed by a bottom cover or by filling with a resin material, etc.
  • a plurality of first package side electrodes 41 for connection with CCD chip side electrodes (not shown) of CCD chip 11 , are disposed on third flat portion 5 of mounting portion 2 .
  • Each first package side electrode 41 is electrically connected to a predetermined electrode pin among a plurality of electrode pins 27 via an internal wiring (not shown) formed inside package P 1 .
  • the CCD chip side electrodes and first package side electrodes 41 are electrically connected via bonding wires (not shown). Transfer signals and other signals are thus sent from the exterior to CCD chip 11 via predetermined electrode pins, internal wirings, first package side electrodes 41 , bonding wires, and CCD chip side electrodes.
  • Each chip resistor array 21 has a plurality of resistors 22 , which are formed in array form on a substrate 21 a .
  • an input terminal (input electrode) 23 and an output terminal (output electrode) 24 are formed for each resistor 22 .
  • Each chip resistor array 21 is mounted on a second planar portion 4 of mounting portion 2 via an adhesive layer (not shown) and is thereby fixed to mounting portion 2 (package P 1 ).
  • Input terminals 23 are electrically connected via bonding wires 42 to output terminals (electrodes) OS of CCD chip 11 .
  • Second package side electrodes 43 for connection to output terminals 24 of chip resistor array 21 .
  • Each second package side electrode 43 is electrically connected to a predetermined electrode pin among the plurality of electrode pins 27 via an internal wiring formed inside package P 1 .
  • Output terminals 24 and second package side electrodes 43 are electrically connected via bonding wires 44 . Signals are thus sent from CCD chip 11 to the exterior via output terminals OS of CCD chip 11 , bonding wires 42 , chip resistor arrays 21 (resistors 22 ), bonding wires 44 , second package side electrodes 43 , internal wirings, and predetermined electrode pins.
  • Each signal processing circuit has resistor 22 , which is included in chip resistor array 21 , and an operational amplifier 51 .
  • Operational amplifier 51 is formed on an external substrate (not shown), etc., onto which solid-state imaging apparatus IS 1 (package P 1 ) is mounted.
  • CCD chip 11 has field-effect transistors 16 for reading potential variations of floating diffusions (not shown), and the gate terminal of each field-effect transistor 16 is electrically connected to the floating diffusion.
  • the source terminal of each field-effect transistor 16 is electrically connected to output terminal OS of CCD chip 11 and is connected via the output terminal OS to input terminal 23 of resistor 22 .
  • the drain terminal of each field-effect transistor 16 is electrically connected to a terminal OD, and a voltage that exhibits a fixed positive voltage value is input into the terminal OD.
  • resistor 22 acts as a load resistor and field-effect transistor 16 and resistor 22 make up a source follower circuit.
  • Output terminal 24 of resistor 22 is electrically connected to the inverted input terminal of operational amplifier 51 .
  • a resistor 52 is disposed between the inverted input terminal and the output terminal of operational amplifier 51 , and a variable voltage supply 53 is electrically connected to the non-inverted input terminal of operational amplifier 51 .
  • the inverted input terminal and the non-inverted input terminal of operational amplifier 51 are in a virtually shorted relationship.
  • a shielding member 35 is positioned with respect to CCD chip 11 so as to shield the front side in the energy ray incident direction of a beveled portion (the inclined portion between thin portion 14 and frame portion 15 ) of CCD chip 11 .
  • the shielding member 35 is formed of a silicon substrate of approximately 300 ⁇ m thickness and blocks energy rays (such as light).
  • a through hole 36 of rectangular shape is formed by etching, etc., at a position of shielding member 35 that opposes thin portion 14 .
  • Shielding member 35 is adhered and fixed to the back surface 7 side of frame portion 15 of CCD chip 11 by an adhesive agent (not shown), formed of epoxy resin, etc.
  • a recessed portion which holds shielding member 35 in the state in which CCD chip 11 and spacer 13 are adhered and fixed, is formed at a position of spacer 13 that corresponds to shielding member 35 , fixed to frame portion 15 of CCD chip 11 , so as to surround the entire periphery of shielding member 35 .
  • chip resistor arrays 21 are positioned on second planar portions 4 , which differ from first planar portion 3 on which CCD chip 11 is positioned, and using the step difference between first planar portion 3 and second planar portions 4 , CCD chip 11 and chip resistor arrays 21 are positioned proximally.
  • the signal transmission paths from CCD chip 11 to chip resistor arrays 21 (resistors 22 ) are made shorter and the parasitic capacitance of the signal transmission paths is made smaller in solid-state imaging apparatus IS 1 of the present embodiment (see FIG. 4B ).
  • the damping of the waveforms of the signals output from CCD chip 11 can be restrained and the high speed response properties can be improved.
  • each chip resistor array 21 includes resistors 22 that are electrically connected to output terminals OS of CCD chip 11 .
  • resistors 22 that function as load resistors are positioned away from CCD chip 11 ; even when resistors 22 generate heat, adverse effects on the characteristics of CCD chip 11 (for example, increasing of the dark current) can be prevented.
  • each operational amplifier 51 Since the inverted input terminal and the non-inverted input terminal of each operational amplifier 51 is in a virtually shorted relationship, the electric potential here is always fixed. Charging and discharging of charges therefore will not occur and effects due to the parasitic capacitance of the signal transmission paths from chip resistor arrays 21 to operational amplifier 51 can be neglected substantially.
  • FIG. 5 is a schematic view for describing the sectional composition of the solid-state imaging apparatus of the second embodiment.
  • FIG. 6 is a plan view of the same solid-state imaging apparatus of the second embodiment.
  • FIG. 7 is a plan view showing the composition of the vicinity of a buffer amplifier module.
  • FIG. 8 is a circuit diagram for describing the composition of the buffer amplifier module.
  • FIGS. 6 and 7 are diagrams of the solid-state imaging apparatus as viewed from the back surface side.
  • a solid-state imaging apparatus IS 2 of the second embodiment comprises a package P 2 , CCD chip 11 , buffer amplifier modules 61 , which serve as signal processing circuits, etc.
  • Mounting portion 2 has a first planar portion 3 for positioning CCD chip 11 , second planar portions 4 for positioning buffer amplifier modules 61 , and a third planar portion 9 .
  • Third planar portion 9 is positioned between back surface 7 of package P 2 and second planar portions 4 and is formed to be stepped with respect to back surface 7 of package P 2 and second planar portions 4 .
  • the portion of hollow portion 1 of package P 2 at the opposite side of the energy ray incident side portion is sealed by a bottom cover 10 .
  • a plurality of package side electrodes 45 are disposed on third planar portion 9 of mounting portion 2 .
  • Each package side electrode 45 is electrically connected to a predetermined electrode pin among the plurality of electrode pins 27 via an internal wiring (not shown) formed inside package P 2 .
  • Predetermined electrodes among CCD chip side electrodes 19 , formed on CCD chip 11 are electrically connected via bonding wires 46 to predetermined electrodes among package side electrodes 45 . Transfer signals and other signals are thus sent from the exterior to CCD chip 11 via predetermined electrode pins, internal wirings, predetermined package side electrodes, bonding wires 46 , and predetermined CCD chip side electrodes.
  • each buffer amplifier module 61 comprises a load resistor 62 , a bipolar transistor 63 , and a field-effect transistor 64 , and load resistor 62 , bipolar transistor 63 , and field-effect transistor 64 are positioned on a substrate 61 a.
  • Each buffer amplifier module 61 (substrate 61 a) is mounted via an adhesive layer (not shown) on a second planar portion 4 of mounting portion 2 and is thereby fixed to the mounting portion 2 (package P 2 ).
  • An output terminal OS 1 (source terminal of a field-effect transistor 16 ) of CCD chip 11 is electrically connected to an input terminal (electrode) 65 of a buffer amplifier module 61 .
  • One terminal of load resistor 62 is electrically connected via input terminal 65 to output terminal OS 1 of CCD chip 11 and the other terminal of load resistor 62 is grounded.
  • the base terminal of bipolar transistor 63 is electrically connected via input terminal 65 and a resistor 66 to output terminal OS 1 of CCD chip 11 , and the emitter terminal is electrically connected to the drain terminal of field-effect transistor 64 and an output terminal (electrode) 67 of buffer amplifier module 61 .
  • the collector terminal of bipolar transistor 63 is electrically connected to a terminal (electrode) 70 .
  • terminal OD a voltage, exhibiting a fixed positive voltage value, is input into terminal 70 .
  • the gate terminal and source terminal of field effect transistor 64 are grounded.
  • Resistor element 66 is for controlling the base current of bipolar transistor 63 .
  • field effect transistor 16 and load resistor 62 make up a source follower circuit.
  • Output terminal OSI of CCD chip 11 and input terminal 65 of buffer amplifier module 61 are connected via a bonding wire 68 .
  • Output terminal 67 of buffer amplifier module 61 is connected via a bonding wire 69 to a predetermined package side electrode OS 2 .
  • Terminal OD is connected via a bonding wire 71 to a terminal 72 of buffer amplifier module 61 and is electrically connected to terminal 70 .
  • Terminal 70 is connected via a bonding wire 47 to a predetermined package side electrode.
  • a terminal SS of the CCD chip is connected via a bonding wire 75 to a terminal (electrode) 76 of buffer amplifier module 61 , and a terminal (electrode) 77 that is electrically connected to the terminal 76 is connected via a bonding wire 78 to a predetermined package side electrode.
  • the predetermined package side electrode is electrically connected to a predetermined electrode pin (ground pin) among electrode pins 27 that is grounded.
  • buffer amplifier modules 61 are positioned on second planar portions 4 , which differ from first planar portion 3 on which CCD chip 11 is positioned, and using the step difference between first planar portion 3 and second planar portions 4 , CCD chip 11 and buffer amplifier modules 61 are positioned proximally.
  • the present embodiment's solid-state imaging apparatus IS 2 is made shorter in the signal transmission paths from CCD chip 11 to buffer amplifier modules 61 and thus made smaller in the parasitic capacitance of the signal transmission paths.
  • Buffer amplifier modules 203 in FIG. 9A have the same composition as buffer amplifier modules 61 of the present embodiment.
  • each buffer amplifier module 61 includes load resistor 62 , which has one end connected to output terminal OS 1 of CCD chip 11 and the other end grounded, and bipolar transistor 63 , which is electrically connected to output terminal OS 1 of CCD chip 11 .
  • load resistor 62 which has one end connected to output terminal OS 1 of CCD chip 11 and the other end grounded
  • bipolar transistor 63 which is electrically connected to output terminal OS 1 of CCD chip 11 .
  • FIG. 10 is a schematic view for describing the sectional composition of the modification example of the solid-state imaging apparatus of the second embodiment.
  • a solid-state imaging apparatus IS 3 of the modification example of the second embodiment comprises a package P 3 , a front-illuminated CCD chip 81 , buffer amplifier modules 61 , which serve as signal processing circuits, etc.
  • Package P 3 has a recessed portion 93 , which is surrounded by a bottom portion 91 and a side portion 92 , and is made of ceramic as with the above-described packages P 1 and P 2 .
  • Bottom portion 91 has a first planar portion 94 for positioning CCD chip 81 and second planar portions 95 for positioning buffer amplifier modules 61 .
  • First planar portion 94 and second planar portions 95 are formed to be stepped with respect to each other.
  • Bottom portion 91 furthermore has a third planar portion 96 , and the third planar portion 96 is positioned between front surface 8 of package P 3 and second planar portions 95 and is formed to be stepped with respect to front surface 8 of package P 3 and second planar portions 95 .
  • CCD chip 81 has an energy ray sensitive portion 12 and is mounted on first planar portion 94 of bottom portion 91 so that the front surface side will be the energy ray incident surface and is fixed to the bottom portion 91 (package P 3 ).
  • Buffer amplifier modules 61 are thus positioned on second planar portions 95 , which differ from first planar portion 94 on which CCD chip 81 is positioned, and using the step difference between first planar portion 94 and second planar portions 95 , CCD chip 81 and buffer amplifier modules 61 are positioned proximally in the present modification example as well.
  • the signal transmission paths from CCD chip 81 to buffer amplifier modules 61 are made short and the parasitic capacitance of the signal transmission paths is made small.
  • the damping of the waveforms of signals output from CCD chip 81 can be restrained and the high-speed response properties can be improved.
  • the present invention is not restricted to the embodiments described above.
  • the solid-state imaging apparatus is not restricted to CCD chips 11 and 81 and may be formed of a photodiode (PD) array of amorphous silicon and a thin-film transistor (TFT) or may be a MOS type image sensor.
  • PD photodiode
  • TFT thin-film transistor
  • the present invention can be applied to a solid-state imaging apparatus, such as a CCD image sensor.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
US10/554,106 2003-04-24 2004-04-14 Solid-state imaging device Active 2025-11-22 US8243175B2 (en)

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JP2003-120343 2003-04-24
JPP2003-120343 2003-04-24
JP2003120343A JP4231328B2 (ja) 2003-04-24 2003-04-24 固体撮像装置
PCT/JP2004/005334 WO2004095831A1 (fr) 2003-04-24 2004-04-14 Dispositif d'imagerie a semi-conducteurs

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EP (1) EP1622367B1 (fr)
JP (1) JP4231328B2 (fr)
KR (1) KR101109278B1 (fr)
CN (1) CN100387051C (fr)
WO (1) WO2004095831A1 (fr)

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JP4490406B2 (ja) * 2006-10-11 2010-06-23 浜松ホトニクス株式会社 固体撮像装置
JP5743767B2 (ja) * 2011-07-13 2015-07-01 キヤノン株式会社 撮像素子ユニットおよび撮像装置
JP5844580B2 (ja) * 2011-09-05 2016-01-20 浜松ホトニクス株式会社 固体撮像素子及び固体撮像素子の実装構造
US9712769B2 (en) * 2011-12-28 2017-07-18 Nikon Corporation Imaging device
JP6004421B2 (ja) * 2012-03-30 2016-10-05 株式会社日立ハイテクノロジーズ 撮像素子、検査装置、及び検出装置
JP6325920B2 (ja) * 2014-07-02 2018-05-16 日本放送協会 高精細撮像素子用パッケージ
WO2017112671A1 (fr) 2015-12-23 2017-06-29 Praxair Technology, Inc. Four de verrerie présentant un meilleur taux de production

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KR20060006049A (ko) 2006-01-18
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CN100387051C (zh) 2008-05-07
EP1622367B1 (fr) 2012-02-22
KR101109278B1 (ko) 2012-02-06
US20070064134A1 (en) 2007-03-22
JP4231328B2 (ja) 2009-02-25
JP2004328386A (ja) 2004-11-18
EP1622367A4 (fr) 2009-12-02
CN1778103A (zh) 2006-05-24

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