TWI726441B - Flexible circuit substrate and chip-on-film package structure - Google Patents

Abstract

A flexible circuit substrate includes a flexible base, a plurality of leads, a solder resist layer, and at least one auxiliary pattern. The flexible base is defined to include a predetermined chip mounting area and a minimum allowable chip mounting area. The minimum allowable chip mounting area is within the predetermined chip mounting area. The leads are disposed on the flexible base and extend into the minimum allowable chip mounting area. The solder resist layer is disposed on the flexible base and partially covers the leads. The solder resist layer has an opening. The boundary of the opening aligns with and overlaps the boundary of the predetermined chip mounting area, or is located between the boundaries of the minimum allowable chip mounting area and the predetermined chip mounting area. The auxiliary pattern is disposed on the flexible base, and is located on the boundary of the predetermined chip mounting area or on the boundary of the minimum allowable chip mounting area. A chip-on-film package structure is also disclosed.

Description

Flexible circuit substrate and film-on-chip packaging structure

The present invention relates to a circuit substrate and a packaging structure, and particularly relates to a flexible circuit substrate and a film-on-chip packaging structure.

The chip on film (COF) package structure is a common package type of the driver chip of the liquid crystal display. Generally speaking, the flexible circuit substrate of the film-on-chip package structure includes a flexible film, pins and a solder mask on the surface of the flexible film. The solder resist layer partially covers the pins, and only exposes the chip setting area and the part where the pins are connected to external components, so as to prevent the pins from being damaged, contaminated or short-circuited.

However, when performing the coating or printing process of the solder mask, the solder mask may overflow due to fluid characteristics or differences in coating/printing accuracy, causing the solder mask to exceed the expected formation range. Especially when the solder mask is forming an opening to define the chip placement area, the solder mask material tends to accumulate at the intersection of the long and short sides of the opening (that is, the corner of the chip placement area), and excessive solder mask material overflows into it. Wafer setting area. In this way, the gap between the solder mask and the chip is likely to be too narrow, which affects the smoothness of filling the encapsulant into the bottom of the chip. Furthermore, the solder mask material overflowing into the chip setting area may also affect the electrical connection between the chip and the pins. Therefore, how to make the film-on-chip package structure reduce the problem of solder mask overflow is a topic that needs to be solved urgently in the field.

The invention provides a flexible circuit substrate, which can reduce the overflow of the solder mask and improve the accuracy of the formation position of the solder mask.

The present invention provides a film-on-chip packaging structure, which can avoid incomplete packaging of the packaging gel and improve electrical quality.

The flexible circuit substrate of the present invention includes a flexible substrate, a plurality of pins, a solder mask, and at least one auxiliary pattern. The flexible substrate is defined with a predetermined wafer setting area and a minimum allowable wafer setting area, and the minimum allowable wafer setting area is located in the predetermined wafer setting area. The multiple pins are arranged on the flexible substrate, and the multiple pins extend into the minimum allowable chip placement area. The solder mask is disposed on the flexible substrate and partially covers a plurality of pins. The solder mask layer has an opening, and the boundary of the opening is aligned and overlapped between the boundary of the predetermined wafer placement area or the boundary of the minimum allowable wafer placement area to the boundary of the predetermined wafer placement area. At least one auxiliary pattern is disposed on the flexible substrate, and at least one auxiliary pattern is located at the boundary of the predetermined chip placement area or the boundary of the minimum allowable chip placement area.

The chip-on-film package structure of the present invention includes the above-mentioned flexible circuit substrate and chip. The chip is arranged on the flexible circuit substrate and is located in the minimum allowable chip setting area. The chip is electrically connected to a plurality of pins.

Based on the above, because the flexible circuit substrate and the film-on-chip package structure of the present invention can be arranged on the boundary (especially the corner) of the predetermined chip placement area or the minimum allowable chip placement area by arranging the auxiliary pattern, and the auxiliary pattern is The first line segment and the second line segment correspondingly overlap the boundary of the predetermined wafer placement area or the minimum allowable wafer placement area. Thereby, the auxiliary pattern can prevent the material of the solder mask from overflowing into the predetermined chip placement area and/or the minimum allowable chip placement area. In this way, the boundary of the opening of the solder mask layer can be more accurately aligned and overlap the boundary of the predetermined chip arrangement area, or be between the predetermined chip arrangement area and the minimum allowable chip arrangement area with an allowable tolerance. Therefore, sufficient space can be maintained between the solder mask of the flexible circuit substrate and the chip to prevent the too narrow space from preventing the encapsulant from flowing smoothly into the bottom of the chip, thereby improving the filling quality of the encapsulant. Furthermore, the internal connection end of the pin can be guaranteed not to be covered by the solder mask, avoiding the problem of poor electrical connection between the chip and the pin, and the electrical quality of the thin film flip chip package structure can be improved. In addition, the auxiliary pattern can fill the non-wiring gaps of the flexible circuit substrate at the corners of the predetermined chip placement area and/or the minimum allowable chip placement area, thereby enhancing the strength of the flexible circuit substrate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The present invention will be explained more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, size, or size of the layers or regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIG. 1 is a schematic top view of a flexible substrate according to an embodiment of the present invention. FIG. 2 is a schematic top view of a flexible circuit substrate according to an embodiment of the present invention. FIG. 3 is a partial enlarged schematic cross-sectional view of the region R in FIG. 2. Please refer to FIGS. 1 and 2. In this embodiment, the flexible circuit substrate 10 includes a flexible substrate 100, a plurality of pins 120, a solder mask 160 (shown in FIG. 2), and at least one auxiliary Pattern 200. It should be noted here that, for the sake of clarity and convenience of description, the flexible substrate 100 shown in FIG. 1 has not yet been configured with a solder mask 160. The flexible circuit substrate 10 shown in FIG. 2 includes a solder mask 160 covering part of the surface of the flexible substrate 100 and portions of the pins 120, but the chip 140 is not shown (shown in FIG. 7) . In this embodiment, the material of the flexible substrate 100 is, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), carbonic acid Polycarbonate (PC) or other suitable flexible materials, but the present invention is not limited to this.

In this embodiment, the flexible substrate 100 may be defined with a predetermined wafer setting area 110 and a minimum allowable wafer setting area 130. The minimum allowable wafer setting area 130 is located within the predetermined wafer setting area 110. In this embodiment, the predetermined wafer setting area 110 can be defined as an optimal range required for setting the wafer 140 (shown in FIG. 7). The minimum allowable wafer setting area 130 may be defined as an area generated according to an inner tolerance when the predetermined wafer setting area 110 is formed.

In detail, as shown in FIG. 1, the boundary of the predetermined wafer setting area 110 includes a first long side 111 and a first short side 112. The first long side 111 and the first short side 112 respectively correspond to the long side and the short side of the chip 140. The first long side 111 is connected to the first short side 112 to form a first corner C1. In this embodiment, the predetermined wafer setting area 110 is, for example, a rectangle surrounded by two parallel first long sides 111 and two parallel first short sides 112, and therefore may have four first corners C1, The first corner C1 is approximately a right angle, but the invention is not limited to this. In other embodiments, the first corner C1 may also be rounded corners (ie, R corners).

The boundary of the minimum allowable wafer placement area 130 includes a second long side 131 and a second short side 132. The second long side 131 and the second short side 132 correspond to the long side and the short side of the chip 140 respectively. The second long side 131 is connected to the second short side 132 to form a second corner C2. In this embodiment, the minimum allowable wafer setting area 130 is, for example, a rectangle surrounded by two parallel second long sides 131 and two parallel second short sides 132, so it may have four second corners C2. , And the second corner C2 is approximately a right angle, but the present invention is not limited to this. In other embodiments, the second corner C2 may also be rounded corners (ie, R corners).

In this embodiment, a plurality of pins 120 are arranged on the flexible substrate 100. The pins 120 may be arranged along the first long side 111, and the pins 120 extend into the minimum allowable chip placement area 130. For example, the pin 120 includes an internal connection terminal 122 disposed in the minimum allowable chip placement area 130 to be electrically connected to the chip 140. The pin 120 may further include an external terminal 124 opposite to the internal terminal 122, and the external terminal 124 is located on the side of the flexible substrate 100 away from the predetermined chip placement area 110, so as to be connected to an external element (not shown). In this embodiment, the material of the pin 120 includes metal or metal alloy, for example, it is made of conductive metal material such as gold, copper, silver, palladium, aluminum or alloys thereof, but the present invention is not limited thereto.

Please refer to FIG. 2, the flexible circuit substrate 10 further includes a solder mask 160. The solder mask 160 is disposed on the flexible substrate 100 and partially covers the pins 120 to avoid oxidation, breakage and damage of the pins 120, and prevent bridging of the pins 120 caused by foreign matter covering. In this embodiment, the solder mask 160 may cover the parts of the pins 120, and expose the inner terminal 122 and the outer terminal 124 to be electrically connected to the chip 140 and external components, respectively. The material of the solder mask 160 is, for example, green paint, but the present invention is not limited to this. In this embodiment, the method of forming the solder mask 160 includes a coating process or a printing process.

In this embodiment, the solder mask 160 has an opening 163 to expose the predetermined chip placement area 110 and/or the minimum allowable chip placement area 130. More specifically, the predetermined wafer placement area 110 is defined by the opening 163 of the solder mask 160. The minimum allowable chip placement area 130 is further defined according to the internal tolerance value set by the allowable deviation of the opening 163 forming the solder mask layer 160. In other words, the predetermined wafer setting area 110 is a range of the opening 163 where the solder mask 160 is scheduled to be formed, and the minimum allowable wafer setting area 130 is a range defined inwardly from the predetermined wafer setting area 110 by a tolerance value. Therefore, any position between the boundary of the opening 163 and the boundary of the predetermined wafer setting area 110 or the boundary of the minimum allowable wafer setting area 130 to the boundary of the predetermined wafer setting area 110 is regarded as meeting the specification. Generally speaking, the minimum allowable chip placement area 130 is larger than the size of the chip 140, so that a gap is maintained between the chip 140 and the solder mask 160, so that the subsequent packaging compound 180 (marked in FIG. 7) can be smoothly filled into the bottom of the chip 140 . For example, when the wafer 140 is placed in the predetermined wafer setting area 110 according to a predetermined position, the shortest distance from the edge of the wafer 140 to the boundary of the predetermined wafer setting area 110 is 250 microns, and if the tolerance value of the opening 163 is set to ±150 Micrometers, the minimum allowable wafer setting area 130 is reduced by 150 micrometers from the boundary of the predetermined wafer setting area 110, that is, the shortest distance from the edge of the wafer 140 to the boundary of the minimum allowable wafer setting area 130 is 100 micrometers.

As shown in FIG. 2, in this embodiment, the boundary of the opening 163 is aligned and overlapped with the boundary of the predetermined wafer placement area 110. In detail, the boundary of the opening 163 includes the third long side 161 and the third short side 162. The third long side 161 aligns and overlaps the first long side 111, and the third short side 162 aligns and overlaps the first short side 112. From another perspective, the boundary of the opening 163 completely overlaps the boundary of the predetermined wafer placement area 110, but the present invention is not limited to this. In some embodiments, the boundary of the opening 163 may also be aligned and overlapped between the boundary of the minimum allowable wafer placement area 130 and the boundary of the predetermined wafer placement area 110. The above embodiments will be described in subsequent paragraphs.

Please refer to FIGS. 1, 2 and 3. In this embodiment, the flexible circuit substrate 10 further includes at least one auxiliary pattern 200 disposed on the flexible substrate 100. In this embodiment, the auxiliary pattern 200 is located at the boundary of the predetermined wafer setting area 110, but the invention is not limited to this. In some embodiments, the auxiliary pattern 200 may also be located at the boundary of the minimum allowable wafer placement area 130.

In detail, in this embodiment, at least one auxiliary pattern 200 is disposed at the first corner C1. As shown in FIG. 1 and FIG. 2, the number of auxiliary patterns 200 is, for example, four, respectively corresponding to the four first corners C1 of the predetermined wafer setting area 110, but the present invention is not limited to this. In some embodiments, the auxiliary pattern 200 can also be configured to overlap the first long side 111 or the first short side 112, and the number can be at least one to four or more than four, depending on the needs of the user. .

In this embodiment, the material of the auxiliary pattern 200 may be the same as or different from the material of the pin 120, including metal or metal alloy, for example, made of conductive metal materials such as gold, copper, silver, palladium, aluminum or alloys thereof. However, the present invention is not limited to this. In this embodiment, the auxiliary pattern 200 and the pins 120 can be made on the flexible substrate 100 at the same time with the same material. In this way, the auxiliary pattern 200 and the pin 120 can belong to the same film layer. In this way, the manufacturing process can be simplified and the manufacturing cost can be saved.

In detail, as shown in FIG. 3, at least one auxiliary pattern 200 of the flexible circuit substrate 10 is disposed at the first corner C1. In this embodiment, the at least one auxiliary pattern 200 may be a patterned raised structure 230. The patterned raised structure 230 constitutes a first line segment L1 and a second line segment L2 that are connected, and the first line segment L1 and the second line segment L2 overlaps the first long side 111 and the first short side 112 respectively at the first corner C1. More specifically, the edge of the patterned protrusion structure 230 has a first inner side wall 231 and a second inner side wall 232 connected to each other. The first inner side wall 231 may correspond to the first line segment L1, and the second inner side wall 232 may correspond to the second line segment L2, so that the patterned protruding structure 230 can form an L shape in a plan view. The first inner side wall 231 and the second inner side wall 232 respectively overlap the first long side 111 and the first short side 112, that is, the patterned protruding structure 230 may be located outside the predetermined wafer placement area 110, but the present invention does not This is limited.

Under the above arrangement, at least one auxiliary pattern 200 can be arranged at the first corner C1 and the first line segment L1 and the second line segment L2 formed by the patterned convex structure 230 (for example: the first inner side wall 221 and the second inner side wall 222) The first long side 111 and the first short side 112 of the predetermined wafer setting area 110 can be overlapped correspondingly. Therefore, when the solder mask layer 160 is formed on the flexible substrate 100, the material of the solder mask layer 160 can be prevented from overflowing into the predetermined chip placement area 110 by the hindrance of the patterned convex structure 230. In this way, the probability that the material of the solder mask 160 enters the predetermined chip placement area 110 can be reduced, and the opening 163 of the solder mask 160 can be aligned and overlapped with the predetermined chip placement area 110 more accurately.

In short, the flexible circuit substrate 10 of the present embodiment can be arranged by arranging the auxiliary pattern 200 at the corner of the predetermined chip arrangement area 110, and the first line segment L1 and the second line segment L2 of the auxiliary pattern 200 can overlap the predetermined chip arrangement. The first long side 111 and the first short side 112 of the area 110. In this way, the auxiliary pattern 200 can prevent the material of the solder mask 160 from overflowing into the predetermined chip placement area 110 or the minimum allowable chip placement area 130. In this way, the third long side 161 and the third short side 162 of the opening 163 of the solder mask 160 can align and overlap the first long side 111 and the first short side 112 more accurately, so that the opening 163 can be aligned and overlapped. In the predetermined wafer setting area 110. Therefore, the solder mask 160 will not overflow into the predetermined chip placement area 110 or the minimum allowable chip placement area 130, which will cause the space between the solder mask 160 and the chip 140 to be too narrow, thereby affecting the flow of the packaging glue 180 into the bottom of the chip 140 The fluency and reduce the integrity of the packaging of the packaging gel 180. Furthermore, the internal connection end 122 of the pin 120 can ensure that it will not be covered by the solder mask 160, thereby avoiding the problem of poor electrical connection between the chip 140 and the pin 120. In addition, the auxiliary pattern 200 can fill the non-wiring gaps of the flexible circuit substrate 10 at the corners of the predetermined chip placement area 110 and/or the minimum allowable chip placement area 130 to improve the strength of the flexible circuit substrate 10.

It must be noted here that the following embodiments follow the component numbers and part of the content of the above embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted, and the description of the omitted parts is omitted. Reference may be made to the foregoing embodiment, and the description of the following embodiments will not be repeated.

4 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to another embodiment of the present invention. Please refer to FIGS. 3 and 4, the flexible circuit substrate 10A of this embodiment is similar to the flexible circuit substrate 10 of the above-mentioned embodiment, but the difference is that the patterned convex structure 230 of at least one auxiliary pattern 200 is disposed in The second corner C2. Specifically, the first inner sidewall 231 and the second inner sidewall 232 of the patterned convex structure 230 respectively overlap the second long side 131 and the second short side 132 of the minimum allowable wafer placement area 130, that is, the patterned convex The starting structure 230 may be located between the minimum allowable wafer setting area 130 and the predetermined wafer setting area 110, but the invention is not limited to this. Under the above arrangement, the L-shaped pattern of the first line segment L1 and the second line segment L2 formed by the patterned convex structure 230 can correspond to the second long side 131 and the second short side 132 at the second corner C2. Under the above arrangement, when the material of the solder resist layer 160A partially overflows into the predetermined wafer setting area 110, the auxiliary pattern 200 can prevent the material of the solder resist layer 160A from continuing to overflow into the minimum allowable wafer setting area 130. As shown in FIG. 4, the first line segment L1 of the auxiliary pattern 200 can block the third long side 161A of the opening 163A of the solder mask 160A and continue to approach the minimum allowable chip placement area 130, and the second line segment L2 can also block the third short side. The edge 162A is close to the minimum allowable chip setting area 130, so that the solder mask 160A can be prevented from entering the minimum allowable chip setting area 130 or further covering the inner terminal 122. Thereby, the flexible circuit substrate 10A of this embodiment can achieve the same effect as the above-mentioned embodiment, so it will not be repeated here.

5 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to still another embodiment of the present invention. Please refer to FIG. 3 and FIG. 5, the flexible circuit substrate 10B of this embodiment is similar to the flexible circuit substrate 10 of the above embodiment, but the difference is that the auxiliary pattern 200A has a patterned opening 220. The patterned opening 220 is, for example, an opening formed after patterning the auxiliary pattern 200A, which can expose the flexible substrate 100. In this embodiment, the patterned opening 220 constitutes a first line segment L1A and a second line segment L2A. For example, the edge of the patterned opening 220 has a first inner side wall 221 and a second inner side wall 222 connected to each other. The first inner side wall 221 may correspond to the first line segment L1A, and the second inner side wall 222 may correspond to the second line segment L2A, so that the patterned opening 220 can be formed in an L shape in a plan view. In this embodiment, the first inner side wall 221 corresponds to overlap the first long side 111, and the second inner side wall 222 corresponds to overlap the first short side 112. In this way, the L-shaped pattern of the first line segment L1A and the second line segment L2A formed by the patterned opening 220 can overlap the first long side 111 and the first short side 112 at the first corner C1 correspondingly. In addition, as shown in FIG. 5, a part of the auxiliary pattern 200A is located in the predetermined wafer setting area 110, and the patterned opening 220 may be located outside the predetermined wafer setting area 110, but the present invention is not limited to this. Under the above configuration, when the material of the solder mask 160 flows through the auxiliary pattern 200A, part of the material will be filled into the patterned opening 220. Therefore, the material of the solder mask 160 can be slowed down by the auxiliary pattern 200A. In addition to its flow, the patterned opening 220 can also be blocked so that the material of the solder mask 160 will not overflow into the predetermined chip placement area 110. Thereby, the probability that the material of the solder mask 160 enters the predetermined chip placement area 110 can be reduced, and the boundary of the opening 163 of the solder mask 160 can be aligned and overlapped with the boundary of the predetermined chip placement area 110 more accurately. The flexible circuit substrate 10B of this embodiment can achieve the same effect as the above-mentioned embodiment, so it will not be repeated here.

FIG. 6 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to another embodiment of the present invention. 4, 5 and 6, the flexible circuit substrate 10C of this embodiment is similar to the flexible circuit substrates 10A, 10B of the above-mentioned embodiment, but the difference is that the auxiliary pattern 20 also includes the first The auxiliary pattern 200A at the corner C1 and the auxiliary pattern 200 arranged at the second corner C2. In this embodiment, the auxiliary pattern 200A has a patterned opening 220 and the patterned opening 220 constitutes a first line segment L1A and a second line segment L2A. The first line segment L1A and the second line segment L2A formed by the patterned opening 220 may overlap the first long side 111 and the first short side 112 at the first corner C1 correspondingly. The type of the auxiliary pattern 200A of this embodiment is substantially the same as that of the embodiment shown in FIG. 5, so it will not be repeated here. The auxiliary pattern 200 has a patterned convex structure 230, and the patterned convex structure 230 constitutes a first line segment L1 and a second line segment L2. The first line segment L1 and the second line segment L2 formed by the patterned convex structure 230 can overlap the second long side 131 and the second short side 132 of the minimum allowable chip placement area 130 at the second corner C2 correspondingly. The type of the auxiliary pattern 200 of this embodiment is substantially the same as that of the embodiment shown in FIG. 4, so it will not be repeated here. In this embodiment, the auxiliary pattern 200A arranged at the first corner C1 is a pattern with patterned openings 220, and the auxiliary pattern 200 arranged at the second corner C2 is a pattern with a patterned convex structure 230. However, the present invention The form of the auxiliary pattern 200A arranged at the boundary of the predetermined wafer setting area 110 and the auxiliary pattern 200 arranged at the boundary of the minimum allowable wafer setting area 130 is not limited to this. Under the above arrangement, the auxiliary pattern 200A arranged at the first corner C1 can be used to prevent the material of the solder mask 160 from entering the predetermined chip arrangement area 110. When the material of the solder mask 160 accumulates too much, it still flows in accidentally. When the chip placement area 110 is predetermined, the auxiliary pattern 200 disposed at the second corner C2 can further block the material of the solder mask 160 from entering the minimum allowable chip placement area 130. Thereby, the flexible circuit substrate 10C of this embodiment can achieve the same effect as the above-mentioned embodiment, so it will not be repeated here.

FIG. 7 is a schematic cross-sectional view of a chip-on-film package structure according to an embodiment of the present invention. Please refer to FIGS. 2, 3 and 7, the chip on film package structure 1 includes a flexible circuit substrate 10 and a chip 140 as shown in FIGS. 2 and 3. In this embodiment, a plurality of pins 120 are disposed on the flexible substrate 100, and the solder resist layer 160 covers a part of the pins 120. The chip 140 is disposed on the flexible circuit substrate 10 and is located in the minimum allowable chip placement area 130. Specifically, the chip 140 is disposed on the flexible substrate 100 and is electrically connected to the plurality of pins 120 in the minimum allowable chip setting area 130. The active surface of the chip 140 may have a plurality of bumps 142, and the chip 140 may be electrically connected to the internal terminals 122 of the pins 120 through the bumps 142. In this embodiment, the chip 140 may be, for example, a driving chip or the like. The material of the bump 142 includes metal or metal alloy, for example, is made of conductive metal material such as gold, copper, silver, palladium, aluminum or alloys thereof, but the present invention is not limited thereto.

In addition, the auxiliary pattern 200 and the pins 120 of this embodiment can be made of the same film layer. In this way, in addition to simplifying the manufacturing process and saving manufacturing costs, the configuration of the auxiliary pattern 200 will not affect the configuration process of the chip 140, thereby improving the structural reliability and electrical properties of the thin-film-on-chip package structure 1.

As shown in FIG. 7, the film-on-chip package structure 1 also includes a packaging glue 180 filled between the flexible substrate 100 and the chip 140 to cover the inner terminal 122 of the pin 120 and the bump 142 of the chip 140 Electrical contacts. For example, the packaging glue 180 can be applied along the periphery of the chip 140 in a dispensing manner, and flows into the bottom of the chip 140 through the gap between the solder mask 160 and the chip 140. More specifically, the encapsulant 180 covers the predetermined chip placement area 110 and may also partially cover the side surface of the chip 140. The encapsulant 180 can also cover a part of the solder mask 160, but the present invention is not limited to this. The material of the encapsulant 180 is, for example, an epoxy-based underfill material, but it is not limited to this. Since the auxiliary pattern 200 can prevent the solder mask 160 from overflowing into the predetermined chip placement area 110 and/or the minimum allowable chip placement area 130, sufficient space can be maintained between the solder mask 160 and the chip 140 without disturbing the package The glue 180 flows, so the packaging glue 180 can be smoothly filled into the bottom of the chip 140. In addition, the solder mask 160 will not affect the electrical connection between the bumps 142 of the chip 140 and the internal terminals 122 due to overflow into the minimum allowable chip placement area 130, so that the thin film flip chip package structure 1 has excellent electrical properties. quality.

In summary, the flexible circuit substrate of the present invention and the film-on-chip package structure including the same can be arranged on the boundary (especially the corner) of the predetermined chip placement area or the minimum allowable chip placement area by arranging the auxiliary pattern, and the auxiliary The first line segment and the second line segment of the pattern overlap the boundary of the predetermined wafer placement area or the minimum allowable wafer placement area. Thereby, the auxiliary pattern can prevent the material of the solder mask from overflowing into the predetermined chip placement area and/or the minimum allowable chip placement area. In this way, the boundary of the opening of the solder mask layer can be more accurately aligned and overlap the boundary of the predetermined chip arrangement area, or be between the predetermined chip arrangement area and the minimum allowable chip arrangement area with an allowable tolerance. Therefore, sufficient space can be maintained between the solder mask of the flexible circuit substrate and the chip to prevent the too narrow space from preventing the encapsulant from flowing smoothly into the bottom of the chip, thereby improving the filling quality of the encapsulant. Furthermore, the internal connection end of the pin can be guaranteed not to be covered by the solder mask, avoiding the problem of poor electrical connection between the chip and the pin, and the electrical quality of the thin film flip chip package structure can be improved. In addition, the auxiliary pattern can fill the non-wiring gaps of the flexible circuit substrate at the corners of the predetermined chip placement area and/or the minimum allowable chip placement area, thereby enhancing the strength of the flexible circuit substrate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

1: Thin film flip chip package structure 10, 10A, 10B, 10C: flexible circuit board 100: Flexible substrate 110: Predetermined wafer setting area 111: The first long side 112: The first short side 120: Pin 122: Inner end 124: External terminal 130: Minimum allowable wafer setting area 131: Second long side 132: Second short side 140: chip 142: bump 160, 160A: solder mask 161, 161A: the third long side 162, 162A: third short side 163, 163A: opening 180: Encapsulation colloid 20, 200, 200A: auxiliary pattern 220: Patterned opening 221, 231: the first inner side wall 222, 232: the second inner side wall 230: Patterned raised structure C1: The first corner C2: The second corner D1: the first distance D2: second distance L1, L1A: the first line segment L2, L2A: the second line segment R: area

FIG. 1 is a schematic top view of a flexible substrate according to an embodiment of the present invention. FIG. 2 is a schematic top view of a flexible circuit substrate according to an embodiment of the present invention. FIG. 3 is a partial enlarged schematic cross-sectional view of the region R in FIG. 2. 4 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to another embodiment of the present invention. 5 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to still another embodiment of the present invention. FIG. 6 is a schematic partial enlarged cross-sectional view of a region R of a flexible circuit substrate according to another embodiment of the present invention. 7 is a schematic cross-sectional view of a chip-on-film package structure according to an embodiment of the invention.

10: Flexible circuit board 100: Flexible substrate 110: Predetermined wafer setting area 111: The first long side 112: The first short side 120: Pin 122: Inner end 124: External terminal 130: Minimum allowable wafer setting area 131: Second long side 132: Second short side 160: solder mask 161: Third long side 162: Third short side 163: Opening 200: auxiliary pattern C1: The first corner C2: The second corner R: area

Claims (8)

A flexible circuit substrate comprising: a flexible substrate, defined with a predetermined wafer setting area and a minimum allowable wafer setting area, the minimum allowable wafer setting area is located in the predetermined wafer setting area, and the minimum allowable wafer The setting area is larger than the size of the chip; a plurality of pins are arranged on the flexible substrate, and the plurality of pins extend into the minimum allowable chip setting area; the solder mask is arranged on the flexible substrate On a flexible substrate and partially covering the plurality of pins, the solder mask has an opening, and the boundary of the opening overlaps the boundary of the predetermined chip placement area or the boundary of the minimum allowable chip placement area And at least one auxiliary pattern disposed on the flexible substrate, and the at least one auxiliary pattern is located at the boundary of the predetermined wafer setting area or the minimum allowable wafer The boundary of the placement area, wherein the boundary of the predetermined wafer placement area includes a first long side and a first short side, the first long side is connected to the first short side to form a first corner, and the minimum allowable wafer The boundary of the setting area includes a second long side and a second short side, the second long side is connected to the second short side to form a second corner, wherein the at least one auxiliary pattern has a connected first line segment and A second line segment, where the first line segment and the second line segment respectively overlap the first long side and the first short side or overlap the second long side and the second short side respectively, The length of the first line segment is less than the length of the second long side, and the length of the second line segment The degree is smaller than the length of the second short side. The flexible circuit substrate according to claim 1, wherein the at least one auxiliary pattern is disposed at the first corner or the second corner. The flexible circuit substrate according to claim 1, wherein the at least one auxiliary pattern has a patterned convex structure, and the patterned convex structure constitutes the first line segment and the second line segment . The flexible circuit substrate according to item 3 of the scope of patent application, wherein the edge of the patterned convex structure has a first inner side wall and a second inner side wall connected to each other, and the first inner side wall and the second inner side wall are connected to each other. The inner side walls respectively overlap the first long side and the first short side or overlap the second long side and the second short side respectively. The flexible circuit substrate according to claim 1, wherein the at least one auxiliary pattern has a patterned opening, and the patterned opening constitutes the first line segment and the second line segment. The flexible circuit substrate according to item 5 of the scope of patent application, wherein the edge of the patterned opening has a first inner side wall and a second inner side wall connected to each other, and the first inner side wall and the second inner side wall are connected The first long side and the first short side are overlapped correspondingly, or the second long side and the second short side are overlapped correspondingly, respectively. The flexible circuit substrate according to the first item of the scope of patent application, wherein the material of the plurality of pins and the at least one auxiliary pattern includes metal or metal alloy. A thin-film-on-chip packaging structure, including: the flexible circuit as described in any one of items 1 to 7 of the scope of patent application A substrate; and a chip disposed on the flexible circuit substrate and located in the minimum allowable chip setting area, wherein the chip is electrically connected to the plurality of pins.

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