TWI758160B - Flexible circuit substrate and chip on film package structure - Google Patents

Abstract

A flexible circuit substrate including a flexible film, a solder resist and a patterned circuit layer is provided. The flexible film has a chip bonding area. The solder resist is disposed on the flexible film and has an opening exposing the chip bonding area and an inner edge demarcated by the opening. The patterned circuit layer includes a plurality of leads and at least one reference mark. The at least one reference mark is located at at least one corner of the opening. A part of the at least one reference mark is located inside the chip bonding area and has a first end, and the other part is covered by the solder resist and has a second end. The shortest distance between the first end and the second end is equal to the allowable tolerance range of a predetermined position of the inner edge. A chip on film package structure is also provided.

Description

Flexible circuit substrate and thin film flip chip package structure

The present invention relates to a circuit substrate and a packaging structure, and in particular, to a flexible circuit substrate and a film-on-chip packaging structure including the same.

Generally speaking, the chip on film (COF) package structure is to bond the chip to the flexible circuit substrate by flip-chip bonding, and usually to protect the circuit on the flexible circuit substrate from scratches Or pollution causes short circuit, open circuit phenomenon and achieves the solder resist function, which will form a protective film on the flexible circuit substrate, which is called Solder Resist (SR). The solder mask layer forms an opening at the intended location of the die to define the die bonding area. However, when coating or printing the solder mask layer, the solder mask material may vary due to differences in fluid properties or coating/printing accuracy. Problems with overflow or insufficient coverage can result, causing the extent of the wafer bond area to exceed predetermined specifications. Especially at the corners of the wafer bonding area, excessive solder resist material tends to accumulate and overflow into a predetermined range of the wafer bonding area. In this way, the gap between the solder mask and the chip is likely to be too narrow, which affects the smoothness of the filling of the encapsulant into the bottom of the chip. Furthermore, the solder resist material overflowing into the die bonding area may also affect the electrical connection between the die and the circuit. Therefore, at present, it is usually measured manually with a ruler to confirm whether the actual opening formation position (physical specification) of the solder mask conforms to the design specification of the theoretical opening formation position (drawing specification) of the solder mask. . However, the confirmation process is often time-consuming and labor-intensive, which in turn increases a lot of labor and time costs and is also prone to the risk of contaminating the material.

The present invention provides a flexible circuit substrate and a chip-on-film packaging structure, which can reduce labor and time costs while reducing the probability of contaminating materials.

A flexible circuit substrate of the present invention comprises a flexible film, a solder resist layer and a patterned circuit layer. The flexible film has a die bond area. The solder resist layer is disposed on the flexible film and has an opening exposing the die bonding area and an inner edge defined by the opening. The patterned circuit layer includes a plurality of pins and at least one reference mark. At least one reference mark is located at at least one corner of the opening and a part of the reference mark is located in the die bonding area and has a first end, and the other part is covered by the solder mask and has a second end. The shortest distance between the first end portion and the second end portion is equal to the allowable tolerance range of the predetermined formation position of the inner edge.

In an embodiment of the present invention, the inner edge has a first side and a second side that are perpendicular to each other, and the first side and the second side are connected to form a corner at at least one corner.

In an embodiment of the present invention, the above-mentioned at least one reference mark is a rectangular strip pattern and the number is at least two, and the at least two reference marks are respectively located on the first side and the second side forming the corner.

In an embodiment of the present invention, two opposite side walls of the above-mentioned rectangular strip pattern respectively form a first end portion and a second end portion.

In an embodiment of the present invention, the at least one reference mark has a first portion located in the die bonding area, a second portion covered by the solder mask, and a third portion connecting the first portion and the second portion. The first portion and the second portion have sections parallel to the first side and the second side.

In an embodiment of the present invention, the shapes of the first portion and the second portion include an L-shape or an arc shape.

In an embodiment of the present invention, a side wall of the first portion described above constitutes a first end portion, and a side wall of the second portion constitutes a second end portion.

In an embodiment of the present invention, the above-mentioned at least one reference mark is not coupled to a plurality of pins.

In an embodiment of the present invention, the above-mentioned at least one reference mark is a plurality of reference marks and is respectively located at four corners of the opening.

A film-on-chip encapsulation structure of the present invention includes the above-mentioned flexible circuit substrate, a chip and an encapsulation colloid. The chip is disposed in the chip bonding area and is electrically connected to a plurality of pins. The encapsulant is filled at least between the chip and the flexible film. The wafer exposes at least one reference mark.

Based on the above, the present invention sets reference marks on the corners of the opening of the solder mask, and designs the reference marks so that the shortest distance between the first end and the second end is equal to the inner edge of the solder mask defined by the opening The allowable tolerance range of the predetermined formation position, so that it can be directly judged by the appearance pattern whether the solder mask has overflow exceeding the specification or insufficient coverage. Identify time, labor costs, and risk of contaminating materials, so you can reduce labor and time costs while reducing the chance of contaminating materials.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Directional terms (eg, up, down, right, left, front, back, top, bottom) as used herein are used for reference only to the drawings and are not intended to imply absolute orientation.

The present invention is more fully described with reference to the drawings of this embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the repeated descriptions will not be repeated in the following paragraphs.

FIG. 1A is a partial top schematic view of a chip on film package structure according to an embodiment of the present invention. FIG. 1B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 1A . Please refer to FIG. 1A and FIG. 1B , in this embodiment, the chip on film package structure 1 includes a flexible circuit substrate 10 , a chip 20 and an encapsulant 30 , wherein the flexible circuit substrate 10 includes a flexible circuit substrate having a chip bonding area 101 . The flexible film 100 and the chip 20 are disposed in the die bonding area 101 , and the encapsulant 30 is filled at least between the chip 20 and the flexible film 100 . Here, the material of the flexible film 100 is, for example, polyimide (PI), polyethylene terephthalate (PET), polyethersulfone (PES), carbonate (polycarbonate, PC) or other suitable flexible material, the wafer 20 is, for example, a drive wafer or any suitable wafer.

In addition, the flexible circuit substrate 10 further includes a solder resist layer 110 and a patterned circuit layer 120, wherein the solder resist layer 110 is disposed on the flexible film 100 and has an opening OP exposing the die bonding area 101 and is defined by the opening OP out the inner edge of IE. On the other hand, the patterned circuit layer 120 includes a plurality of pins 122 electrically connected to the chip 20 and at least one reference mark 124 , the at least one reference mark 124 is located at at least one corner C of the opening OP, wherein the at least one reference mark 124 is A part P1 is located in the die bonding area 101 and is exposed by the die 20 and has a first end E1, and another part P2 of the at least one reference mark 124 is covered by the solder mask 110 and has a second end E2. Here, the solder resist layer 110 and the patterned circuit layer 120 may be any suitable materials, which are not limited in the present invention.

In the present embodiment, the reference mark 124 is disposed on the corner C of the opening OP of the solder resist 110 and the shortest distance between the first end E1 and the second end E2 of the reference mark 124 is equal to that of the inner edge IE of the solder resist 110 The allowable tolerance range R of the predetermined formation position, in this way, it is possible to directly judge whether the solder mask layer 110 has overflow exceeding the specification or insufficient coverage by the appearance pattern, and there is no need to manually measure with a ruler. Reduce confirmation time, labor costs, and risk of contaminating materials, thereby reducing labor and time costs while reducing the chance of contaminating materials.

For example, the allowable tolerance range R of the predetermined formation position of the inner edge IE of the solder mask layer 110 is, for example, ±150 μm (ie, the upper limit of deviation is +150 μm, and the lower limit of deviation is −150 μm). The shortest distance between the predetermined formation position from the end portion E1 to the inner edge IE and the predetermined formation position from the second end portion E2 to the inner edge IE is not more than 150 μm, but the invention is not limited to this, and the allowable tolerance range R can be determined according to the wafer bonding area 101 size adjusted.

In one embodiment, the inner edge IE has a first side IE1 and a second side IE2 that are perpendicular to each other, and the first side IE1 and the second side IE2 are connected to form a corner IE3 at the corner C. Further, the die bonding area 101 has two opposite long sides and two short sides, and the first side IE1 may be the long side located in the die bonding area 101 , and the second side IE2 may be the short side located in the die bonding area 101 . side, but the present invention is not limited to this. In addition, as shown in FIG. 1A , the number of at least one reference mark 124 can be multiple (eight are schematically shown in FIG. 1A ) and are respectively located at four corners C of the opening OP, wherein the reference marks on each corner C are The number of the marks 124 is two, and they are respectively arranged perpendicular to the first side IE1 and the second side IE2, but the invention is not limited thereto.

In one embodiment, the reference marks 124 may be rectangular strip patterns 124 ′ and the number is at least two. In other words, the corner C may include at least two reference marks 124 of the rectangular strip patterns 124 ′, wherein at least two The reference marks 124 are respectively located on the first side IE1 and the second side IE2 forming the corner IE3, as shown in FIG. 1B , but the present invention is not limited thereto. In other embodiments, the reference marks may be set according to actual design requirements. Available in different numbers and shapes.

In one embodiment, the two opposite side walls of the rectangular strip pattern 124' respectively form the first end E1 and the second end E2. For example, the rectangular strip pattern 124' has two opposite long sides and opposite sides. The two short sides of the first end portion E1 and the two opposite side walls of the second end portion E2 respectively constitute the two short sides thereof, but the present invention is not limited to this. The two opposite side walls of the one end portion E1 and the second end portion E2 may also be the two long sides.

In one embodiment, the corner C is a blank area on the flexible circuit substrate 10 (without functional pins), so the reference marks 124 disposed thereon are not coupled to the pins 122 . Furthermore, since the blank area has a large space and will not affect the circuit connection on the flexible circuit substrate 10 , the reference mark 124 can be designed without affecting the electrical capability of the flexible circuit substrate 10 . There is greater flexibility for space arrangement below, but the present invention is not limited to this.

In one embodiment, the pins 122 and the reference marks 124 of the patterned circuit layer 120 are formed by, for example, the same process and the same material. In other words, the pins 122 and the reference marks 124 are integrally formed. Not limited to this.

It must be noted here that the following embodiments use the element numbers and parts of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted, and the description of the omitted part is omitted. Reference may be made to the foregoing embodiments, and detailed descriptions in the following embodiments will not be repeated.

FIG. 2A is a partial top view of a chip on film package structure according to another embodiment of the present invention. FIG. 2B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 2A . Referring to FIGS. 2A and 2B , the chip on film packaging structure 1 a of the present embodiment is similar to the chip on film packaging structure 1 in the above-mentioned embodiment, and the difference lies in: the patterned circuit of the chip on film packaging structure 1 a in this embodiment The reference mark 124a of the layer 120a has a first portion P1a located within the die bonding area 101, a second portion P2a covered by the solder mask 110, and a third portion P3a connecting the first portion P1a and the second portion P2a, wherein the first portion P1a and the second portion P2a have sections parallel to the first side IE1 and the second side IE2 of the inner edge IE of the solder mask 110 . Further, in this embodiment, the segment P1a1 of the first portion P1a parallel to the first side IE1 is connected with the segment P1a2 parallel to the second side IE2 to form an L-shaped shape, and the second portion P2a is parallel to the region of the first side IE1 The segment P2a1 is connected with the segment P2a2 parallel to the second side IE2 to form an L-shaped shape, and the third portion P3a can connect the L-shaped turning point of the first portion P1a (ie the intersection of the segment P1a1 and the segment P1a2) and the second portion P2a The L-shaped turning point (ie, the intersection of the segment P2a1 and the segment P2a2 ), but the invention is not limited to this, in other embodiments, the first part and the second part may have other shapes.

In one embodiment, a side wall of the first portion P1a constitutes the first end portion E1a, and a side wall of the second portion P2a constitutes the second end portion E2a, wherein the side wall of the first portion P1a constituting the first end portion E1a is, for example, the first portion P1a is farthest from the side wall of the inner edge IE, and the side wall of the second portion P2a constituting the second end E2a is, for example, the side wall of the second portion P2a farthest from the inner edge IE, but the invention is not limited thereto.

FIG. 3A is a partial top schematic view of a chip on film package structure according to still another embodiment of the present invention. FIG. 3B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 3A . Referring to FIGS. 3A and 3B , the chip on film packaging structure 1 b of this embodiment is similar to the chip on film packaging structure 1 a in the above-mentioned embodiment, and the difference lies in that the patterned circuit of the chip on film packaging structure 1 b in this embodiment is different. The shape of the first portion P1b and the second portion P2b of the reference mark 124b of the layer 120b is arc-shaped. Further, the first part P1b is parallel to the segment P1b1 of the first side IE1 and the segment P1b2 parallel to the second side IE2 and the second part P2b is parallel to the segment P2b1 of the first side IE1 and the segment P2b2 parallel to the second side IE2 The arc can be connected according to the turning radian of the corner IE3 of the inner edge IE, and the third part P3b can connect the arc apex of the first part P1b and the arc apex of the second part P2b, but the invention is not limited thereto.

In one embodiment, a side wall of the first portion P1b constitutes the first end portion E1b, a side wall of the second portion P2b constitutes the second end portion E2b, and the first end portion E1b and the second end portion E2b may be similar to the first end portion E1b and the second end portion E2b. The end portion E1a and the second end portion E2a will not be repeated here.

To sum up, in the present invention, reference marks are set on the corners of the opening of the solder mask, and the reference marks are designed so that the shortest distance between the first end and the second end is equal to the distance of the solder mask defined by the opening. The allowable tolerance range of the predetermined formation position of the inner edge. In this way, it is possible to directly judge whether the solder mask has overflow exceeding the specification or insufficient coverage by the appearance graphics, and no need to manually measure with a ruler. , reduce the confirmation time, labor expenditure and the risk of contaminating materials, so it can reduce the probability of contaminating materials while reducing labor and time costs. In addition, when the corner is a blank area on the flexible circuit substrate, since the blank area has a large space and will not affect the circuit connection on the flexible circuit substrate, the reference mark can be designed without affecting the flexible circuit substrate. Under the electrical capability of the flexible circuit substrate, there is greater flexibility in spatial arrangement.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

1, 1a, 1b: Thin film flip chip packaging structure 10: Flexible circuit substrate 100: Flexible film 110: Solder mask 120, 120a, 120b: patterned circuit layer 122: pin 124, 124a, 124b: Reference marks 124': Rectangular strip pattern 101: Wafer Bonding Area 20: Wafer 30: Encapsulating colloid C: corner E1, E1a, E1b: first end E2, E2a, E2b: second end IE: inner edge IE1: first side IE2: Second side IE3: Corner OP: opening P1, P2: Partially P1a, P1b: Part 1 P2a, P2b: Part II P3a, P3b: Part III P1a1, P1a2, P2a1, P2a2: Segments R: Allowable tolerance range

FIG. 1A is a partial top schematic view of a chip on film package structure according to an embodiment of the present invention. FIG. 1B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 1A . FIG. 2A is a partial top view of a chip on film package structure according to another embodiment of the present invention. FIG. 2B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 2A . FIG. 3A is a partial top schematic view of a chip on film package structure according to still another embodiment of the present invention. FIG. 3B is an enlarged schematic view of a corner portion of the wafer bonding area in FIG. 3A . It should be noted that, for the sake of clarity, the wafer, solder mask and encapsulant of FIGS. 1A , 2A and 3A are represented by perspective drawing.

101: Wafer Bonding Area

110: Solder mask

124: Reference mark

124': Rectangular strip pattern

C: corner

E1: first end

E2: Second end

IE: inner edge

IE1: first side

IE2: Second side

IE3: Corner

P1, P2: Partially

R: Allowable tolerance range

Claims (10)

A flexible circuit substrate, comprising: A flexible film with a die bond area; a solder mask layer disposed on the flexible film, wherein the solder mask layer has an opening exposing the die bonding area and an inner edge defined by the opening; and The patterned circuit layer includes a plurality of pins and at least one reference mark, the at least one reference mark is located at at least one corner of the opening, wherein a part of the at least one reference mark is located in the die bonding area and has a first reference mark. one end, the other part of the at least one reference mark is covered by the solder mask and has a second end, the shortest distance between the first end and the second end is equal to the inner The allowable tolerance range for the intended formation position of the edge. The flexible circuit substrate according to claim 1, wherein the inner edge has a first side and a second side that are perpendicular to each other, and the first side and the second side are connected to form the at least one corner. corner. The flexible circuit substrate according to claim 2, wherein the at least one reference mark is a rectangular strip pattern and the number is at least two, and the at least two reference marks are respectively located on the first and second reference marks forming the corners. one side and the second side. The flexible circuit substrate according to claim 3, wherein two opposite side walls of the rectangular strip pattern constitute the first end portion and the second end portion, respectively. The flexible wiring substrate of claim 2, wherein the at least one reference mark has a first portion located in the die bonding region, a second portion covered by the solder mask, and connected to the first portion A third portion of the second portion, the first portion and the second portion have sections parallel to the first side and the second side. The flexible circuit substrate according to claim 5, wherein the shapes of the first part and the second part include an L-shape or an arc shape. The flexible circuit board according to claim 5, wherein a side wall of the first portion constitutes the first end portion, and a side wall of the second portion constitutes the second end portion. The flexible circuit substrate of claim 1, wherein the at least one reference mark is not coupled to the plurality of pins. The flexible circuit substrate according to claim 1, wherein the at least one reference mark is a plurality of reference marks, which are respectively located at four corners of the opening. A film-on-chip packaging structure, comprising: The flexible circuit substrate according to any one of claim 1 to claim 9; a chip, disposed in the chip bonding area and electrically connected to the plurality of pins, wherein the chip exposes the at least one reference mark; and The encapsulant is filled at least between the chip and the flexible film.

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