CN113594126A - Flexible circuit substrate and chip-on-film package structure - Google Patents
Flexible circuit substrate and chip-on-film package structure Download PDFInfo
- Publication number
- CN113594126A CN113594126A CN202010553325.8A CN202010553325A CN113594126A CN 113594126 A CN113594126 A CN 113594126A CN 202010553325 A CN202010553325 A CN 202010553325A CN 113594126 A CN113594126 A CN 113594126A
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- circuit substrate
- flexible circuit
- chip
- outer lead
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- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 230000005540 biological transmission Effects 0.000 claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 claims abstract description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 238000005538 encapsulation Methods 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 description 49
- 239000007787 solid Substances 0.000 description 11
- 239000010409 thin film Substances 0.000 description 7
- 238000002845 discoloration Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000006748 scratching Methods 0.000 description 2
- 230000002393 scratching effect Effects 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
Abstract
本发明提供一种可挠性线路基板，包括可挠性薄膜、多个引脚以及防焊层。可挠性薄膜具有位于可挠性薄膜两侧的二个传输区域与位于二个传输区域之间的封装区域。封装区域内具有芯片接合区、环绕芯片接合区的覆盖区与位于覆盖区外侧的外接区。多个引脚设置于可挠性薄膜上且位于封装区域内。多个引脚包括多个内引脚部与多个外引脚部，多个内引脚部延伸入芯片接合区内，多个外引脚部自覆盖区内延伸至外接区且在二个传输区域之间相邻排列，其中最外侧的外引脚部分别具有至少一镂空图案。防焊层设置于可挠性薄膜上且位于覆盖区。防焊层局部覆盖多个引脚并暴露出芯片接合区与外接区。另提供一种薄膜覆晶封装结构。
The invention provides a flexible circuit substrate, comprising a flexible film, a plurality of pins and a solder resist layer. The flexible film has two transmission areas located on both sides of the flexible film and an encapsulation area located between the two transmission areas. The package area includes a chip bonding area, a covering area surrounding the chip bonding area, and an external area outside the covering area. A plurality of pins are arranged on the flexible film and located in the package area. The plurality of pins include a plurality of inner pin portions and a plurality of outer pin portions, the plurality of inner pin portions extend into the chip bonding area, and the plurality of outer pin portions extend from the coverage area to the outer area and are located between the two The transmission areas are arranged adjacent to each other, wherein the outermost outer pin portions respectively have at least one hollow pattern. The solder mask is arranged on the flexible film and is located in the coverage area. The solder mask partially covers the plurality of pins and exposes the chip bonding area and the external area. In addition, a film-on-chip packaging structure is provided.
Description
Technical Field
The present invention relates to circuit substrates and packaging structures, and more particularly to a flexible circuit substrate and a chip-on-film packaging structure.
Background
A Chip-On-Film (COF) package structure is a package structure applying tape automated bonding technology. Since the bonding between the COF structure and other components (such as a panel, etc.) needs to be performed with high density, alignment marks (alignment marks) for bonding external leads are usually designed in the blank region between the transmission region of the flexible film and the external leads, and the alignment marks are usually solid metal patterns formed during the lead forming process, and the accuracy of the bonding operation of the external leads is ensured by confirming the corresponding coincidence of the alignment marks and the alignment patterns on the other components in shape and position.
However, as the density of integrated circuits increases, the solid alignment marks located on the blank area are closer to the transmission area, and the mechanism driving the flexible film to move on the platform or the bumps on the Spacer tape (Spacer) wound together with the chip-on-film package structure are likely to cause damage or friction discoloration of the solid alignment marks, which further causes reflection or deformation of the alignment marks to deteriorate the alignment accuracy of the alignment marks, and reduces the yield of the connection between the chip-on-film package structure and other components.
Disclosure of Invention
The invention aims at a flexible circuit substrate and a thin film flip chip packaging structure, and the hollow pattern used as an alignment mark can have better alignment precision so as to increase the joint yield between the thin film flip chip packaging structure and other components.
According to an embodiment of the invention, a flexible circuit substrate includes a flexible film, a plurality of leads and a solder mask. The flexible film is provided with two transmission areas positioned at two sides of the flexible film and a packaging area positioned between the two transmission areas. The packaging area is provided with a chip bonding area, a covering area surrounding the chip bonding area and an external connection area positioned outside the covering area. The plurality of pins are arranged on the flexible film and positioned in the packaging area. The plurality of pins comprise a plurality of inner pin parts and a plurality of outer pin parts, the inner pin parts extend into the chip bonding area, the outer pin parts extend from the covering area to the outer connection area and are adjacently arranged between the two transmission areas, and the outer pin parts on the outermost sides are respectively provided with at least one hollow pattern. The solder mask layer is arranged on the flexible film and is positioned in the covering area. The solder mask layer partially covers the plurality of pins and exposes the chip bonding area and the external connection area.
In an embodiment of the invention, the outermost outer lead portions are two outer lead portions closest to the two transmission areas.
In an embodiment of the invention, the at least one hollow pattern penetrates through the outermost outer lead portion and exposes the flexible film.
In an embodiment of the invention, the outermost outer lead portion is a dummy lead.
In an embodiment of the invention, the at least one hollow pattern is rectangular, circular, T-shaped, cross-shaped or a combination thereof in a top view.
In an embodiment of the invention, the at least one hollow pattern includes two hollow patterns.
In an embodiment of the invention, the two hollow patterns are arranged along an extending direction of the outer lead portion.
In an embodiment of the invention, the width of the outermost outer lead portion is greater than the width of the remaining outer lead portions.
In an embodiment of the invention, a width of the outermost outer lead portion is between 100 micrometers and 350 micrometers.
In an embodiment of the invention, a shortest distance between the outermost outer lead portion and the edge of the flexible film is not less than 3.5 mm.
The invention provides a chip-on-film package structure, which comprises the flexible circuit substrate and a chip. The chip is arranged on the flexible circuit substrate and is positioned in the chip bonding area, wherein the chip is electrically connected with the plurality of inner pin parts.
In view of the above, in the chip-on-film package structure of the present invention, the at least one hollow pattern is formed on the outermost outer lead portion of the flexible circuit substrate, and with the aid of the light source (positive light source or backlight source), the alignment pattern on the other component (e.g., panel) located below can be viewed through the hollow pattern, so that the alignment mark can be used as an alignment mark when the chip-on-film package structure is bonded to the other component. In addition, because the hollow pattern is located on the outer pin part at the outermost side, compared with the solid alignment mark designed on the blank area between the transmission area and the pin, the hollow pattern can be far away from the transmission area, so that the damage or friction discoloration of the alignment mark caused by the mechanism driving the flexible circuit substrate to move on the machine table or the salient points on the spacing belt can be avoided, and the condition that the thin film flip chip packaging structure and other components cannot be aligned accurately due to the damage and discoloration of the alignment mark can be further prevented. In other words, the hollow pattern on the flexible circuit substrate for use as the alignment mark can have better alignment accuracy, so as to increase the bonding yield between the COF package structure and other components.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention.
Fig. 1B is an enlarged schematic view of the region a of fig. 1A.
Fig. 1C is a partially enlarged schematic view of the chip-on-film package structure of fig. 1A when being bonded with other components.
Fig. 1D is a partial top view of a chip on film package structure in the prior art.
Fig. 2 is a partial top view of a chip-on-film package structure according to another embodiment of the invention.
Fig. 3 is a partial top view of a chip on film package structure according to another embodiment of the invention.
Description of the reference numerals
10 transport region
12, a transmission hole
20 encapsulation area
202 chip bonding area
204 coverage area
206 external connection area
30 other Components
31 alignment pattern
100. 100a, 100b chip-on-film package structure
110 flexible circuit board
112 flexible film
114. 115 pin
1141 inner lead part
1142. 1142' outer lead part
1142a, 1142a1, 1142a2 hollow pattern
1152 solid contraposition mark
116 welding prevention layer
120: chip
A is a region
A1 blank area
D the direction of extension
E, edge
w1, w2 width
L is the shortest distance
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness, dimensions, or dimensions of layers or regions in the figures may be exaggerated for clarity.
Fig. 1A is a schematic top view of a chip-on-film package structure according to an embodiment of the invention. Fig. 1B is an enlarged schematic view of the region a of fig. 1A. Fig. 1C is a partially enlarged schematic view of the chip-on-film package structure of fig. 1A when being bonded with other components. Fig. 1D is a partial top view of a chip on film package structure in the prior art. Referring to fig. 1A to fig. 1C, in the present embodiment, the chip-on-film package structure 100 includes a flexible circuit substrate 110 and a chip 120, wherein the flexible circuit substrate 110 includes a flexible film 112, a plurality of leads 114 and a solder mask 116.
Further, the flexible film 112 has two transmission regions 10 respectively located at two sides and a packaging region 20 located between the two transmission regions 10, wherein the transmission regions 10 may have transmission holes 12 for transmission and positioning. The package region 20 has a die attach region 202, a footprint 204 surrounding the die attach region 202, and a circumscribing region 206 located outside the footprint 204. The flexible film 112 may be made of polyethylene terephthalate (PET), Polyimide (PI), Polyether (PES), Polycarbonate (PC), or other suitable flexible materials.
The plurality of leads 114 are disposed on the flexible film 112 and located in the package region 20. The leads 114 include inner lead portions 1141 and outer lead portions 1142, wherein the inner lead portions 1141 extend into the chip bonding region 202, and the outer lead portions 1142 extend from the covering region 204 to the outer region 206 and are adjacently arranged between the two transmission regions 10. In addition, the outermost outer lead portions 1142' have at least one hollow pattern 1142a, respectively.
On the other hand, the solder mask 116 is disposed on the flexible film 112 and located in the covering region 204, and the solder mask 116 partially covers the plurality of leads 114 and exposes the chip bonding region 202 and the external connection region 206. The chip 120 is disposed on the flexible circuit substrate 110 and located in the chip bonding region 202, wherein the chip 120 is electrically connected to the plurality of inner lead portions 1141. More specifically, the chip 120 is electrically connected to the inner lead portions 1141 through metal bumps (not shown).
In the flip-chip on film package structure 100 of the present embodiment, since the hollow pattern 1142a of the flexible circuit substrate 110 is transparent, the lower pattern can be observed through the hollow pattern 1142a with the aid of a light source (a front light source or a back light source), so that the flip-chip on film package structure 100 can be used as an alignment mark when bonding other components (such as a panel). More specifically, referring to fig. 1C, when the bonding operation between the outer lead portion 1142 of the chip-on-film package 100 and the electrical terminals (not shown) of the other component 30 is performed, whether the shape of the light-transmissive hollow pattern 1142a is overlapped with the alignment pattern 31 of the other component 30 can be observed through the light-transmissive hollow pattern 1142a, so that the outer lead portion 1142 and the electrical terminals can be accurately bonded. In addition, since the hollow pattern 1142a is disposed on the outermost outer lead portion 1142', compared to the solid alignment mark 1152 designed on the blank area a1 between the transmission area 10 and the lead 115 in fig. 1D, the hollow pattern 1142a can be farther from the transmission area 10, so as to prevent a mechanism (such as a ratchet or a roller) on the machine that drives the flexible circuit substrate 110 to move during transmission from scratching the alignment mark, or prevent the bump arranged on the spacer tape near the transmission area 10 from rubbing and damaging the alignment mark when the flexible circuit substrate 110 and the spacer tape are rolled up, thereby preventing the occurrence of the situation that the thin film flip chip package structure 100 and other components cannot be aligned accurately due to the damage of the alignment mark. In other words, the hollow pattern 1142a on the flexible circuit substrate 110 for being the alignment mark can have a better alignment precision to increase the bonding yield between the thin film flip chip package structure and other components.
Further, the current solid alignment marks 1152 are typically formed in the same process as the leads 115, typically by etching a copper layer to form the respective discrete leads 115 and solid alignment marks 1152 and forming a tin-plated layer on the copper layer. If the solid alignment mark 1152 rubs against the driving mechanism on the machine or the bumps on the spacer tape, the solid alignment mark 1152 may change color to affect the interpretation of the image, and the situation of inaccurate alignment is caused. Therefore, through the design of the hollow pattern 1142a in this embodiment, even if the tin layer on the outermost outer lead portion 1142' is rubbed and discolored, the interpretation of the hollow pattern 1142a will not be affected, and therefore, the occurrence of poor alignment can be avoided.
In one embodiment, the outermost outer lead portions 1142' may be the two outer lead portions 1142 closest to the two transmission regions 10. However, the present invention is not limited thereto, and the number and the position of the outermost outer lead portions 1142' may depend on the actual design requirement.
In an embodiment, the at least one hollow pattern 1142a may penetrate through the outermost outer lead portion 1142' and expose the flexible film 112, so that the light source may be selected to use a positive light source or a negative light source, so as to make the light source more flexible in selection, but the invention is not limited thereto.
In an embodiment, the outermost outer lead portion 1142' is, for example, a dummy lead (dummy lead), but the invention is not limited thereto. Here, the dummy pins are, for example, located in the area of the flexible film 112 where no signal pin passes through, and are only disposed to reinforce the structural strength of the flexible film 112.
In an embodiment, as shown in fig. 1A and 1B, the hollow pattern 1142a may be a plurality of hollow patterns 1142 a. For example, the hollow pattern 1142a may include two hollow patterns 1142a1 and 1142a 2. In addition, the shape of the hollow pattern 1142a may be rectangular, circular, T-shaped, cross-shaped or a combination thereof in a top view. For example, the two hollow patterns 1142a1 and 1142a2 can be a combination of a circle and a rectangle, respectively. However, the invention is not limited thereto, and in other embodiments, the number and the shape of the plurality of hollow patterns 1142a may have different combination embodiments.
In an embodiment, the two hollow patterns 1142a1 and 1142a2 may be arranged along the extending direction D of the outer lead portion 1142. However, the invention is not limited thereto, and the two hollow patterns 1142a1 and 1142a2 may have different arrangements according to the actual design requirement.
In an embodiment, the width w1 of the outermost outer lead portion 1142 'may be greater than the width w2 of the remaining outer lead portions 1142, so that the outermost outer lead portion 1142' has a larger space for disposing the hollow pattern 1142 a. For example, the width w1 of the outermost outer lead portion 1142' may be between 100 micrometers (μm) and 350 micrometers, and the width w2 of the remaining outer lead portions 1142 may be between 20 micrometers and 40 micrometers. However, the present invention is not limited thereto, and the width w1 of the outermost outer lead portion 1142' and the width w2 of the remaining outer lead portions 1142 can be adjusted according to the actual design requirement.
In one embodiment, the shortest distance L from the outermost outer lead portion 1142 'to the edge E of the flexible film 112 is provided to avoid scratching the outermost outer lead portion 1142' during the driving process, thereby reducing the bonding yield of the thin film flip chip package structure 100. For example, the shortest distance L may be not less than 3.5 millimeters (mm), but the present invention is not limited thereto.
It should be noted that, in the following embodiments, the component numbers and part of the contents of the above embodiments are used, wherein the same or similar component numbers are used to indicate the same or similar components, and the descriptions of the same technical contents are omitted, and the description of the omitted parts can refer to the foregoing embodiments, and the descriptions of the following embodiments are not repeated.
Fig. 2 is a partial top view of a chip-on-film package structure according to another embodiment of the invention. Referring to fig. 2, the chip-on-film package structure 100a of the present embodiment is similar to the chip-on-film package structure 100 of the previous embodiment, and the difference is: the two hollow patterns 1142a1 and 1142a2 can be a combination of T-shape and rectangle, respectively.
Fig. 3 is a partial top view of a chip on film package structure according to another embodiment of the invention. Referring to fig. 3, the chip-on-film package structure 100b of the present embodiment is similar to the chip-on-film package structure 100 of the previous embodiment, and the difference is: the two hollow patterns 1142a1 and 1142a2 can be a combination of a cross and a T, respectively.
It should be noted that the invention is not limited to the number, shape and arrangement of the hollow patterns 1142a in the foregoing embodiments, and it is within the scope of the invention as long as the outermost outer lead portions 1142' have at least one hollow pattern 1142a respectively.
In summary, in the flip-chip on film package structure of the present invention, the at least one hollow pattern is formed on the outermost outer lead portion of the flexible circuit substrate, and the alignment pattern on the other component (e.g., the panel) located below can be viewed through the hollow pattern with the aid of the light source, so that the flip-chip on film package structure can be used as an alignment mark when the flip-chip on film package structure is bonded to the other component. In addition, because the hollow pattern is arranged on the outer pin part at the outermost side, compared with the solid alignment mark designed on the blank area between the transmission area and the pin, the hollow pattern can be far away from the transmission area, so that the damage or friction discoloration of the alignment mark caused by a mechanism driving the flexible circuit substrate to move on the machine table or the salient points on the spacing belt can be avoided, and the condition that the thin film flip chip packaging structure and other components cannot be aligned accurately due to the damage and discoloration of the alignment mark can be further prevented. In other words, the hollow pattern on the flexible circuit substrate for use as the alignment mark can have better alignment accuracy, so as to increase the bonding yield between the COF package structure and other components.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (11)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW109114581A TWI760737B (en) | 2020-04-30 | 2020-04-30 | Flexible circuit substrate and chip on film package structure |
| TW109114581 | 2020-04-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113594126A true CN113594126A (en) | 2021-11-02 |
| CN113594126B CN113594126B (en) | 2024-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010553325.8A Active CN113594126B (en) | 2020-04-30 | 2020-06-17 | Flexible circuit substrate and chip-on-film packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113594126B (en) |
| TW (1) | TWI760737B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI841230B (en) * | 2023-02-09 | 2024-05-01 | 南茂科技股份有限公司 | Flexible circuit board and chip on film package structure |
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| US20090162607A1 (en) * | 2007-12-21 | 2009-06-25 | Sang Gon Lee | Flexible film and display device comprising the same |
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| WO2019088563A1 (en) * | 2017-11-02 | 2019-05-09 | 엘지이노텍 주식회사 | Flexible circuit board and chip package comprising same |
| CN110277363A (en) * | 2018-03-16 | 2019-09-24 | 南茂科技股份有限公司 | Semiconductor Package Structure |
| US20210045229A1 (en) * | 2017-05-15 | 2021-02-11 | Lg Innotek Co., Ltd. | Flexible circuit board for all-in-one chip on film, chip package including same, and electronic device including same |
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2020
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- 2020-06-17 CN CN202010553325.8A patent/CN113594126B/en active Active
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|---|---|---|---|---|
| KR20020004866A (en) * | 2000-07-05 | 2002-01-16 | 마찌다 가쯔히꼬 | Flexible printed circuit board, integrated circuit chip mounting flexible printed circuit board, display apparatus incorporating, integrated circuit chip mounted structure, and bonding method of integrated circuit chip mounting flexible printed circuit board |
| TW200737377A (en) * | 2006-03-24 | 2007-10-01 | Chipmos Technologies Inc | Inner lead bonding tape and tape carrier package utilizing the tape |
| CN101123239A (en) * | 2006-08-07 | 2008-02-13 | 南茂科技股份有限公司 | Chip carrier and chip package thereof |
| US20090162607A1 (en) * | 2007-12-21 | 2009-06-25 | Sang Gon Lee | Flexible film and display device comprising the same |
| CN102890348A (en) * | 2012-10-18 | 2013-01-23 | 深圳市华星光电技术有限公司 | COF (chip on film) base band, manufacturing method of COF base band, liquid crystal display module |
| US20210045229A1 (en) * | 2017-05-15 | 2021-02-11 | Lg Innotek Co., Ltd. | Flexible circuit board for all-in-one chip on film, chip package including same, and electronic device including same |
| WO2019088563A1 (en) * | 2017-11-02 | 2019-05-09 | 엘지이노텍 주식회사 | Flexible circuit board and chip package comprising same |
| US20200243452A1 (en) * | 2017-11-02 | 2020-07-30 | Lg Innotek Co., Ltd. | Flexible circuit board and chip package including same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI841230B (en) * | 2023-02-09 | 2024-05-01 | 南茂科技股份有限公司 | Flexible circuit board and chip on film package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI760737B (en) | 2022-04-11 |
| TW202143431A (en) | 2021-11-16 |
| CN113594126B (en) | 2024-11-26 |
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