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CN1949487A - Flip-Chip-on-Film package structure that prevents sealing material from overflowing - Google Patents

Flip-Chip-on-Film package structure that prevents sealing material from overflowing Download PDF

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Publication number
CN1949487A
CN1949487A CN 200510108619 CN200510108619A CN1949487A CN 1949487 A CN1949487 A CN 1949487A CN 200510108619 CN200510108619 CN 200510108619 CN 200510108619 A CN200510108619 A CN 200510108619A CN 1949487 A CN1949487 A CN 1949487A
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Prior art keywords
flip
chip
film
encapsulating structure
encapsulant
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Pending
Application number
CN 200510108619
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Chinese (zh)
Inventor
黄敏娥
刘光华
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Chipmos Technologies Inc
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Chipmos Technologies Bermuda Ltd
Chipmos Technologies Inc
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Application filed by Chipmos Technologies Bermuda Ltd, Chipmos Technologies Inc filed Critical Chipmos Technologies Bermuda Ltd
Priority to CN 200510108619 priority Critical patent/CN1949487A/en
Publication of CN1949487A publication Critical patent/CN1949487A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a flip-chip on film packaging structure which comprises a substrate, a flip chip, a plurality of bumps, a first sealing material and a retaining wall. The substrate has an upper surface and a plurality of leads formed on the upper surface. The flip chip is provided with an active surface and a plurality of welding pads formed on the active surface, wherein each welding pad corresponds to one pin of the pins. Each bump engages one of the pads and a pin corresponding to the pad. A first sealing material is coated to cover the periphery of the flip chip. A dam is formed on the upper surface of the substrate and surrounds the flip chip to prevent overflow of the first sealing material.

Description

可防止密封材料溢流的膜上倒装片封装结构Flip-Chip-on-Film package structure that prevents sealing material from overflowing

技术领域technical field

本发明涉及一种膜上倒装片封装结构(Flip-chip-on-film packagestructure)，特别是涉及一种可防止密封材料溢流的膜上倒装片封装结构。The invention relates to a Flip-chip-on-film package structure, in particular to a Flip-chip package structure on a film which can prevent sealing material from overflowing.

背景技术Background technique

请参阅图1，图1为现有技术的芯片封装结构10的示意图。现有技术的芯片封装结构10包含基板12、芯片14以及点涂胶体16。基板12具有上表面120以及形成于上表面120上的引线层122。芯片14具有有源面(Activesurface)140。至少一个凸块(Bump)18形成于芯片14的有源面140上。当芯片14被固定至基板12时，这些凸块18与基板12的引线层122形成电连接。涂布点涂胶体16以密封这些凸块18。Please refer to FIG. 1 , which is a schematic diagram of a chip packaging structure 10 in the prior art. The prior art chip packaging structure 10 includes a substrate 12 , a chip 14 and a dispensing glue 16 . The substrate 12 has an upper surface 120 and a lead layer 122 formed on the upper surface 120 . Chip 14 has an active surface (active surface) 140 . At least one bump (Bump) 18 is formed on the active surface 140 of the chip 14 . These bumps 18 form electrical connections with the lead layer 122 of the substrate 12 when the chip 14 is fixed to the substrate 12 . Dispensing glue 16 is applied to seal these bumps 18 .

随着集成电路往微小化的发展，产品面积因微小化关系必须缩小以制造出最小的成品面积，因此，必须控制涂胶的溢流。此外，基板12上通常会设置多个芯片14，以提高芯片封装结构10的效能。然而，当芯片14的数目增加时，芯片与芯片间的距离便会缩减，使得涂布点涂胶体16时，常会发生溢流，而污染邻近的芯片。With the development of miniaturization of integrated circuits, the product area must be reduced due to miniaturization to produce the smallest finished product area. Therefore, the overflow of glue must be controlled. In addition, usually a plurality of chips 14 are disposed on the substrate 12 to improve the performance of the chip packaging structure 10 . However, when the number of chips 14 increases, the distance between the chips will decrease, so that when the dispensing glue 16 is applied, overflow will often occur and contaminate adjacent chips.

因此，本发明的主要目的在于提供一种膜上倒装片封装结构，以解决上述问题。Therefore, the main purpose of the present invention is to provide a flip chip on film packaging structure to solve the above problems.

发明内容Contents of the invention

本发明的一个目的在于提供一种膜上倒装片封装结构，该膜上倒装片封装结构利用一形成于基板的上表面上的挡墙(Barricade)，并且围绕倒装芯片(Flip Chip)的周围，用以防止密封材料的溢流。An object of the present invention is to provide a flip-chip packaging structure on a film, which utilizes a barrier wall (Barricade) formed on the upper surface of the substrate and surrounds the flip chip (Flip Chip) around to prevent overflow of sealing material.

根据一个优选具体实施例，本发明的膜上倒装片封装结构包含基板、倒装片芯片、多个凸块、一第一密封材料以及一挡墙。基板具有一上表面以及多条形成于上表面上的引脚(Lead)。倒装片芯片具有一有源面以及形成于有源面上的多个焊垫(Pad)，其中，这些焊垫中的每一个焊垫对应这些引脚中的一条引脚。每一个凸块接合这些焊垫中的一个焊垫以及对应该焊垫的引脚。涂布第一密封材料以覆盖倒装芯片的周围。挡墙形成于基板的上表面上，并且围绕倒装片芯片的周围，用以防止第一密封材料的溢流。According to a preferred embodiment, the flip-chip package structure of the present invention includes a substrate, a flip-chip chip, a plurality of bumps, a first sealing material, and a barrier wall. The substrate has an upper surface and a plurality of leads formed on the upper surface. The flip-chip chip has an active surface and a plurality of pads formed on the active surface, wherein each of the pads corresponds to one of the pins. Each bump engages one of the pads and a lead corresponding to the pad. A first encapsulant is applied to cover the periphery of the flip chip. The barrier wall is formed on the upper surface of the substrate and surrounds the flip-chip chip to prevent overflow of the first sealing material.

因此，通过本发明的膜上倒装片封装结构，涂布密封材料以覆盖倒装芯片周围，因围绕倒装芯片周围的挡墙的限制，而不会有密封材料溢流的情况发生。Therefore, with the Flip Chip on Film packaging structure of the present invention, the encapsulant is coated to cover the periphery of the flip chip, and the overflow of the encapsulant will not occur due to the limitation of the barrier surrounding the flip chip.

关于本发明的优点与精神可以通过以下的发明详述及附图得到进一步的了解。The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

附图说明Description of drawings

图1为现有技术的芯片封装结构的示意图。FIG. 1 is a schematic diagram of a chip packaging structure in the prior art.

图2为根据本发明第一优选具体实施例的膜上倒装片封装结构的示意图。FIG. 2 is a schematic diagram of a flip-chip-on-film packaging structure according to a first preferred embodiment of the present invention.

图3为图2中膜上倒装片封装结构的上视图。FIG. 3 is a top view of the flip chip package structure in FIG. 2 .

附图标记说明Explanation of reference signs

10：芯片封装结构              12、32：基板10: Chip package structure 12, 32: Substrate

120、320：上表面              122：引线层120, 320: Upper surface 122: Lead layer

14：芯片                      140、340：有源面14: chip 140, 340: active surface

16：点涂胶体                  18、36：凸块16: Colloid dispensing 18, 36: Bump

30：膜上倒装片封装结构        322：引脚30: Flip chip package structure on film 322: Pin

34：倒装芯片                  38：第一密封材料34: Flip chip 38: First sealing material

40：挡墙40: retaining wall

具体实施方式Detailed ways

请参阅图2以及图3，图2为根据本发明第一优选具体实施例的膜上倒装片封装结构30的示意图。图3为图2中膜上倒装片封装结构30的顶视图。膜上倒装片封装结构30包含基板32、倒装芯片34、多个凸块36、第一密封材料38以及挡墙40。基板32具有上表面320以及多条形成于上表面320上的引脚322。在此实施例中，基板32可为柔性电路板(Flexible circuit board)。倒装芯片34具有有源面340以及形成于有源面340上的多个焊垫(未显示于图中)，其中，这些焊垫中的每一个焊垫对应这些引脚322中的一条引脚322。每一个凸块36形成于倒装芯片34的有源面340上或形成于这些引脚322上，用以接合这些焊垫中的一个焊垫以及对应该焊垫的引脚322。在此实施例中，这些凸块36以原子间键合(Interatomic bonding)方式与基板32上的这些引脚322接合。在另一优选具体实施例中，这些凸块36通过一共晶接合工艺(Eutectic bonding process)或一超声波热结合工艺(Ultrasonic-thermobonding process)与基板32上的这些引脚322接合。这些凸块36可为金凸块(Gold bump)或其它类似元件。Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a schematic diagram of a flip-chip-on-film packaging structure 30 according to a first preferred embodiment of the present invention. FIG. 3 is a top view of the flip-chip package structure 30 in FIG. 2 . The Flip Chip on Film packaging structure 30 includes a substrate 32 , a flip chip 34 , a plurality of bumps 36 , a first encapsulant 38 and a barrier wall 40 . The substrate 32 has an upper surface 320 and a plurality of pins 322 formed on the upper surface 320 . In this embodiment, the substrate 32 can be a flexible circuit board (Flexible circuit board). The flip chip 34 has an active surface 340 and a plurality of bonding pads (not shown) formed on the active surface 340, wherein each bonding pad in these bonding pads corresponds to one of the pins 322. 322 feet. Each bump 36 is formed on the active surface 340 of the flip chip 34 or on the leads 322 for bonding to one of the pads and the lead 322 corresponding to the pad. In this embodiment, the bumps 36 are bonded to the pins 322 on the substrate 32 by interatomic bonding. In another preferred embodiment, the bumps 36 are bonded to the pins 322 on the substrate 32 through an eutectic bonding process or an ultrasonic-thermobonding process. The bumps 36 can be gold bumps or other similar elements.

如图2所示，涂布第一密封材料38以覆盖倒装芯片34的周围以及这些凸块36。在上述的实施例中，第一密封材料38可为底部填充材料(Under-filling material)，并且第一密封材料38具有防水性。As shown in FIG. 2 , a first encapsulant 38 is applied to cover the periphery of the flip chip 34 and these bumps 36 . In the above-mentioned embodiment, the first sealing material 38 may be an under-filling material, and the first sealing material 38 is waterproof.

如图2以及图3所示，挡墙40形成于基板32的上表面320上，并且围绕倒装芯片34的周围，用以防止第一密封材料38的溢流。在此实施例中，挡墙40由选自树脂(Resin)材料、非导电胶(Non-conductive paste，NCP)、底部填充胶(Under-filling material)以及一焊阻材料(Solder resistance material)的一种材料形成。在此实施例中，挡墙40通过一印刷工艺形成于基板32的上表面320上。藉此，涂布第一密封材料38以覆盖倒装片芯片34周围的，因围绕倒装片芯片34周围的挡墙40的限制，而不会有第一密封材料38溢流的情况发生。As shown in FIGS. 2 and 3 , the barrier wall 40 is formed on the upper surface 320 of the substrate 32 and surrounds the flip chip 34 to prevent the first sealing material 38 from overflowing. In this embodiment, the retaining wall 40 is made of a resin (Resin) material, a non-conductive paste (Non-conductive paste, NCP), an underfill glue (Under-filling material) and a solder resistance material (Solder resistance material). A material is formed. In this embodiment, the retaining wall 40 is formed on the upper surface 320 of the substrate 32 through a printing process. In this way, the first sealing material 38 is coated to cover the surrounding of the flip-chip chip 34 , and the overflow of the first sealing material 38 does not occur due to the limitation of the barrier wall 40 surrounding the flip-chip chip 34 .

在另一优选具体实施例中，本发明的膜上倒装片封装结构30可进一步包含第二密封材料(未显示于图中)。第二密封材料涂布于倒装芯片34与基板32之间，致使倒装芯片34固着于基板32上。第二密封材料可为热固性(Thermosetting)材料，并且当热固时具收缩性，或者，第二密封材料由选自非导电胶、各向异性导电胶(Anisotropic conductive paste，ACP)以及一各向异性导电膜(Anisotropic conductive film，ACF)的一种材料形成。In another preferred embodiment, the flip-chip package structure 30 of the present invention may further include a second sealing material (not shown in the figure). The second sealing material is coated between the flip chip 34 and the substrate 32 , so that the flip chip 34 is fixed on the substrate 32 . The second sealing material can be a thermosetting (Thermosetting) material, and when heat is cured, it is shrinkable, or the second sealing material is selected from non-conductive adhesive, anisotropic conductive paste (Anisotropic conductive paste, ACP) and an anisotropic conductive paste. It is formed by a material of Anisotropic conductive film (ACF).

与现有技术比较，本发明的膜上倒装片封装结构利用一挡墙形成于基板的上表面上，并且围绕倒装芯片的周围，用以防止密封材料的溢流，以控制封装结构成品的尺寸，并且避免相邻的倒装芯片遭受密封材料的污染。Compared with the prior art, the film-on-flip-chip packaging structure of the present invention utilizes a retaining wall formed on the upper surface of the substrate and surrounds the flip-chip to prevent the overflow of the sealing material and to control the finished product of the packaging structure. size, and to avoid contamination of adjacent flip-chips by encapsulation materials.

通过以上优选具体实施例的详述，希望能更加清楚描述本发明的特征与精神，而并非以上述所公开的优选具体实施例来对本发明的范畴加以限制。相反地，其目的是希望能涵盖各种改变及具等同性的安排于本发明的权利要求书的范畴内。Through the detailed description of the preferred specific embodiments above, it is hoped that the features and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred specific embodiments disclosed above. On the contrary, the intention is to cover various modifications and equivalent arrangements within the scope of the appended claims of the present invention.

Claims (13)

1, flip-chip encapsulating structure on a kind of film comprises:
Substrate, described substrate have a upper surface and many pins that are formed on the described upper surface;
Flip-chip, described flip-chip have active face and are formed at a plurality of weld pads on the described active face, a pin in the corresponding described pin of each weld pad in the described weld pad;
A plurality of projections, a weld pad in the described weld pad of each bump bond in the described projection and the pin of corresponding described weld pad;
First encapsulant, be coated with described first encapsulant with cover described flip-chip around; And
Barricade, described barricade are formed on the described upper surface of described substrate and around described flip-chip, in order to prevent the overflow of described first encapsulant.
2, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described barricade is formed by a kind of material that is selected from resin material, non-conductive adhesive, bottom filling material and weldering resistance material.
3, flip-chip encapsulating structure on the film as claimed in claim 1, wherein said barricade is formed on the upper surface of described substrate by a typography.
4, flip-chip encapsulating structure on the film as claimed in claim 1 further comprises:
Second encapsulant, described second encapsulant is coated between described flip-chip and the described substrate, causes described flip-chip to be bonded on the described substrate.
5, flip-chip encapsulating structure on the film as claimed in claim 4, wherein, described second encapsulant is a kind of thermosets.
6, flip-chip encapsulating structure on the film as claimed in claim 4, wherein said second encapsulant is selected from non-conductive adhesive, anisotropy conductiving glue and anisotropic conductive film.
7, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described first encapsulant is a kind of underfill.
8, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described first encapsulant has water proofing property.
9, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described projection engages with described pin on the described substrate in the interatomic bond mode of closing.
10, flip-chip encapsulating structure on the film as claimed in claim 9, wherein, described projection engages with described pin on the described substrate by an eutectic joint technology or ultrasonic heat combined process.
11, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described projection is formed on the active face of described flip-chip or is formed on the described pin.
12, flip-chip encapsulating structure on the film as claimed in claim 1, wherein, described substrate is a kind of flexible PCB.
13, flip-chip encapsulating structure on the film as claimed in claim 1 wherein, is coated with described first encapsulant to cover described projection.
CN 200510108619 2005-10-10 2005-10-10 Flip-Chip-on-Film package structure that prevents sealing material from overflowing Pending CN1949487A (en)

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CN109729746A (en) * 2016-09-01 2019-05-07 奥斯兰姆奥普托半导体股份有限两合公司 Device with carrier and optoelectronic components
CN112638025A (en) * 2019-10-08 2021-04-09 南茂科技股份有限公司 Flexible circuit substrate and chip-on-film package structure
TWI867893B (en) * 2023-12-13 2024-12-21 南茂科技股份有限公司 Chip on film package

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CN101335253B (en) * 2007-06-27 2012-06-13 新光电气工业株式会社 Semiconductor package and semiconductor device using the same
CN103098190A (en) * 2010-09-09 2013-05-08 超威半导体公司 Semiconductor chip device with underfill
CN102254837A (en) * 2011-04-29 2011-11-23 永道无线射频标签(扬州)有限公司 Packaging process of electronic tag inversely stuck sheet packaging production line
CN102637612A (en) * 2012-05-03 2012-08-15 福建华映显示科技有限公司 Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip
CN102637612B (en) * 2012-05-03 2014-07-30 福建华映显示科技有限公司 Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip
CN103985807B (en) * 2013-02-07 2016-12-28 深圳大道半导体有限公司 Inorganic substrate and manufacture method thereof
CN103985807A (en) * 2013-02-07 2014-08-13 罗容 Inorganic substrate and manufacturing method thereof
CN104733402A (en) * 2013-12-19 2015-06-24 矽品精密工业股份有限公司 Semiconductor package structure and method for fabricating the same
CN109729746A (en) * 2016-09-01 2019-05-07 奥斯兰姆奥普托半导体股份有限两合公司 Device with carrier and optoelectronic components
US10629578B2 (en) 2016-09-01 2020-04-21 Osram Oled Gmbh Arrangement having a carrier and an optoelectronic component
CN109729746B (en) * 2016-09-01 2020-07-10 奥斯兰姆奥普托半导体股份有限两合公司 Device with carrier and optoelectronic component
CN108281409A (en) * 2018-01-11 2018-07-13 苏州通富超威半导体有限公司 One kind can reduce encapsulation chip size packages substrate and the preparation method and application thereof
CN112638025A (en) * 2019-10-08 2021-04-09 南茂科技股份有限公司 Flexible circuit substrate and chip-on-film package structure
TWI867893B (en) * 2023-12-13 2024-12-21 南茂科技股份有限公司 Chip on film package

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