CN102637612A - Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip - Google Patents
Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip Download PDFInfo
- Publication number
- CN102637612A CN102637612A CN2012101340853A CN201210134085A CN102637612A CN 102637612 A CN102637612 A CN 102637612A CN 2012101340853 A CN2012101340853 A CN 2012101340853A CN 201210134085 A CN201210134085 A CN 201210134085A CN 102637612 A CN102637612 A CN 102637612A
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- bonding area
- semiconductor chip
- insulating barrier
- chip bonding
- metal wire
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 title abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 61
- 239000000853 adhesive Substances 0.000 claims abstract description 29
- 230000001070 adhesive effect Effects 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims description 59
- 239000012774 insulation material Substances 0.000 claims description 31
- 238000007731 hot pressing Methods 0.000 claims description 13
- 229910010272 inorganic material Inorganic materials 0.000 claims description 4
- 239000011147 inorganic material Substances 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 abstract 3
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000005260 corrosion Methods 0.000 description 8
- 230000007797 corrosion Effects 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000006698 induction Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a method for fixedly arranging a semiconductor chip on a circuit substrate. The method comprises the following steps of: providing a circuit substrate, wherein the circuit substrate sequentially comprises a base material, at least one metal wire and an insulating layer, wherein the base material is provided with a chip splicing region; forming an organic insulating material on the insulating layer outside the chip splicing region, and then, forming an anisotropic conductive adhesive to cover the chip splicing region and a part of the organic insulating material; and finally, thermally pressing the semiconductor chip on the anisotropic conductive adhesive. The organic insulating material is formed on the insulating layer, and thus the metal wire arranged below the insulating layer is prevented from being corroded. The invention also provides a packaging structure of a semiconductor chip.
Description
Technical field
The invention relates to a kind of method and structure thereof that sets firmly semiconductor chip in circuit base plate, particularly relevant for a kind of be used for LCD set firmly method and the structure thereof of semiconductor chip in circuit base plate.
Background technology
In recent years, high before structure dress density of the characteristic demand of electronic product and high electric reliability development.For reach these demands, develop as chip on the flexible substrate (chip on film, COF) with glass top chip (chip on glass, technology COG).And the glass top chip technology extensively applies in the field of liquid crystal at present.
Generally speaking, the step of glass top chip processing procedure is following.At first, cover one deck anisotropic conducting rubber on joint sheet and insulating barrier on every side thereof.Then, hot pressing semiconductor chip on anisotropic conducting rubber makes can see through anisotropic conducting rubber between projection and the joint sheet of semiconductor chip and electrically connect.Yet in hot and humid reliability test, corrosion phenomenon can take place and make metal wire break in the metal wire of insulating barrier below randomly, and then causes scrapping of panel.
Therefore, need a kind of method and structure thereof that sets firmly semiconductor chip in circuit base plate of exploitation, to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of method that sets firmly semiconductor chip in circuit base plate, to avoid metal wire generation corrosion phenomenon in hot and humid reliability test.
According to an embodiment of the present invention, this method comprises the following step.Circuit base plate is provided, and circuit base plate comprises base material, at least one metal wire and insulating barrier.Base material has a chip bonding area.Metal wire is positioned on the base material, and it is extended in the chip bonding area outward by chip bonding area, and metal wire has a joint sheet and is positioned at chip bonding area.It is online that insulating barrier is disposed at metal, and insulating barrier has an opening and exposes joint sheet.Form the organic insulation material on the insulating barrier of chip bonding area outer rim.Form the part that anisotropic conducting rubber covers chip bonding area and organic insulation material.The hot pressing semiconductor chip makes the projection of semiconductor chip electrically connect by anisotropic conducting rubber and joint sheet on anisotropic conducting rubber.
In another embodiment, this method comprises the following step.Circuit base plate is provided, and circuit base plate comprises base material, at least one metal wire and insulating barrier.Base material has a chip bonding area.Metal wire is positioned on the base material, and it is extended in the chip bonding area outward by chip bonding area, and metal wire has a joint sheet and is positioned at chip bonding area.It is online that insulating barrier is disposed at metal, and insulating barrier has an opening and exposes joint sheet.It is online that insulating barrier is disposed at metal, and insulating barrier has an opening and exposes joint sheet.Form non-conductive adhesive on the insulating barrier of chip bonding area and chip bonding area outer rim, wherein non-conductive adhesive covers the part of metal wire.Form anisotropic conducting rubber on the insulating barrier of the non-conductive adhesive of chip bonding area and chip bonding area outer rim.The hot pressing semiconductor chip makes the projection of semiconductor chip electrically connect by anisotropic conducting rubber and joint sheet on anisotropic conducting rubber.
Another aspect of the present invention is that a kind of semiconductor chip package is being provided, and it includes base material, at least one metal wire, insulating barrier, organic insulation material, anisotropic conducting rubber and chip.Base material has a chip bonding area.Metal wire is positioned on the base material, and it is extended in the chip bonding area outward by chip bonding area, and metal wire has a joint sheet and is positioned at chip bonding area.It is online that insulating barrier is positioned at metal, and insulating barrier has an opening and exposes joint sheet.The organic insulation material is positioned on the insulating barrier of chip bonding area outer rim.Anisotropic conducting rubber covers the part of chip bonding area and organic insulation material.Semiconductor chip is positioned on the anisotropic conducting rubber of chip bonding area, and wherein the projection of semiconductor chip electrically connects by anisotropic conducting rubber and joint sheet.
Description of drawings
Fig. 1 sets firmly the flow chart of semiconductor chip in the method for circuit base plate according to an embodiment of the present invention.
Fig. 2 A is the schematic top plan view according to the circuit base plate of an embodiment of the present invention.
Fig. 2 B is the generalized section according to the circuit base plate of an embodiment of the present invention.
Fig. 3 A is the schematic top plan view according to the semiconductor chip package of an embodiment of the present invention.
Fig. 3 B, 3C set firmly the generalized section of semiconductor chip in each process stage of the method for circuit base plate according to an embodiment of the present invention.
Fig. 4 sets firmly the flow chart of semiconductor chip in the method for circuit base plate according to another execution mode of the present invention.
Fig. 5 A is the schematic top plan view according to the semiconductor chip package of another execution mode of the present invention.
Fig. 5 B is the schematic top plan view according to the semiconductor chip package of the another execution mode of the present invention.
Fig. 5 C, 5D are the generalized sections that sets firmly semiconductor chip each process stage in the method for circuit base plate according to another execution mode of the present invention.
Among the figure: 100; 400: manufacturing approach 110; 120; 130; 140; 410; 420; 430; 440: step 204; 206: metal wire 204a; 206a: joint sheet 208: insulating barrier 208a: opening 210: circuit base plate 212: chip bonding area 214: chip bonding area outer rim 220: organic insulation material 222: non-conductive adhesive 230; 230a: anisotropic conducting rubber 240: semiconductor chip 242: projection 300; 500: semiconductor chip package D1: the dimension D2 of non-conductive adhesive: the dimension W1 of anisotropic conducting rubber: the thickness W2 of insulating barrier: the thickness W3 of organic insulation material: the thickness of non-conductive adhesive
.
Specific embodiment
More detailed and complete for the narration that makes this disclosure, hereinafter has been directed against enforcement aspect of the present invention and specific embodiment has proposed illustrative description; But this is not unique form of implementing or using the specific embodiment of the invention.Following each embodiment that discloses can make up or replace under useful situation each other, also can add other embodiment in one embodiment, and need not further put down in writing or explain.
An aspect of the present invention is that a kind of method that sets firmly semiconductor chip in circuit base plate is being provided.Fig. 1 is the flow chart of method 100.Fig. 2 A is the schematic top plan view according to the circuit base plate of an embodiment of the present invention.Fig. 2 B is the generalized section according to the circuit base plate of an embodiment of the present invention, and it is the section line segment of the 2A-2A ' in Fig. 2 A.Fig. 3 A is the schematic top plan view according to the semiconductor chip package of an embodiment of the present invention.Fig. 3 B and 3C are the generalized sections of each process stage of method 100, and it is the section line segment of the 3A-3A ' in Fig. 3 A.
In step 110, circuit base plate 210 is provided, it comprises base material 202, metal wire 204,206 and insulating barrier 208, shown in Fig. 2 A and 2B.Circuit base plate 210 can be the part of thin film transistor base plate, like the part of desire encapsulation lock chip for driving.Base material 202 has at least one chip bonding area 212 and chip bonding area outer rim 214.Metal wire 204,206 is positioned on the base material 202, and it can be respectively the metal wire of outer metal wire and portion of terminal.Metal wire 204,206 is by chip bonding area 212 outer extending in the chip bonding area 212.And each metal wire 204,206 respectively has a joint sheet 204a, 206a is positioned at chip bonding area 212.Insulating barrier 208 is disposed on the metal wire 204,206, and insulating barrier 208 has opening 208a, to expose joint sheet 204a, 206a.In one embodiment, the material of insulating barrier 208 is made by inorganic material, for example is silicon nitride.
In step 120, form organic insulation material 220 on the insulating barrier 208 of chip bonding area outer rim 214, shown in Fig. 3 A and Fig. 3 B.This is for after forming anisotropic conducting rubber (step 130) and hot pressing semiconductor chip (step 140), lets 208 isolation of anisotropic conducting rubber 230 and insulating barrier, with solution metal wire etching problem.Metal wire corrosion mechanism will specify in step 130 in the known package structure.Organic insulation material 220 itself can have stickiness, as rubber or non-conductive adhesive (non-conductive film, NCF).Perhaps, have adhesion layer (not illustrating) on the surface of organic insulation material 220, for example can be insulating tape to stick together with insulating barrier 208.
In step 130, (anisotropic conductive film ACF) 230 covers chip bonding area 212 and a part of organic insulation material 220, shown in Fig. 3 A and 3B to form anisotropic conducting rubber.That is to say that organic insulation material 220 is isolated anisotropic conducting rubber 230 and insulating barrier 208, to solve the metal wire etching problem.The machine-processed inference of metal wire corrosion is following in the known package structure.When applying a voltage to metal wire, metal wire can form induction field with the conducting particles in the anisotropic conducting rubber.Induction field possibly make the insulating barrier of anisotropic conducting rubber below break.When carrying out hot and humid reliability test, aqueous vapor possibly get into from the crack and the metal wire reaction, causes the metal wire corrosion.Therefore, in this execution mode, by organic insulation material 220 isolate anisotropic conducting rubber 230 with insulating barrier 208 so that induction field lowers, and can prevent that insulating barrier 208 from breaking.In one embodiment, the thickness W2 of organic insulation material 220 is greater than the thickness W1 of insulating barrier 208.Specifically, the thickness W1 of insulating barrier 208 can be less than 1 μ m, and the thickness W2 of organic insulation material 220 can be much larger than 1 μ m.
In step 140, hot pressing semiconductor chip 240 makes projection 242 electrically connect with joint sheet 204a, 206a by anisotropic conducting rubber 230, shown in Fig. 3 A and 3C on anisotropic conducting rubber 230.Semiconductor chip 240 can be in order to provide voltage to the metal wire 204,206 greater than 10 V.Semiconductor chip 240 for example can be the lock chip for driving.In the hot pressing processing procedure, anisotropic conducting rubber 230 flows and inserts in the opening 208a.Anisotropic conducting rubber 230 is isolated by the organic insulation material 220 and the upper surface of insulating barrier 208, and can avoid the metal wire corrosion phenomenon to take place.The conducting particles vertical electrical that in addition, can see through distortion between projection 242 and joint sheet 204a, 206a be connected.
Fig. 4 is the flow chart of method 400.Step 410 can be identical with the step 110 among Fig. 1.Below will enumerate two kinds of embodiment.Fig. 5 A and 5B illustrate the schematic top plan view of the semiconductor chip package of two embodiment respectively.Fig. 5 C and 5D illustrate the generalized section of each process stage in the method 400, and it is 5A-5A ' or the section line segment of the 5B-5B ' among Fig. 5 B in Fig. 5 A.
In step 420, form non-conductive adhesive 222 on the insulating barrier 208 of chip bonding area 212 and chip bonding area outer rim 214, shown in Fig. 5 C.And non-conductive adhesive 222 covers the part of metal wire 204,206.In one embodiment, a non-conductive adhesive 222 is in order on the insulating barrier 208 that covers a chip bonding area 212 and chip bonding area 212 outer rims, shown in Fig. 5 A.In another embodiment, a non-conductive adhesive 222 is in order to cover the part beyond several chip bonding area 212 and the chip bonding area, shown in Fig. 5 B.
In step 430, form anisotropic conducting rubber 230 on the non-conductive adhesive 222 of chip bonding area 212 tops, shown in Fig. 5 C.Be similar to the organic insulation material 220 in the method 100, non-conductive adhesive 222 can be in order to isolated insulation layer 208 and anisotropic conducting rubber 230.In one embodiment, the dimension D1 of non-conductive adhesive 222 is greater than the dimension D2 of anisotropic conducting rubber 230, shown in Fig. 5 A and 5B.In this dimension of mentioning, be meant the two-dimentional dimension that length and width constitute.This is in order to prevent when the hot pressing processing procedure, anisotropic conducting rubber 230 overflows and contacting with the upper surface of insulating barrier 208.In one embodiment, the thickness W3 of non-conductive adhesive 222 is greater than the thickness W1 of insulating barrier 208.Glue composition in the anisotropic conducting rubber 230 can be roughly the same with non-conductive adhesive 222, but do not contain conducting particles in the non-conductive adhesive 222.
In step 440, hot pressing semiconductor chip 240 makes projection 242 electrically connect with joint sheet 204a, 206a by anisotropic conducting rubber 230, shown in Fig. 5 D on anisotropic conducting rubber 230.In the hot pressing processing procedure, non-conductive adhesive 222 flows with anisotropic conducting rubber 230 and merges each other, and inserts among the opening 208a.The conducting particles vertical electrical that in addition, can see through distortion between projection 242 and joint sheet 204a, 206a be connected.
The metal wire corrosion phenomenon does not all take place through behind the hot and humid reliability test in the structure that above-mentioned two kinds of execution modes are made.Therefore the execution mode that the present invention disclosed can effectively solve known metal wire etching problem.
Another aspect of the present invention is that a kind of semiconductor chip package is being provided.Shown in Fig. 3 C and 5D, semiconductor chip package 300,500 all includes base material 202, at least one metal wire 204, insulating barrier 208, organic insulation material 220, anisotropic conducting rubber 230a and semiconductor chip 240.
Metal wire 204,206 can be respectively the metal wire of outer metal wire and portion of terminal, and it is positioned on the base material 202.Metal wire 204,206 is by chip bonding area 212 outer extending in the chip bonding area 212.And each metal wire 204,206 respectively has a joint sheet 204a, 206a is positioned at chip bonding area 212.
Insulating barrier 208 is disposed on the metal wire 204,206.And insulating barrier 208 has opening 208a, to expose joint sheet 204a, 206a.In one embodiment, the material of insulating barrier 208 is made by inorganic material, for example is silicon nitride.
Anisotropic conducting rubber 230a covers the part of chip bonding area 212 and organic insulation material 220.In semiconductor chip package 300, anisotropic conducting rubber 230a is by being formed through the hot pressing processing procedure by anisotropic conducting rubber 230.In semiconductor chip package 500, anisotropic conducting rubber 230a is by being formed through the hot pressing processing procedure by non-conductive adhesive 222 and anisotropic conducting rubber 230.
From the above, by the organic insulation material being set on insulating barrier, can effectively avoid the metal wire corrosion of insulating barrier below.Further, can reduce quantity and the reduction scrap cost that panel is scrapped.
Though the present invention discloses as above with execution mode; Right its is not in order to limiting the present invention, anyly has the knack of this art, do not breaking away from the spirit and scope of the present invention; When can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (10)
1. a method that sets firmly semiconductor chip in circuit base plate is characterized in that, comprises:
This circuit base plate is provided, and this circuit base plate comprises:
One base material has a chip bonding area;
At least one metal wire is positioned on this base material, and this metal wire is extended into outward in this chip bonding area by this chip bonding area, and this metal wire has a joint sheet and is positioned at this chip bonding area; And
One insulating barrier, it is online to be disposed at this metal, and this insulating barrier has an opening and exposes this joint sheet;
Form an organic insulation material on this insulating barrier of this chip bonding area outer rim;
Form the part that an anisotropic conducting rubber covers this chip bonding area and this organic insulation material; And
This semiconductor chip of hot pressing makes a projection of this semiconductor chip electrically connect by this anisotropic conducting rubber and this joint sheet on this anisotropic conducting rubber.
2. the method that sets firmly semiconductor chip in circuit base plate according to claim 1 is characterized in that this insulating barrier is made by an inorganic material.
3. the method that sets firmly semiconductor chip in circuit base plate according to claim 1 is characterized in that this organic insulation material is rubber, insulating tape or non-conductive adhesive.
4. the method that sets firmly semiconductor chip in circuit base plate according to claim 1 is characterized in that the thickness of this organic insulation material is greater than the thickness of this insulating barrier.
5. a method that sets firmly semiconductor chip in circuit base plate is characterized in that, comprises:
This circuit base plate is provided, and this circuit base plate comprises:
One base material has a chip bonding area;
At least one metal wire is positioned on this base material, and this metal wire is extended into outward in this chip bonding area by this chip bonding area, and this metal wire has a joint sheet and is positioned at this chip bonding area; And
One insulating barrier, it is online to be disposed at this metal, and this insulating barrier has an opening and exposes this joint sheet;
Form a non-conductive adhesive on this insulating barrier of this chip bonding area and this chip bonding area outer rim, wherein this non-conductive adhesive covers the part of this metal wire;
Form an anisotropic conducting rubber on this insulating barrier of this non-conductive adhesive of this chip bonding area and this chip bonding area outer rim; And
This semiconductor chip of hot pressing makes a projection of this semiconductor chip electrically connect by this anisotropic conducting rubber and this joint sheet on this anisotropic conducting rubber.
6. the method that sets firmly semiconductor chip in circuit base plate according to claim 5 is characterized in that the thickness of this non-conductive adhesive is greater than the thickness of this insulating barrier.
7. a semiconductor chip package is characterized in that, comprises:
One base material has a chip bonding area;
At least one metal wire is positioned on this base material, and this metal wire is extended into outward in this chip bonding area by this chip bonding area, and this metal wire has a joint sheet and is positioned at this chip bonding area;
One insulating barrier, it is online to be positioned at this metal, and this insulating barrier has an opening and exposes this joint sheet;
One organic insulation material is positioned on this insulating barrier of this chip bonding area outer rim;
One anisotropic conducting rubber covers the part of this chip bonding area and this organic insulation material; And
The semiconductor chip is positioned on this anisotropic conducting rubber of this chip bonding area, and wherein a projection of this semiconductor chip electrically connects by this anisotropic conducting rubber and this joint sheet.
8. semiconductor chip package according to claim 7 is characterized in that the thickness of this organic insulation material is greater than the thickness of this insulating barrier.
9. semiconductor chip package according to claim 7 is characterized in that this insulating barrier is made by an inorganic material.
10. semiconductor chip package according to claim 7 is characterized in that, this organic insulation material comprises rubber, insulating tape or non-conductive adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210134085.3A CN102637612B (en) | 2012-05-03 | 2012-05-03 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210134085.3A CN102637612B (en) | 2012-05-03 | 2012-05-03 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102637612A true CN102637612A (en) | 2012-08-15 |
| CN102637612B CN102637612B (en) | 2014-07-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210134085.3A Expired - Fee Related CN102637612B (en) | 2012-05-03 | 2012-05-03 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190796A (en) * | 1996-10-03 | 1998-08-19 | 国际商业机器公司 | Inorganic package layer for sealing organic layer and making method thereof |
| CN1949487A (en) * | 2005-10-10 | 2007-04-18 | 南茂科技股份有限公司 | Flip-Chip-on-Film package structure that prevents sealing material from overflowing |
| CN101136385A (en) * | 2006-08-29 | 2008-03-05 | 欣兴电子股份有限公司 | Embedded chip packaging process and circuit substrate with embedded chip |
-
2012
- 2012-05-03 CN CN201210134085.3A patent/CN102637612B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1190796A (en) * | 1996-10-03 | 1998-08-19 | 国际商业机器公司 | Inorganic package layer for sealing organic layer and making method thereof |
| CN1949487A (en) * | 2005-10-10 | 2007-04-18 | 南茂科技股份有限公司 | Flip-Chip-on-Film package structure that prevents sealing material from overflowing |
| CN101136385A (en) * | 2006-08-29 | 2008-03-05 | 欣兴电子股份有限公司 | Embedded chip packaging process and circuit substrate with embedded chip |
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| Publication number | Publication date |
|---|---|
| CN102637612B (en) | 2014-07-30 |
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Effective date of registration: 20170807 Address after: 1#, building third, fourth, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: 350015, Xingye Road, Mawei Science Park, Fujian, Fuzhou 1, China Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
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