CN101231983A - Thin film chip-on-package substrate - Google Patents

Abstract

A thin film chip package substrate mainly includes a flexible dielectric layer, a plurality of pins and at least one alignment mark. The pins are arranged on the flexible dielectric layer, wherein the inner ends of the pins extend into a chip coverage area of the flexible dielectric layer. The alignment mark is arranged on the flexible dielectric layer and is located in the chip coverage area. This avoids occupying the pin setting area of the substrate and solves the problem that the alignment mark may be shielded by a fixture during alignment.

Description

Thin film chip-on-package substrate

technical field

The invention relates to a chip-on-film packaging substrate (COF substrate), in particular to a chip-on-film packaging substrate that facilitates chip bonding and alignment.

Background technique

In the current chip-on-film packaging structure, the distance between the bumps of the chip and the pins of the film substrate must be the same and smaller and smaller, even within 30 microns, so the allowable alignment error is getting smaller and smaller. more stringent. Therefore, the alignment technology of chip bonding needs to be improved, otherwise there will be problems of bridging short circuit and signal connection failure. However, as the pitch of the pins of the thin film substrate becomes smaller, that is, the number of pins increases, the requirement for an area available for pin configuration on the substrate is greater, which relatively limits the setting position of the alignment mark.

As shown in FIG. 1 , a conventional thin film chip-on-chip packaging substrate 100 mainly includes a flexible dielectric layer 110 , a plurality of pins 120 and at least one pair of alignment marks 130 . The flexible dielectric layer 110 has a chip coverage area 111 for a chip 11 to be disposed (as shown in FIG. 2 ). The pins 120 are disposed on the flexible dielectric layer 110 . The alignment mark 130 is disposed on the flexible dielectric layer 110 . The substrate 100 further includes a solder resist layer 140 formed on the flexible dielectric layer 110 and partially covering the pins 120 . An opening 141 of the solder resist layer 140 is slightly larger than the chip coverage area 111 to expose the inner ends 121 of the pins 120 for bonding to a plurality of bumps 13 of a chip 11 . It is known that the alignment mark 130 is located outside the opening 141 of the solder resist layer 140 or is disposed in a narrow area between the opening 141 of the solder resist layer 140 and the chip coverage area 111 . When the density of the pin arrangement is increased, the pin arrangement area of the substrate 100 will be affected, and the alignment mark 130 may be covered by the jig during the alignment of the substrate before wafer bonding.

It can be seen that the structure and use of the existing thin film chip-on-chip packaging substrate obviously still have inconveniences and defects, and further improvement is urgently needed. In order to solve the above-mentioned problems, the relevant manufacturers have tried their best to find a solution, but for a long time no suitable design has been developed, and the general products have no suitable structure to solve the above-mentioned problems. This is obviously related. The problem that the industry is eager to solve. Therefore, how to create a thin film chip-on-chip packaging substrate with a new structure has become a goal that needs to be improved in the current industry.

In view of the defects of the above-mentioned existing film-on-chip packaging substrates, the inventors actively researched and innovated based on years of rich practical experience and professional knowledge engaged in the design and manufacture of such products, and combined with the application of academic theories, in order to create a new The film-on-chip package substrate with the structure can improve the general existing film-on-chip package substrate and make it more practical. Through continuous research, design, and after repeated trial samples and improvements, the present invention with practical value is finally created.

Contents of the invention

The main purpose of the present invention is to provide a thin film chip-on-chip packaging substrate, which changes the position of the alignment mark to avoid occupying the pin setting area and solves the problem that the alignment mark may be covered by the jig during alignment.

Another object of the present invention is to provide a chip-on-film packaging substrate for improving the fixing force of the alignment mark.

The purpose of the present invention and the solution to its technical problems are mainly achieved by adopting the following technical solutions. According to the present invention, a chip-on-film package substrate includes a flexible dielectric layer, a plurality of pins and at least one pair of alignment marks. The flexible dielectric layer has a chip footprint area. The pins are disposed on the flexible dielectric layer, and the inner ends of the pins further extend into the chip footprint. The alignment mark is disposed on the flexible dielectric layer and located in the wafer coverage area. A chip-on-film packaging structure using the substrate is also disclosed.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the foregoing thin film chip-on-chip package substrate, the alignment mark can be directly attached to the flexible dielectric layer.

In the foregoing thin film chip-on-chip package substrate, the alignment mark and the leads may be made of the same metal material.

In the foregoing chip-on-chip packaging substrate, the shape of the alignment mark can be selected from one of cross, square, T-shape and L-shape.

In the aforementioned film-on-chip packaging substrate, a solder resist layer may be further included, which is formed on the flexible dielectric layer and partially covers the leads, and the solder resist layer has an opening corresponding to the Chip footprint.

In the aforementioned thin film chip-on-chip package substrate, the alignment mark extends a dummy pin, one end of which extends beyond the opening of the solder resist layer and is covered by the solder resist layer.

With the above technical solutions, the thin film chip-on-chip package substrate of the present invention has at least the following advantages:

1. Change the configuration position of the alignment mark to avoid occupying the pin setting area and solve the problem that the alignment mark may be covered by the fixture during alignment.

2. Improve the fixing force of the alignment mark.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

Figure 1: A schematic top view of an existing thin film chip-on-chip packaging substrate.

FIG. 2 : a schematic partial cross-sectional view of a conventional thin film chip-on-chip packaging structure using the substrate.

FIG. 3 is a schematic top view of a chip-on-film package substrate according to the first embodiment of the present invention.

FIG. 4 is a schematic partial cross-sectional view of a chip-on-film packaging structure using the substrate according to the first embodiment of the present invention.

5A and 5B : according to the first embodiment of the present invention, schematic diagrams illustrating that the shape of the alignment mark in the thin film chip-on-chip packaging substrate can be changed equivalently.

FIG. 6 is a schematic top view of another chip-on-film package substrate according to the second embodiment of the present invention.

FIG. 7 is a schematic partial cross-sectional view of a chip-on-film packaging structure using the substrate according to the second embodiment of the present invention.

11: Wafer 12: Encapsulant 13: Bump

21: Wafer 22: Encapsulant 23: Bump

31: Wafer 32: Encapsulant 33: Bump

100: Thin film chip-on-chip package substrate

110: Flexible dielectric layer 111: Die footprint

120: pin 121: inner end

130: Alignment mark 140: Solder mask 141: Hole opening

200: Thin film chip-on-chip package substrate

210: Flexible dielectric layer 211: Die footprint

220: pin 221: inner end

230: Alignment mark 230A: Alignment mark 230B: Alignment mark

240: Solder mask 241: Opening

300: Thin film chip-on-chip package substrate

310: Flexible dielectric layer 311: Die footprint

320: pin 321: inner end

330: Alignment mark 331: Dummy pin

340: Solder mask 341: Opening

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation, structure, characteristics and features of the thin film chip-on-chip packaging substrate proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. Efficacy, detailed as follows.

In the first specific embodiment of the present invention, a chip-on-film packaging substrate is disclosed, as shown in FIG. 3 and can be referred to FIG. pins 220 and at least one pair of bit marks 230. The flexible dielectric layer 210 has a chip footprint 211 . Wherein, the size of the chip footprint 211 substantially corresponds to the size of a chip 21 (as shown in FIG. 4 ). Usually, the flexible dielectric layer 210 is a polyimide layer (PI), which has good flexibility.

The pins 220 are disposed on the flexible dielectric layer 210 , wherein the inner ends 221 of the pins 220 further extend into the chip coverage area 211 , and are exposed. Usually, the pins 220 are made of copper, and the inner end 221 and the outer end of the pins 220 are exposed and plated with a welding layer (not shown), such as a tin layer.

The alignment mark 230 is disposed on the flexible dielectric layer 210 and located in the wafer coverage area 211 , for example, may be located in a corner of the wafer coverage area 211 . Generally speaking, the alignment mark 230 and the pins 220 can be made of the same metal material, so as to be in the same layer structure as the pins 220, so as to facilitate manufacturing and accurately serve as an alignment reference for the pins 220 point. The alignment mark 230 can be directly attached to the flexible dielectric layer 210 . Usually, the alignment mark 230 only needs to have one or more corner shapes of about 90°, for example, the shape can be selected from one of cross, square, T-shape and L-shape. In this embodiment, the alignment mark 230 is in the shape of a cross.

The substrate 200 may further include a solder resist layer 240 formed on the flexible dielectric layer 210 and partially covering the pins 220 . The solder resist layer 240 has an opening 241 , which is roughly rectangular, corresponding to the chip coverage area 211 , to expose the inner ends 221 of the pins 220 and the alignment mark 230 . Usually the opening 241 of the solder resist layer 240 is slightly larger than the chip footprint 211 .

As shown in FIG. 4, a thin film chip-on-chip package structure can be made by using the aforementioned substrate 200, which mainly includes the substrate 200, a chip 21 and an encapsulant 22, the chip 21 is arranged on the substrate 200, and the chip 21 has a plurality of bumps 23 . According to the reference coordinates of the alignment marks 230 , the bumps 23 can be accurately bonded to the inner ends 221 of the pins. The bumps 23 are then sealed with the encapsulant 22 formed by dispensing. In addition, the alignment mark 230 does not occupy the lead arrangement area of the substrate 200 and solves the problem that the existing alignment mark may be covered by the jig during alignment.

As shown in FIGS. 5A and 5B , the alignment marks 230 in the wafer coverage area 211 can be replaced by alignment marks 230A and 230B of different shapes. For example, the alignment mark 230A in FIG. 5A is square, and the alignment mark 230B in FIG. 5B is T-shaped.

According to the second embodiment of the present invention, another thin film chip-on-chip packaging substrate is disclosed. As shown in FIG. 6 and with reference to FIG. 7 , the thin film chip-on-chip packaging substrate 300 includes a flexible dielectric layer 310 , a plurality of pins 320 and at least one pair of alignment marks 330 . The flexible dielectric layer 310 has a chip footprint 311 , which refers to an area intended to be occupied by a chip.

As shown in FIGS. 6 and 7 , the pins 320 are disposed on the flexible dielectric layer 310 , and the inner ends 321 of the pins 320 further extend into the chip footprint 311 .

As shown in FIGS. 6 and 7 , the alignment mark 330 is disposed on the flexible dielectric layer 310 and located within the wafer footprint 311 . With the setting position of the alignment mark 330 , it avoids occupying the lead arrangement area of the substrate 300 and solves the problem that the existing alignment mark may be covered by the jig during alignment. In this embodiment, the alignment mark 330 is L-shaped.

In addition, the substrate 300 may further include a solder resist layer 340 formed on the flexible dielectric layer 310 and partially covering the pins 320, the solder resist layer 340 has an opening 341 corresponding to the The chip cover area 311 exposes the inner ends 321 of the pins 320 .

Preferably, the alignment mark 330 extends with a dummy pin 331, one end of which extends beyond the opening 341 of the solder resist layer 340 and is covered by the solder resist layer 340, so that the alignment mark can be improved. 330 on the flexible dielectric layer 310 to prevent improper displacement or loosening.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, can use the technical content disclosed above to make some changes or modify equivalent embodiments with equivalent changes, but all the content that does not depart from the technical solution of the present invention, according to the present invention Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence still belong to the scope of the technical solutions of the present invention.

Claims (6)

1. A chip-on-film package substrate, characterized in that it comprises: a flexible dielectric layer having a die footprint; a plurality of leads disposed on the flexible dielectric layer, wherein inner ends of the leads further extend into the die footprint; and At least one pair of alignment marks are disposed on the flexible dielectric layer and located within the wafer footprint. 2. The chip-on-chip package substrate according to claim 1, wherein the alignment mark is directly attached to the flexible dielectric layer. 3 . The chip-on-chip package substrate according to claim 1 , wherein the alignment mark and the lead are made of the same metal material. 4 . 4 . The chip-on-chip packaging substrate according to claim 1 , wherein the shape of the alignment mark is selected from one of a cross shape, a square shape, a T shape and an L shape. 5. The thin film chip-on-chip package substrate according to claim 1, further comprising a solder resist layer formed on the flexible dielectric layer and partially covering the pins, the solder resist layer has an opening , which corresponds to the wafer footprint. 6. The thin film chip-on-chip package substrate according to claim 5, wherein the alignment mark extends a dummy pin, one end of which extends beyond the opening of the solder resist layer and is covered by the solder resist layer covered by.

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