TWI662707B - Semiconductor power device and manufacturing method thereof - Google Patents

Abstract

A semiconductor power device includes: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas in the channel layer and adjacent to an interface between the channel layer and the barrier layer A drain electrode, a gate electrode, and a source electrode are respectively located on the barrier layer; a first region P-type semiconductor layer is located between the gate electrode and the barrier layer; and an isolation region forming layer Is located around the top of the barrier layer, and there is no two-dimensional electron gas in the channel layer below the isolation region forming layer.

Description

Semiconductor power element and manufacturing method thereof

The present invention relates to a semiconductor power device, and more particularly, to a semiconductor power device including a nitride semiconductor.

In recent years, due to the increasing demand for high-frequency and high-power products, semiconductor power devices based on gallium nitride, such as aluminum gallium nitride-gallium nitride (AlGaN / GaN), have high-speed electron mobility and can reach Very fast switching speed, component characteristics that can be operated in high frequency, high power and high temperature working environment, so it is widely used in power supply, DC / DC converter, DC / AC switching Inverters (AC / DC inverters) and industrial applications, their fields include electronic products, uninterruptible power systems, automobiles, motors, wind power, etc.

The active area of a semiconductor power device is generally defined by the area of the area through which the current flows when the device is turned on. This active area is defined in the device manufacturing process. After the active area range of each component is distinguished on the wafer, the individual components can be tested on the wafer to obtain the electrical characteristics of a single component; therefore, the isolation between the components must be ensured. In the conventional GaN semiconductor power device manufacturing process, dry etching can be used to remove part of the semiconductor layer or implement ion implantation in the semiconductor layer to create isolation regions between the components, so that there is no conduction between the components. Layer to complete independent multiple components on a single wafer.

The present application discloses a semiconductor power device including: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas in the channel layer and adjacent to the channel layer and the barrier An interface between the gate electrode; a drain electrode, a gate electrode, and a source electrode respectively on the barrier layer; a first region P-type semiconductor layer between the gate electrode and the barrier layer; and The isolation region forming layer is located around the top of the barrier layer, and the channel layer below the isolation region forming layer does not have a two-dimensional electron gas.

The present application further discloses a method for manufacturing a semiconductor power device, including: providing a substrate; forming an epitaxial stack on the substrate; the epitaxial stack includes: a channel layer; a barrier layer; and a P-type semiconductor layer ; Removing a part of the P-type semiconductor layer to form a first region P-type semiconductor layer and a second region P-type semiconductor layer, wherein the second region P-type semiconductor layer is located around the barrier layer; forming a source And a drain on the barrier layer; and a gate on the P-type semiconductor layer in the first region.

The description of the embodiment of the present invention is as shown in the drawings. The same or similar parts are marked with the same numbers in the drawings or the description.

Figures 1A and 1B illustrate a semiconductor power device 100 in an embodiment of the present application. Figure 1B is a cross-sectional view taken along line B-B 'in Figure 1A. The semiconductor power device 100 sequentially includes a substrate 10, a nucleation layer 20, a buffer structure 30, a channel layer 40, a barrier layer 50, a first conductive type compound semiconductor layer 60a in a first region, and a second The first conductive type compound semiconductor layer 60b in the region, a gate electrode G, a source electrode S, and a drain electrode D.

The material of the substrate 10 may be a semiconductor material or an oxide material. The aforementioned semiconductor material may include, for example, silicon (Si), gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), and the like. The oxide material may include sapphire, for example. In addition, when distinguished by conductivity, the substrate 10 itself may be a conductive substrate or an insulating substrate. The aforementioned conductive substrate includes a substrate such as a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate. The above-mentioned insulating substrate includes substrates such as sapphire and Silicon on insulator (SOI). In addition, the substrate 10 may be selectively doped with a substance to change its conductivity to form a conductive or non-conductive substrate. For a silicon (Si) substrate, the dopant may be boron (B) or arsenic. (As) or phosphorus (P). In this embodiment, the substrate 10 is a silicon substrate, and the thickness is about 1000-1200um. The nucleation layer 20 is located above the substrate 10 and has a thickness of about tens of nanometers or hundreds of nanometers, so as to reduce the lattice difference between the substrate 10 and the barrier layer 50. The nucleation layer 20 is, for example, a group three or five material, and includes materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The buffer structure 30 is located above the nucleation layer 20 and has a thickness of about several micrometers or tens of micrometers. The material of the buffer structure 30 can be a group of three or five materials, which is also used to reduce the lattice difference between the substrate 10 and the barrier layer 50 and reduce Grid defect. In this embodiment, the buffer structure 30 may include a single-layer structure or a multi-layer structure. When the buffer structure 30 is a multi-layer structure, it may include a super lattice multilayer or two or more layers of different interactions. Stacked. The material of the single-layer or multi-layer buffer structure 30 may include three or five semiconductor materials, such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN), and may be doped with other elements. For example, carbon (C) or iron (Fe) is included therein, and the doping concentration may be gradually changed or fixed according to the growth direction. In addition, when the buffer structure 30 is a superlattice stack, it may be composed of two layers of epitaxial layers stacked alternately with different materials, and the material may be a Group III semiconductor material, such as an aluminum nitride layer (AlN). It is formed by overlapping with an aluminum gallium nitride layer (AlGaN) or is formed by overlapping a gallium nitride layer (GaN) and an indium gallium nitride layer (InGaN).

The channel layer 40 is formed on the buffer layer 30 and has a first energy gap. The barrier layer 50 is formed on the channel layer 40 and has a second energy gap. The second energy gap is higher than the first energy gap. The lattice constant of the barrier layer 50 is smaller than that of the channel layer 40. In this embodiment, the material of the channel layer 40 and the barrier layer 50 includes aluminum indium gallium nitride (Al _x In _y Ga ( _1-xy ) N), where 0 ≦ x <1, 0 ≦ x + y ≦ 1 . In this embodiment, the aluminum content of the barrier layer 50 may be between 0.1 and 0.3. The channel layer 40 and the barrier layer 50 themselves form spontaneous polarization, and the barrier layer 50 and the channel layer 40 are different from each other due to the different lattice constants between the channel layer 40 and each layer in the epitaxial stack below. The sum of the interactions forms a piezoelectric polarization for the upper barrier layer 50. The above two polarization phenomena affect the structure of the energy bands of the two, so that the energy bands are bent, and some energy bands are below the Fermi energy , Electrons can move two-dimensionally in the energy band below the Fermi level, and two-dimensional electron gas 16 (2DEG) is generated at the heterojunction between the channel layer 40 and the barrier layer 50 (represented by dotted lines) In the figure). In this embodiment, the material of the channel layer 40 and the barrier layer 50 may be, for example, an intrinsic semiconductor that is not doped with other elements, but other elements may be doped according to the characteristics of the element. For example, elemental silicon (Si) can be doped therein, and the concentration of the two-dimensional electron gas layer is adjusted by the doped element concentration.

Above the barrier layer 50, there is a first conductive compound semiconductor layer 60, a first conductive compound semiconductor layer 60a including a first region is located in a central region of the barrier layer 50, and a first conductive region of a second region The compound semiconductor layer 60 b is located in a region around the barrier layer 50. The first conductive type compound semiconductor layers 60a and 60b of the first region and the second region are separated from each other, and the first conductive type compound semiconductor layer 60a of the first region is a closed loop pattern as viewed from above.

The material of the first conductive type compound semiconductor layer 60 includes a p-type semiconductor material. In this embodiment, the first conductive type compound semiconductor layer 60 is, for example, a p-type group III semiconductor, such as a p-type gallium nitride layer (p-GaN). ). Its role is to reduce the concentration of the two-dimensional electron gas 16 under the first conductive type compound semiconductor layer 60 or to dissipate the two-dimensional electron gas 16 below, so that the semiconductor power element is in an unconducted state when the gate is not biased. Status (normally off). The first conductive type compound semiconductor layers 60a and 60b in the first region and the second region may have the same material characteristics, such as the same thickness, material composition, first conductive type dopant, or first conductive type doping concentration. .

A gate electrode G is formed above the first conductive type compound semiconductor layer 60a in the first region, and the gate electrode G and the first conductive type compound semiconductor layer 60a in the first region have corresponding closed loop patterns. The source electrode S and the drain electrode D are located above the barrier layer 50, the source electrode S is located in the gate electrode G of the closed loop pattern, and the drain electrode D is located on a side outside the gate electrode G of the closed loop pattern. In one embodiment, the distance between the drain electrode D and the gate electrode G is greater than the distance between the gate electrode G and the source electrode S. The first conductive type compound semiconductor layer 60b located in the second region around the barrier layer 50 surrounds the gate electrode G, the source electrode S, and the drain electrode D at the same time. The material of the drain electrode D and the source electrode S may be selected from titanium (Ti) and aluminum (Al), and the material of the gate electrode G may be selected from nickel (Ni), gold (Au), tungsten (W), and nitride Titanium (TiN), tungsten nitride (TiW), platinum (Pt), molybdenum (Mo), or a combination thereof.

2 to 5B illustrate a method for manufacturing the semiconductor power device 100 disclosed in this application.

Referring to FIG. 2, the method for manufacturing a semiconductor power device includes a wafer formation step. First, the nucleation layer 20, the buffer structure 30, the channel layer 40, the barrier layer 50, and the first conductive compound semiconductor layer 60 are sequentially grown on the substrate 10. The substrate 10 is, for example, a silicon substrate with a thickness of about 1000 to 1200 um. The nucleation layer 20, the buffer structure 30, the channel layer 40, and the barrier layer 50 are epitaxially grown on the (111) surface of the substrate 10, and along the [0001] Direction growth. The epitaxy method is, for example, metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). In other embodiments, a part of the substrate 10 may be further removed to reduce the leakage path and achieve the effect of reducing leakage. For example, thinning the surface of the substrate 10 relative to the semiconductor layer such as the nucleation layer 20; or removing the substrate 10 and transposing the semiconductor layer such as the nucleation layer 20 above the substrate 10 to an insulating heat dissipation substrate; In one embodiment, after the substrate 10 is removed, the semiconductor layer having a higher epitaxial defect density can be further removed, for example, the nucleation layer 20 and the buffer structure 30 are removed, and then transposed and bonded to the insulation and heat dissipation substrate. Process.

Next, as shown in FIG. 3, the first conductive compound semiconductor layer 60 is also grown over the barrier layer 50 in an epitaxial growth manner to obtain a wafer 1.

Following the wafer formation step, the method for manufacturing a semiconductor power device includes a patterning step of a first conductive compound semiconductor layer 60. As shown in FIGS. 4A and 4B, FIG. 4B is a cross-sectional view taken along line BB ′ in FIG. 4A. The pattern of the first conductive compound semiconductor layer 60 is defined by a process such as etching, and a part of the first The conductive compound semiconductor layer 60 is used to form a first conductive compound semiconductor layer 60a in a first region and a first conductive compound semiconductor layer 60b in a second region. The first conductive compound semiconductor layer 60b in the second region is further used. A plurality of active regions A1 and A2 are defined in the wafer 1, and an element isolation region ISO is defined between the plurality of active regions A1 and A2. The current is controlled within the respective active regions, so that subsequent formation of Each semiconductor power element can operate independently without interference from each other.

In the upper view of FIG. 4A, the first conductive type compound semiconductor layer 60b in the second region surrounds and surrounds each active region A1, A2 and is located between each active region A1, A2, and is located in the middle of each active region A1, A2. Around the barrier layer 50, a reverse polarization effect is generated by using a lattice difference between the first conductive compound semiconductor layer 60b and the barrier layer 50 in the second region, and the energy band is raised above the Fermi level. The two-dimensional electron gas 16 below the area is dissipated or the concentration is reduced, thereby achieving the effect of element isolation. The first conductive type compound semiconductor layer 60a in the first region is located in each of the active regions A1 and A2, and has a closed ring type in the top view, and is separated from the first conductive type compound semiconductor layer 60b in the second region.

Following the patterning step of the first conductive compound semiconductor layer 60, the method for manufacturing a semiconductor power device includes an electrode forming step. Fig. 5B is a sectional view taken along line B-B 'in Fig. 5A. As shown in FIGS. 5B and 5B, a drain electrode D and a source electrode S are respectively formed over the barrier layer 50, and a gate electrode G is formed over the first conductive type compound semiconductor layer 60a in the first region as the An end that is electrically connected to an external electronic component or an external power source. The gate electrode G and the first conductive compound semiconductor layer 60a in the first region have corresponding closed-loop patterns in a top view, and the source electrode S is located in the gate electrode G of the closed-loop pattern. The electrode D may be located on one side of the barrier layer outside the closed loop pattern. In this embodiment, the appropriate materials of the drain electrode D and the source electrode S can be selected, and / or the drain electrode D and the source electrode S and the barrier layer 50 can be made by a process (such as thermal annealing). An ohmic contact is formed between them. Similarly, a Schottky contact or an ohmic contact can be formed between the gate electrode G and the first conductive type compound semiconductor layer 60a in the first region by selecting an appropriate material of the gate electrode G.

As shown in FIG. 5B, the semiconductor power element 100 formed according to the manufacturing method of the present application, when the gate electrode G is not biased, the channel layer 40 under the first conductive compound semiconductor layer 60a in the first region There is no two-dimensional electron gas 16 inside, so the semiconductor power element 100 is not turned on and is turned off. In addition, under the closed-loop pattern of the first conductive compound semiconductor layer 60a and the gate electrode G in the first region, the corresponding channel layer 40 does not have a two-dimensional electron gas 16, thereby forming a radon blocking region 18 to surround the source. The electrode S prevents the current from passing from the drain electrode D to the source electrode S and allows the device to be in a closed state.

When a bias voltage is applied to the gate electrode G, as shown in FIG. 6, a two-dimensional electron gas 16 is formed in the channel layer below the first conductive compound semiconductor layer 60 a in the first region in each semiconductor power element 100. Therefore, each semiconductor power element 100 is turned on. And because the first conductive compound semiconductor layer 60a in the first region and the first conductive compound semiconductor layer 60b in the second region are separated from each other, that is, the first conductive compound semiconductor layer 60a in the first region is isolated from the device. The area ISO has a pitch. Therefore, the two-dimensional electron gas 16 in a single semiconductor power device 100 is not affected by the surrounding device isolation area ISO, and current can flow from the drain electrode D to the source electrode S; The two-dimensional electron gas 16 is not formed in the channel layer 40 of the ISO (that is, the first conductive type compound semiconductor layer 60b in the second region), so that the elements can be electrically isolated from each other.

In an embodiment of the present application, the first conductive type compound semiconductor layer 60a in the first region below the gate electrode G and the first conductive type compound semiconductor layer 60b in the second region are formed in a manner that the first conductive layer is formed. The first conductive compound semiconductor layer 60 is formed after etching the first conductive compound semiconductor layer 60 at the same time. Therefore, the first conductive compound semiconductor layer 60a in the first region and the first conductive compound semiconductor layer 60b in the second region may be formed. It has the same characteristics, such as the same thickness, material composition, first conductivity type dopant, or first conductivity type doping concentration. In addition, compared with the conventional technology using dry etching or ion implantation in the semiconductor layer to form an element isolation region, the semiconductor power device and its manufacturing method disclosed in this application are more simplified in manufacturing process, and also have Lower production costs.

In another embodiment of the present application, after the semiconductor power element manufacturing method is completed, each semiconductor power element 100 may be further divided along the first conductive compound semiconductor layer 60b in the second region, for example, using a wheel cutter Dicing or laser cutting to form the individual semiconductor power device 100 as shown in FIGS. 1A and 1B. In the separated semiconductor power device 100, there is no two-dimensional electron gas under the first conductive type compound semiconductor layer 60b in the second region, and it has the function of reducing the leakage current path. In an embodiment, the width of the first conductive compound semiconductor layer 60b in the second region before cutting is larger than that of the first conductive compound semiconductor layer 60a in the first region; The width should be wide enough so that after the first conductive type compound semiconductor layer 60b in part of the second region is removed during the dicing process, enough first conductive type compound semiconductor layer 60b in the second region is left on the semiconductor power device. The above function.

In another embodiment of the present application, before forming the drain electrode D, the source electrode S, and the gate electrode G, a dielectric layer 32 may be formed on the upper surface of the barrier layer 50 as shown in FIG. 7. on. Part of the dielectric layer 32 is located below the gate electrode G and between the gate electrode G and the barrier layer 50, which can further reduce the surface leakage current, increase the operating bias range of the gate electrode G, and improve the reliability of the device. degree. The dielectric layer 32 may be an oxide or a nitride, for example, an oxide such as silicon oxide or aluminum oxide, or a nitride such as silicon nitride or gallium nitride.

In another embodiment of the present application, after forming the drain electrode D, the source electrode S, and the gate electrode G, a protective layer (not shown) may be further formed to cover the dielectric layer 32 and the drain electrode. D. The surfaces of the source electrode S and the gate electrode G to prevent the electrical properties of the channel layer 40 from being affected. In this embodiment, the protective layer may be an oxide or a nitride, such as an oxide such as silicon oxide or aluminum oxide, or a nitride such as silicon nitride or gallium nitride. Then, the protective layer is etched to expose part of the drain electrode D, the source electrode S, and the gate electrode G, that is, the drain electrode D, the source electrode S, and the gate electrode G may have a part of the surface not covered by the protective layer. Covering to increase the convenience of electrical connection with the outside world.

Figures 8A to 8D show a semiconductor power device 200 in another embodiment of the present application. Figure 8B is a cross-sectional view taken along line BB 'in Figure 8A, and Figure 8C is taken along C- in Figure 8A. A cross-sectional view of the line C ′, and FIG. 8D is a cross-sectional view of the line DD ′ in FIG. 8A.

The semiconductor power element 200 is similar to the semiconductor power element 100, and includes a substrate 10, a nucleation layer 20, a buffer structure 30, a channel layer 40, and a barrier layer 50, a first conductive compound semiconductor layer 60a, and a second region in this order. The first conductive type compound semiconductor layer 60b in the region, the gate electrode G, the source electrode S, and the drain electrode D. Above the barrier layer 50, a first conductive compound semiconductor layer 60 a having a first region is located in a central region of the barrier layer 50, and a first conductive compound semiconductor layer 60 b of a second region is located around the barrier layer 50. Regions, and the first conductive compound semiconductor layers 60a and 60b of the first region and the second region are separated from each other. The materials, formation methods, and functions of the first conductive type compound semiconductor layers 60a and 60b in the first region and the second region are the same as those of the aforementioned semiconductor power element 100, and are not repeated here. Different from the semiconductor power element 100, the first conductive type compound semiconductor layer 60a in the first region of the semiconductor power element 200 is a stripe pattern as viewed from above. In addition, as shown in FIGS. 8C and 8D, in order to take into consideration the functions of the semiconductor power element 200 to close and isolate the first conductive compound semiconductor layer 60a in the first region and the first conductive compound semiconductor layer 60b in the second region, In this embodiment, a recessed portion 28 and an insulating layer 42 on the recessed portion 28 are used to electrically insulate the first conductive compound semiconductor layers 60a and 60b in the first region and the second region, thereby closing the ring in the semiconductor power device 100 described above. Is a modification of the first conductive type compound semiconductor layer 60a of the type. Between the two ends of the first conductive type compound semiconductor layer 60a in the first region and the first conductive type compound semiconductor layer 60b in the second region, part of the barrier layer 50 and the channel layer 40 are removed by etching to form a recess 28, The bottom surface of the recessed portion 28 is a surface 401 exposed by etching the channel layer 40. The insulating layer 42 is formed on the bottom surface, the side wall, and a part of the upper surface of the first conductive type compound semiconductor layer 60 of the recessed portion 28.

The gate electrode G is disposed above the first conductive type compound semiconductor layer 60a in the first region, and has a stripe pattern similar to that of the first conductive type compound semiconductor layer 60a in the first region. The gate electrode G is provided along the first conductive type compound semiconductor layer 60 a in the first region, and extends from both ends of the first conductive type compound semiconductor layer 60 a in the first region to the insulating layer 42 in the recess 28. The source electrode S and the drain electrode D are disposed on the barrier layer 50 and on both sides of the gate electrode G, respectively.

9A to 10 are schematic diagrams of operation states of a plurality of semiconductor power elements 200. As in the aforementioned manufacturing process of the semiconductor power element, the state of each semiconductor power element 200 without the bias voltage applied to the gate electrode G is shown in FIGS. 9A to 9C, and FIG. 9B is a line B-B ′ in FIG. 9A A cross-sectional view of the line segment, FIG. 9C is a cross-sectional view along the line CC ′ in FIG. 9A. The channel layer 40 under the first conductive type compound semiconductor layer 60a in the first region does not have the two-dimensional electron gas 16, so the semiconductor power element 200 is not turned on and is turned off. In addition, as shown in FIG. 9C, in the recesses 28 at both ends of the gate electrode G and the first conductive compound semiconductor layer 60a in the first region, since the barrier layer 50 and part of the channel layer 40 have been removed by etching, Therefore, the two-dimensional electron gas 16 in the recessed portion 28 cannot be formed and is blocked, so that no current flows between the drain electrode D and the source electrode S, so that each element can be reliably closed.

When a bias voltage is applied to the gate electrode G, as shown in FIG. 10, a two-dimensional electron gas 16 is formed in a channel layer below the first conductive compound semiconductor layer 60a in the first region in each semiconductor power element 200. Therefore, each semiconductor power element 200 is turned on. In the channel layer 40 below the first conductive type compound semiconductor layer 60b in the second region, that is, the two-dimensional electron gas 16 is not formed in the element isolation region ISO, so that the elements can be electrically isolated. And since the first conductive type compound semiconductor layer 60a in the first region and the first conductive type compound semiconductor layer 60b in the second region are separated from each other, the two-dimensional electron gas 16 in the semiconductor power element 200 is separated from the surrounding element isolation area ISO Without being affected by each other, the electrical characteristics of individual semiconductor power components can be accurately measured on a single wafer.

However, the above embodiments are only for illustrative purposes to explain the principles and effects of the present application, and are not intended to limit the present application. Any person with ordinary knowledge in the technical field to which this application belongs can modify and change the above embodiments without departing from the technical principles and spirit of this application. Therefore, the scope of protection of the rights in this application is as listed in the scope of patent application described later.

1 wafer 10 substrate 18 blocking region 20 nucleation layer 28 recess 30 buffer structure 32 dielectric layer 40 channel layer 42 insulating layer 50 barrier layer 60 first conductive compound semiconductor layer 60a first conductive compound of first region Semiconductor layer 60b First conductive compound semiconductor layer 100, 200 in the second region Semiconductor power element A1, A2 Active region S Source electrode D Drain electrode G Gate electrode ISO element isolation region

(FIGS. 1A to 1B) are semiconductor power devices disclosed in one embodiment of the present invention. (Figures 2 to 5B) are a method for manufacturing a semiconductor power device disclosed in one embodiment of the present invention. (FIG. 6) is an operation state of the semiconductor power element disclosed in one embodiment of the present invention. (Figure 7) is a semiconductor power device disclosed in another embodiment of the present invention. (Figures 8A to 8D) are semiconductor power devices disclosed in another embodiment of the present invention. (FIGS. 9A to 9C) are operation states of a semiconductor power element disclosed in another embodiment of the present invention. (FIG. 10) is an operation state of a semiconductor power element disclosed in another embodiment of the present invention.

Claims (10)

A semiconductor power device includes: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas in the channel layer and adjacent to the channel layer and the resistor An interface between the barrier layers; a drain electrode, a gate electrode, and a source electrode are respectively located on the barrier layer; a first region P-type semiconductor layer is located between the gate electrode and the barrier layer And an isolation region forming layer located around the barrier layer, and the channel layer below the isolation region forming layer does not have the two-dimensional electron gas. The semiconductor power device according to item 1 of the application, wherein the isolation region forming layer includes a second region P-type semiconductor layer. The semiconductor power device according to item 2 of the scope of patent application, wherein the first region P-type semiconductor layer and the second region P-type semiconductor layer are separated from each other. The semiconductor power device according to item 2 of the scope of patent application, wherein the first region P-type semiconductor layer and the second region P-type semiconductor layer have the same material characteristics. The semiconductor power device according to item 2 of the scope of patent application, wherein the P-type semiconductor layer in the first region and the P-type semiconductor layer in the second region have the same thickness, the same material, the same conductivity type dopant, or the same doping concentration One of the material properties. The semiconductor power device according to item 1 of the application, wherein the gate electrode is located between the source electrode and the drain electrode, and the gate electrode is closed around the source electrode. The semiconductor power device described in item 1 of the patent application or wherein the channel layer and the barrier layer include an aluminum indium gallium nitride layer (Al _x In _y Ga _(1-xy) N), where 0 ≦ x <1, 0 ≦ x + y ≦ 1, and the energy gap of the barrier layer is greater than the energy gap of the channel layer. The semiconductor power device according to item 2 of the scope of patent application, wherein the second region P-type semiconductor layer surrounds the drain electrode, the gate electrode, and the source electrode in a top view, and / or the first A region P-type semiconductor layer has a closed ring shape or a bar shape in a top view. A method for manufacturing a semiconductor power device includes: providing a substrate; forming an epitaxial stack on the substrate, the epitaxial stack sequentially including: a channel layer; a barrier layer; and a P-type semiconductor layer; Removing a portion of the P-type semiconductor layer to form a first region P-type semiconductor layer and a second region P-type semiconductor layer, wherein the second region P-type semiconductor layer is located around the barrier layer; forming A source and a drain are on the barrier layer; and a gate is formed on the first region P-type semiconductor layer. The method for manufacturing a semiconductor power device according to item 9 of the scope of patent application, wherein a two-dimensional electron gas is included in the channel layer and adjacent to an interface between the channel layer and the barrier layer.