TWI768985B - Semiconductor structure and high electron mobility transistor - Google Patents

Abstract

A semiconductor structure includes a superlattice structure, an electrical isolation layer, a channel layer, and a composition gradient layer. The superlattice structure is disposed on a substrate, the electrical isolation layer is disposed on the superlattice structure, the channel layer is disposed on the electrical isolation layer, and the composition gradient layer is disposed between the electrical isolation layer and the superlattice structure, wherein the composition gradient layer and the superlattice structure include a same group III element, and the atomic percentage of the same group III element in the composition gradient layer is gradually decreased in the direction from the superlattice structure to the electrical isolation layer. In addition, a high electron mobility transistor including the semiconductor structure is also provided.

Description

Semiconductor structures and high electron mobility transistors

The present disclosure relates to the field of semiconductor devices, and more particularly, to a semiconductor structure and a high electron mobility transistor including the semiconductor structure.

In semiconductor technology, group III-V compound semiconductors can be used to form various integrated circuit devices, such as high power field effect transistors, high frequency transistors or high electron mobility transistors (HEMTs). HEMT is a transistor with two dimensional electron gas (2-DEG), and its 2-DEG will be adjacent to the junction between two materials with different energy gaps (ie, heterojunction) . Since HEMT does not use the doped region as the carrier channel of the transistor, but uses 2-DEG as the carrier channel of the transistor, compared with the conventional MOSFET, HEMT has various attractive Human characteristics such as high electron mobility and the ability to transmit signals at high frequencies.

For a conventional HEMT, a channel layer, a barrier layer, a compound semiconductor cap layer, and a gate electrode may be sequentially stacked. Using the gate electrode to bias the compound semiconductor cap layer, the two-dimensional electron gas concentration in the channel layer under the compound semiconductor cap layer can be regulated, and then the switching of the HEMT can be regulated.

However, the stress generated by the above-mentioned HEMT stack due to lattice mismatch, and then The polarization effect is formed, which leads to the leakage current phenomenon of the HEMT, thereby reducing the electrical performance of the HEMT.

In view of this, it is necessary to propose an improved high electron mobility transistor to improve the electrical performance of HEMT.

According to an embodiment of the present disclosure, a semiconductor structure is provided, including a superlattice structure, an electrical isolation layer, a channel layer, and a compositionally graded layer. The superlattice structure is arranged on the substrate, the electrical isolation layer is arranged on the superlattice structure, the channel layer is arranged on the electrical isolation layer, and the composition gradient layer is arranged between the electrical isolation layer and the superlattice structure, wherein the composition gradient layer The superlattice structure contains an identical Group III element, and the atomic percentage of this same Group III element in the compositionally graded layer gradually decreases from the superlattice structure to the electrical isolation layer.

According to an embodiment of the present disclosure, a high electron mobility transistor is provided, including the above-mentioned semiconductor structure, a barrier layer, a doped semiconductor cap layer, a gate electrode, a source electrode and a drain electrode. The barrier layer is arranged on the channel layer, the doped semiconductor cap layer is arranged on the barrier layer, the gate electrode is arranged on the doped semiconductor cap layer, and the source electrode and the drain electrode are respectively arranged on the gate electrode on both sides.

In order to make the features of the present disclosure clear and easy to understand, the following specific embodiments are given and described in detail as follows in conjunction with the accompanying drawings.

100: High electron mobility transistor

102: Substrate

104: Nucleation layer

106: Superlattice Structure

106-1: The first superlattice stack

106-2: Second Superlattice Stack

106A: first superlattice layer

106B: Second superlattice layer

108: Tensile stress layer

110: Composition of gradient layers

112: Electrical isolation layer

114: channel layer

116: Barrier layer

118: Doping semiconductor capping layer

120: Quarantine

122: source electrode

124: drain electrode

125: Contact hole

126: gate electrode

128: Passivation layer

128-1: First passivation layer

128-2: First passivation layer

130: Two-dimensional electron gas region

140: 2D Electric Hole Gas

150: Two-dimensional electron gas

C1: Numerical value

C2: Numerical value

C3: Numerical value

201: Straight

202: Arc

203: Stepped Curve

204: Wavy Curves

In order to make the following easier to understand, reference is made to both the drawings and their detailed description while reading the present disclosure. The specific embodiments of the present disclosure will be explained in detail through the specific embodiments herein and the corresponding drawings will be referred to, and the working principles of the specific embodiments of the present disclosure will be described. Furthermore, for clarity See, the features in the drawings may not be drawn to actual scale, so the dimensions of some features in some drawings may be intentionally enlarged or reduced.

FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure.

FIG. 2 is an enlarged cross-sectional schematic diagram of a first superlattice stack, a tensile stress layer, a compositionally graded layer and an electrical isolation layer of a HEMT according to another embodiment of the present disclosure.

Figures 3, 4, 5, and 6 illustrate the same group III elements such as aluminum in the compositionally graded layer, the tensile stress layer, and the uppermost second superlattice layer of the HEMT according to different embodiments of the present disclosure (Al) concentration curve of atomic percent as a function of different depth positions.

FIGS. 7, 8, 9, and 10 are schematic cross-sectional views of intermediate stages of manufacturing a HEMT according to an embodiment of the present disclosure.

The present disclosure provides several different embodiments for implementing different features of the present disclosure. For simplicity of illustration, the present disclosure also describes examples of specific components and arrangements. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or over the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between features", so that the first feature is not in direct contact with the second feature. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notation. These repeated reference signs and notations are used for brevity and clarity of description, rather than to indicate associations between different embodiments and/or configurations.

In addition, for the space-related narrative words mentioned in this disclosure, for example: "below", "low", "below", "above", "above", "below", "top" ”, “bottom” and similar words, for the convenience of description, their usage is to describe the relationship between one element or feature in the drawings and another (or more) elements or relative relationship of features. In addition to the pendulum shown in the drawings, these space-related terms are also used to describe the possible pendulum orientations of the semiconductor device during use and operation. With the different swing directions of the semiconductor device (rotated by 90 degrees or other orientations), the space-related descriptions used to describe the swing directions should also be interpreted in a similar manner.

Although the present disclosure uses the terms first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that such elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not by themselves imply or represent that element The presence of any preceding ordinal numbers does not imply the order in which an element is arranged relative to another element, or the order of the method of manufacture. Thus, a first element, component, region, layer or block discussed below could be termed a second element, component, region, layer or block without departing from the scope of the specific embodiments of the present disclosure Of.

The terms "about" or "substantially" referred to in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, the meaning of "about" or "substantially" can still be implied without the specific description of "about" or "substantially".

In the present disclosure, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III (group III) element and at least one group V (group V) element. Wherein, the third group element can be boron (B), aluminum (Al), gallium (Ga) or indium (In), and the fifth group element can be nitrogen (N), phosphorus (P), arsenic (As) or Antimony (Sb). Further, "group III and V semiconductors" can be binary compound semiconductors, ternary compound semiconductors or quaternary compound semiconductors, including: gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), Gallium Arsenide (GaAs), Aluminum Gallium Nitride (AlGaN), Indium Aluminum Gallium Nitride (InAlGaN), Indium Gallium Nitride (InGaN), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Arsenide Gallium (AlGaAs), Aluminum Indium Arsenide (InAlAs), Indium Gallium Arsenide (InGaAs), Aluminum Nitride (AlN), Gallium Indium Phosphide (GaInP), Aluminum Gallium Arsenide (AlGaAs), Aluminum Indium Arsenide (InAlAs), Indium Gallium Arsenide (InGaAs) , its analogs, or a combination of the above compounds, but not limited thereto. In addition, depending on the requirements, dopants may also be included in the III-V semiconductor, which is a III-V semiconductor with a specific conductivity type, such as an n-type or p-type III-V semiconductor. Hereinafter, group III-V semiconductors may also be referred to as group III-V semiconductors.

Although the invention of the present disclosure is described below with reference to specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. Furthermore, in order not to obscure the spirit of the present invention, certain details will be omitted, which are within the knowledge of those having ordinary skill in the art.

The present disclosure relates to a semiconductor structure, and a high electron mobility transistor (HEMT) including the semiconductor structure, which can be used as a power switching transistor for voltage converter applications. Compared with silicon power transistors, group III-V semiconductor HEMTs (III-V HEMTs) have the characteristics of low on-state resistance and low switching loss due to their wider energy bandgap.

FIG. 1 is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure. As shown in FIG. 1, according to an embodiment of the present disclosure, a high electron mobility transistor 100, such as an enhancement type HEMT, is disposed on a substrate 102, and a nucleation layer may be disposed on the substrate 102 in sequence 104. A superlattice (SL) structure 106, a composition gradient layer 110, an electrical isolation layer 112, a channel layer 114, a barrier layer 116, a doped semiconductor cap layer 118, and Passivation layer 128. According to an embodiment, the superlattice structure 106 may include two or more different superlattice stacks, eg, the first superlattice stack 106-1 is disposed on the second superlattice stack 106-2. Each superlattice stack may include a plurality of pairs of superlattice layers, and the superlattice layers may be periodically alternately stacked. Each superlattice layer may be composed of two or more materials, and the thickness of each superlattice layer is about several nanometers (nm) to tens of nanometers. The first superlattice stack 106-1 and the second superlattice stack 106-2 may have different material compositions, different material composition ratios, or material periodicity Alternate stacking is different. According to another embodiment, the superlattice structure 106 may be a single superlattice stack, such as the first superlattice stack 106-1.

In addition, the high electron mobility transistor 100 further includes a gate electrode 126 , a source electrode 122 and a drain electrode 124 , wherein the gate electrode 126 is disposed on the doped semiconductor cap layer 118 and penetrates through the passivation layer 128 . 122 and the drain electrode 124 are respectively disposed on both sides of the gate electrode 126 . According to some embodiments, source electrode 122 and drain electrode 124 may extend from passivation layer 128 down into barrier layer 116 or channel layer 114 and spaced a vertical distance from electrical isolation layer 112 . In addition, the isolation region 120 is disposed on the periphery of the source electrode 122 and the drain electrode 124 to isolate the adjacent HEMTs. The isolation region 120 passes through the barrier layer 116 into the channel layer 114 , and the bottom of the isolation region 120 is lower than the bottoms of the source electrode 122 and the drain electrode 124 , so that the isolation region 120 is deeper than the source electrode 122 and the drain electrode 124 . Close to the electrical isolation layer 112 to achieve good electrical isolation. However, in other embodiments, the isolation region 120 can be extended to other layers according to actual requirements to achieve electrical isolation.

According to an embodiment of the present disclosure, the channel layer 114 may include one or more III-V semiconductor layers, and the composition of the III-V semiconductor layers may be GaN, AlGaN, InGaN or InAlGaN, but not limited thereto. In addition, the channel layer 114 may be undoped or doped one or more III-V semiconductor layers. The doped channel layer 114 may be, for example, a p-type III-V semiconductor layer. For the III-V semiconductor layer, the dopant may be carbon (C), iron (Fe), magnesium (Mg) or zinc (Zn), but is not limited thereto. The above-mentioned barrier layer 116 may include one or more III-V semiconductor layers, and its composition may be different from that of the channel layer 114 . For example, the barrier layer 116 may include AlN, AlzGa _{(1-z) N} (0<z<1), or a combination thereof. According to an embodiment, the channel layer 114 may be an undoped GaN layer and the barrier layer 116 may be an undoped or intrinsically n-type AlGaN layer. Since there is a discontinuous energy gap between the channel layer 114 and the barrier layer 116, by stacking the channel layer 114 and the barrier layer 116 on each other, electrons will be collected in the channel layer 114 and the barrier layer 116 due to the piezoelectric effect Heterojunction between them, thus creating a thin layer of high electron mobility, ie, a two-dimensional electron gas (2-DEG) region 130 . For normally off devices, when no voltage is applied to the gate electrode 126, the region covered by the doped semiconductor cap layer 118 will not form 2-DEG, which can be regarded as a 2-DEG cut-off region. At this time, there is no conduction between the source electrode 122 and the drain electrode 124 . When a positive voltage is applied to the gate electrode 126, a 2-DEG is formed in the area covered by the doped semiconductor capping layer 118, resulting in a continuous 2-DEG region 130 between the source electrode 122 and the drain electrode 124, while Conduction is established between the source electrode 122 and the drain electrode 124 .

2 is an enlarged cross-sectional schematic diagram of a first superlattice stack, a tensile stress layer, a compositionally graded layer and an electrical isolation layer of a high electron mobility transistor according to another embodiment of the present disclosure. The difference between FIG. 2 and FIG. 1 is that a tensile stress layer 108 is further disposed between the first superlattice stack 106 - 1 and the compositionally graded layer 110 in FIG. 2 . As shown in FIG. 2, according to an embodiment of the present disclosure, the first superlattice stack 106-1 of the high electron mobility transistor 100 can be composed of a plurality of first superlattice layers 106A and second superlattice layers stacked in pairs Grid layer 106B is formed. Although FIG. 2 only shows four superlattice layers stacked in pairs, according to other embodiments of the present disclosure, the first superlattice stack 106-1 may also be composed of more superlattice layers stacked in pairs, such as More than 100 pairs of superlattice layers are formed. The first superlattice layer 106A has tensile stress, the second superlattice layer 106B has compressive stress, and the second superlattice layer 106B is stacked on the first superlattice layer 106A. In other words, the first superlattice layer 106A generates tensile stress on the adjacent second superlattice layer 106B, and the second superlattice layer 106B generates compressive stress on the adjacent first superlattice layer 106A. By adjusting the thickness of each layer of the first superlattice layer 106A and the second superlattice layer 106B, the 2-DEG 150 in the second superlattice layer 106B other than the uppermost second superlattice layer 106B can be made. and 2-DHG 140 are paired with each other, thereby offsetting the effects of the 2-DEG layer and the 2-DHG layer. In addition, according to an embodiment of the present disclosure, by disposing the tensile stress layer 108 on the uppermost second superlattice layer 106B, 2-DEG can be generated in the uppermost second superlattice layer 106B to offset the uppermost second superlattice layer 106B. 2-DHG in the upper second superlattice layer 106B, thereby avoiding the generation of 2-DHG layers that are not paired with 2-DEG in the uppermost second superlattice layer 106B, thereby preventing the generation of lateral current transmission paths , to avoid leakage current between adjacent HEMTs.

In addition, according to an embodiment of the present disclosure, at the first position between the electrical isolation layer 112 and the superlattice structure 106 A compositionally graded layer 110 is disposed between a superlattice stack 106 - 1 , and the compositionally graded layer 110 is disposed on the tensile stress layer 108 . The compositionally graded layer 110 can be used to eliminate the compressive stress of the electrical isolation layer 112 to the tensile stress layer 108 . According to an embodiment of the present disclosure, the composition of the superlattice structure 106 , the tensile stress layer 108 and the compositionally graded layer 110 includes a same Group III element, and the composition of the same Group III element in the compositionally graded layer 110 The atomic percentage gradually decreases from the superlattice structure 106 to the electrical isolation layer 112 to avoid compressive stress in the electrical isolation layer 112 . In this way, 2-DHG will not be generated at the interface between the electrical isolation layer 112 and the composition graded layer 110, so that the 2-DHG layer on the bottom surface of the electrical isolation layer 112 can be avoided, thereby preventing the generation of lateral current transmission paths and avoiding phase Leakage current occurs between adjacent HEMTs.

In addition, according to an embodiment of the present disclosure, the bottom of the gradation layer 110 can have tensile stress by adjusting the composition of the gradation layer 110 . Thereby, tensile stress can be generated on the uppermost second superlattice layer 106B, and 2-DEG can be generated in the uppermost second superlattice layer 106B to offset the uppermost second superlattice layer 2-DHG in 106B. Therefore, even if the tensile stress layer 108 is not provided, the degree of leakage current between adjacent HEMTs can be reduced.

In addition, the embodiments of the present disclosure can avoid leakage current between adjacent HEMTs. Due to the composition of the graded composition layer 110 , the tensile stress layer 108 and the superlattice structure 106 , these stacked layers have good crystallinity. Lattice matching can prevent the HEMT stack from generating stress, thereby avoiding the polarization effect, so that various leakage currents of the HEMT disclosed in the present disclosure are reduced, thereby improving the electrical performance of the HEMT.

According to an embodiment of the present disclosure, the composition of the compositionally graded layer 110 may be a ternary III-V semiconductor, such as aluminum gallium nitride ( _{AlxGa (1-x)} N), where 0.1<x<0.9, and the value of x is From the superlattice structure 106 to the electrical isolation layer 112, the atomic percentage of the same group III element, such as aluminum (Al), decreases from bottom to top, that is, in the depth direction. , and the atomic percentage of another third group element such as gallium (Ga) in the composition graded layer 110 increases from bottom to top, and the other third group element such as gallium (Ga) is contained in the electrical isolation layer 112 . In one embodiment, the composition of the tensile stressor layer 108 may be a binary III-V semiconductor, such as aluminum nitride (AlN). According to an embodiment, the average atomic concentration of this same Group III element, eg, aluminum (Al), in tensile stress layer 108 is higher than the average atomic concentration of this same Group III element, eg, aluminum (Al), in compositionally graded layer 110 . Atomic concentration. In addition, in one embodiment, the thickness of the compositionally graded layer 110 may be 0.5% to 5% of the thickness of the electrical isolation layer 112 , and the thickness of the tensile stress layer 108 may be 0.2% to 2% of the thickness of the electrical isolation layer 112 . It should be noted that the thicknesses of the compositionally graded layer 110 and the tensile stress layer 108 must be greater than the thicknesses of the respective superlattice layers, for example, greater than the thicknesses of the first superlattice layer 106A or the second superlattice layer 106B, in order to generate Or relieve the stress at the interface. According to an embodiment of the present disclosure, the compositionally graded layer 110 may be doped with a dopant, and the dopant may be carbon or iron, thereby increasing the resistivity of the compositionally graded layer 110 .

According to an embodiment of the present disclosure, when comparing the first superlattice layer 106A and the second superlattice layer 106B, the composition of the first superlattice layer 106A has a smaller lattice constant and a wider energy gap, such as Aluminum nitride (AlN), the composition of the second superlattice layer 106B has a relatively large lattice constant and a relatively narrow energy gap, such as aluminum gallium nitride ( _{AlyGa (1-y)} N, where 0.05<y< 0.3). The average atomic concentration of the aforementioned same Group III elements such as aluminum (Al) in the compositionally graded layer 110 is higher than the average atomic concentration of this same Group III element such as aluminum (Al) in the second superlattice layers 106B . According to an embodiment, the atomic percentage of aluminum (Al) in each second superlattice layer 106B in the first superlattice stack 106-1 may be different, that is, the gallium (Al) in each second superlattice layer 106B The atomic percentage of Ga) may be different, for example, the atomic percentage of aluminum (Al) in each second superlattice layer 106B may vary with each layer, decreasing from the lower layer to the upper layer, so as to reduce the atomic percentage of the first superlattice stack 106-1. stress. In addition, according to an embodiment, the first superlattice layer 106A and the second superlattice layer 106B of the first superlattice stack 106-1 may be doped with a dopant, and the dopant may be carbon or iron, Thereby, the resistivity of the first superlattice stack 106-1 can be increased.

Furthermore, according to an embodiment of the present disclosure, as shown in FIG. 1, the superlattice structure 106 may include a second superlattice stack 106-2 disposed under the first superlattice stack 106-1, similar to the second superlattice stack 106-2. The first superlattice stack 106-1 and the second superlattice stack 106-2 shown in the figure may be composed of a plurality of third superlattice layers and fourth superlattice layers stacked in pairs, wherein the third superlattice layer The lattice layer has tensile stress, the fourth superlattice layer has compressive stress, and the fourth superlattice layer is stacked on the third superlattice layer, by adjusting the third superlattice layer and the fourth superlattice layer The thickness of each layer can prevent unpaired 2-DEG layer and 2-DHG layer from being generated in the second superlattice stack 106-2. In addition, in one embodiment, the composition of the third superlattice layer is, for example, aluminum nitride (AlN), and the composition of the fourth superlattice layer is, for example, aluminum gallium nitride (AlwGa _{(1-w) N} , where 0.1<w<0.5), and the average atomic concentration of aluminum (Al) in the second superlattice stack 106-2 is higher than the average atomic concentration of aluminum (Al) in the first superlattice stack 106-1. In one embodiment, the atomic percentage of aluminum (Al) in each of the fourth superlattice layers may be different, that is, the atomic percentage of gallium (Ga) in each of the fourth superlattice layers may be different. The atomic percentage of aluminum (Al) in the superlattice layers may vary with each layer, decreasing from the lower layer to the upper layer, to reduce the stress of the second superlattice stack 106-2. In addition, according to an embodiment, the third superlattice layer and the fourth superlattice layer of the second superlattice stack 106-2 may be doped with a dopant, and the dopant may be carbon or iron, thereby The resistance of the second superlattice stack 106-2 can be increased. According to an embodiment, the average atomic concentration of the aforementioned same group III elements such as aluminum (Al) in the compositionally graded layer 110 is higher than that of the same group III elements such as aluminum (Al) in the fourth superlattice layers The average atomic concentration of .

In addition, according to an embodiment of the present disclosure, the average atomic concentration of the same group III element such as aluminum (Al) in the compositionally graded layer 110 is lower than that of the same group III element such as aluminum in the overall superlattice structure 106 (Al) average atomic concentration. According to an embodiment, the thickness of the tensile stress layer 108 is greater than the thickness of each superlattice layer in the superlattice structure 106, eg, greater than the thickness of the first superlattice layer 106A, the second superlattice layer 106A of the first superlattice stack 106-1 The thickness of the lattice layer 106B is also greater than the thickness of the third superlattice layer and the third superlattice layer of the second superlattice stack 106-2.

According to an embodiment of the present disclosure, the composition of the electrical isolation layer 112 may be a doped or undoped binary III-V semiconductor, such as carbon-doped gallium nitride (c-GaN), and is electrically isolated The concentration of the carbon dopant in the layer 112 gradually increases from the compositionally graded layer 110 to the channel layer 114, that is, in the depth direction, the concentration of the carbon dopant in the electrical isolation layer 112 increases from bottom to top to prevent Carbon is deposited at the interface between the electrical isolation layer 112 and the compositionally graded layer 110 , thereby making the surface of the electrical isolation layer 112 close to the channel layer 114 higher in resistance to provide better electrical isolation.

FIG. 3 shows the same Group III elements in the compositionally graded layer, the tensile stress layer, and the uppermost second superlattice layer of a high electron mobility transistor (HEMT) according to an embodiment of the present disclosure For example, the concentration curve of the atomic percentage of aluminum (Al) as a function of different depth positions. The horizontal axis of FIG. 3 is the position of the composition graded layer 110, the tensile stress layer 108 and the uppermost second superlattice layer 106B in the depth direction, and the vertical axis is the atomic percentage of aluminum (Al). According to an embodiment, As shown in FIG. 3, the atomic percentage of aluminum (Al) of the uppermost second superlattice layer 106B is about C3, the atomic percentage of aluminum (Al) of the tensile stress layer 108 is the highest value of C2, and the composition graded layer The atomic percentage of aluminum (Al) of 110 decreases from bottom to top in the depth direction, gradually decreasing from the value C1 to nearly 0, where the value C3 is about 10%, the value C2 is about 50%, and the value C1 is about 30%, at In this embodiment, the concentration variation curve of the atomic percentage of aluminum (Al) constituting the graded layer 110 may be a straight line 201 . In one embodiment, the atomic percentage of aluminum (Al) constituting the graded layer 110 may also be gradually reduced to near 0 from other values higher or lower than the value C1 as a starting value. According to an embodiment of the present disclosure, the average atomic concentration of aluminum (Al) in the tensile stress layer 108 is higher than the average atomic concentration of aluminum (Al) in the compositionally graded layer 110 , and the average atomic concentration of aluminum (Al) in the compositionally graded layer 110 is higher than The average atomic concentration of aluminum (Al) in the uppermost second superlattice layer 106B.

FIGS. 4 , 5 and 6 are respectively the same third of the compositionally graded layer, the tensile stress layer and the uppermost second superlattice layer of the HEMT according to some embodiments of the present disclosure. Concentration curves of atomic percent of group elements such as aluminum (Al) as a function of different depth positions. The difference between the embodiment in FIG. 4 and FIG. 3 is that the concentration change curve of the atomic percentage of aluminum (Al) in the composition graded layer 110 can be an arc 202 . The difference between the embodiment in FIG. 5 and FIG. 3 lies in the composition graded layer 110 . The concentration change curve of the atomic percentage of aluminum (Al) can be a step-shaped curve 203. The difference between the embodiment in FIG. 6 and FIG. 3 is that the concentration change curve of the aluminum (Al) atomic percentage of the composition graded layer 110 can be wave-shaped. For the curve 204, other similar parts can be referred to the description of FIG. 3 above.

FIG. 7 , FIG. 8 , FIG. 9 , and FIG. 10 are respectively schematic cross-sectional views of intermediate stages of fabricating the high electron mobility transistor 100 according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, As shown in FIG. 7, a substrate 102 is provided on which a nucleation layer 104, a superlattice structure 106, a tensile stress layer 108, a compositionally graded layer 110, an electrical isolation layer 112, a channel layer 114, a barrier layer are formed in sequence Layer 116 and a stack of doped semiconductor capping layers 118 . In one embodiment, the superlattice structure 106 may consist of a first superlattice stack 106-1 disposed on a second superlattice stack 106-2. In another embodiment, the superlattice structure 106 may be composed of the first superlattice stack 106-1.

According to an embodiment, the substrate 102 may be a bulk silicon substrate, a silicon carbide (SiC) substrate, a sapphire (sapphire) substrate, a silicon on insulator (SOI) substrate, or a germanium on insulator (germanium on insulator, GOI) substrate, but not limited to this. In another embodiment, the substrate 102 further includes a single or multiple layers of insulating material and/or other suitable material layers (eg, semiconductor layers) and a core layer. The insulating material layer may be oxide, nitride, oxynitride, or other suitable insulating material. The core layer may be silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), aluminum gallium nitride (AlGaN), zinc oxide (ZnO), or gallium oxide (Ga ₂ O ₃ ), or Other suitable ceramic materials. In one embodiment, a single or multiple layers of insulating material and/or other suitable material layers coat the core layer.

The nucleation layer 104 can be selectively disposed on the substrate 102 , which has less lattice defects, and thus can improve the epitaxial quality of the superlattice structure 106 disposed on the nucleation layer 104 . In one embodiment, the nucleation layer 104 may include a nitride (AlN) stack layer, eg, may include a first nitride layer and a second nitride layer. According to an embodiment of the present disclosure, the first nitride layer may be, for example, a low temperature aluminum nitride layer (LT-AlN), and the low temperature aluminum nitride layer may be deposited by metal-organic chemical vapor deposition (MOCVD). Formed at an ambient temperature of 800°C-1100°C; the second nitride layer can be, for example, a high temperature aluminum nitride layer (HT-AlN), which can be deposited by metal organic chemical vapor deposition at 1100°C-1400 It is formed at an ambient temperature of °C, but is not limited to this.

The superlattice structure 106 is disposed on the substrate 102. According to an embodiment of the present disclosure, the second superlattice stack 106-2 of the superlattice structure 106 can be selectively disposed on the nucleation layer 104. Next, the first superlattice The lattice stack 106-1 is disposed on the second superlattice stack 106-2, or the first superlattice stack 106-1 may be disposed on the nucleation layer 104 when the second superlattice stack 106-2 is omitted. The superlattice structure 106 can be used to reduce the degree of lattice mismatch between the substrate 102 and the semiconductor layers disposed on the superlattice structure 106, and to reduce the stress caused by the lattice mismatch. According to an embodiment of the present disclosure, as shown in FIG. 2 , the first superlattice stack 106 - 1 may include a first superlattice layer 106A and a second superlattice layer 106B. Similarly, the second superlattice stack 106-2 may include a plurality of pairs of superlattice layers, such as a third superlattice layer and a fourth superlattice layer. According to different requirements, the first superlattice stack 106-1 and the second superlattice stack 106-2 can each be a structure composed of at least two kinds of III-V semiconductor layers stacked periodically, for example, each includes a plurality of Pairs of AlN thin layers/AlGaN thin layers or a plurality of pairs of AlN thin layers/GaN thin layers, or structures each comprising a stack of a plurality of III-V semiconductor layers with graded composition ratios, such as aluminum nitride The composition ratio of aluminum in gallium (Al _a Ga _1-a N, 0.15≦a≦0.9) may gradually decrease from the lower superlattice layer to the upper superlattice layer, but is not limited thereto. According to an embodiment, the superlattice structure 106 may be formed by an atomic layer deposition (ALD) process by adjusting the ratio of source gases for depositing each atomic layer, such as aluminum (Al), nitrogen (N), and gallium ( Ga) ratio of source gas, multiple superlattice layer stacks of various composition ratios can be deposited.

According to an embodiment of the present disclosure, the tensile stress layer 108 may be selectively disposed on the superlattice structure 106 , the compositionally graded layer 110 may be formed on the tensile stress layer 108 , and the composition of the tensile stress layer 108 and the compositionally graded layer 110 may be formed. As mentioned above, it will not be repeated here. According to an embodiment, the compositionally graded layer 110 and the tensile stress layer 108 can be formed by an atomic layer deposition (ALD) process, by adjusting the ratio of source gas for depositing each atomic layer, such as adjusting aluminum (Al), nitrogen ( The ratio of N) and gallium (Ga) source gases can deposit a plurality of atomic layer stacks with graded composition ratios, thereby forming a graded composition layer 110 with graded aluminum (Al) atomic percentage or atomic concentration, for example. According to an embodiment, the thickness of the tensile stress layer 108 may be 2 nm to 20 nm, or may be 0.2% to 2% of the thickness of the electrical isolation layer 112; the thickness of the compositionally graded layer 110 may be 5 nm to 50 nm, or may be electrically isolated 0.5% to 5% of the thickness of layer 112.

According to an embodiment of the present disclosure, the electrical isolation layer 112 is disposed on the composition graded layer 110, and the electrical isolation layer 112 is Compared with other layers, the debonding layer 112 has a higher resistivity, so that leakage current can be avoided between the semiconductor layer disposed on the electrical isolation layer 112 and the substrate 102 . The channel layer 114 may be disposed on the electrical isolation layer 112 , and the barrier layer 116 may be disposed on the channel layer 114 . The compositions of the channel layer 114 and the barrier layer 116 are as described above, and will not be repeated here. A doped semiconductor capping layer 118 may be formed on the barrier layer 116 to deplete the two-dimensional electron gas (2-DEG) region to achieve a normally-off state of the HEMT. The doped semiconductor capping layer 118 may be one or more doped III-V semiconductor layers, such as GaN doped with p-type dopants or n-type dopants. Its composition can be GaN, AlGaN, InGaN or InAlGaN, and its dopant can be C, Fe, Mg or Zn, but not limited thereto. According to an embodiment, the doped semiconductor capping layer 118 may be a p-type GaN layer.

Next, according to an embodiment of the present disclosure, as shown in FIG. 8, a patterned doped semiconductor capping layer 118 is formed on the barrier layer 116, and the patterned doped semiconductor capping layer 118 can be formed by lithography and etching processes . Then, isolation regions 120 are formed around the HEMTs to isolate adjacent HEMTs. According to one embodiment, isolation region 120 extends through barrier layer 116 down into channel layer 114 and is spaced apart from electrical isolation layer 112 . In one embodiment, the isolation region 120 may be a shallow trench isolation (STI), which may form trenches in the barrier layer 116 and the channel layer 114 through an etching process, and then fill the trenches with a layer Or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, or a combination thereof, are subjected to a chemical mechanical polishing (CMP) process to form the isolation region 120 . In another embodiment, the isolation region 120 can be formed by ion implantation, and a hard mask is used to cover the area outside the predetermined isolation region 120, and dopants are implanted into the barrier layer 116 and the channel layer 114 to form isolation In region 120, the dopant is, for example, helium or carbon.

Next, according to an embodiment of the present disclosure, as shown in FIG. 9 , a first passivation layer 128 - 1 is formed on the isolation region 120 and the barrier layer 116 , and source electrodes are formed on both sides of the doped semiconductor cap layer 118 122 and drain electrode 124. In one embodiment, the source electrode 122 and the drain electrode 124 extend through the first passivation layer 128-1 and the barrier layer 116 and extend down into the channel layer 114, so that the bottom of the source electrode 122 and the drain electrode 124 Above the bottom of isolation region 120 and below the top surface of channel layer 114 . In another embodiment, the source electrode 122 and the drain electrode 124 penetrate the first passivation layer 128-1 and extend down into the barrier layer 116, so that the bottom of the source electrode 122 and the drain electrode 124 is higher than the bottom of the isolation region 120 and lower than the barrier The top surface of layer 116 .

According to an embodiment, the first passivation layer 128-1 may be deposited to cover the isolation region 120, the barrier layer 116 and the doped semiconductor capping layer 118, and then the first passivation layer 128-1, the barrier layer 116 and the channel layer may be deposited. Contact holes for the source electrode 122 and the drain electrode 124 on both sides of the doped semiconductor cap layer 118 are formed in 114, and then a conductive material layer is deposited in the contact holes and on the first passivation layer 128-1. In one embodiment, the source electrode 122 and the drain electrode 124 can be formed through a chemical mechanical polishing process, and the top surface of the doped semiconductor cap layer 118 is exposed, wherein the top surface of the source electrode 122 and the drain electrode 124 can be The top surface of the doped semiconductor capping layer 118 is flush. In another embodiment, after the conductive material layer is deposited, an etching process may be used to remove the conductive material layer outside the contact holes to form the source electrode 122 and the drain electrode 124 , and to doped the semiconductor cap layer 118 . The top surface may still be covered by the first passivation layer 128-1.

According to an embodiment, the source electrode 122 and the drain electrode 124 may be a single-layer or multi-layer structure, and the composition may include an ohmic contact metal. Wherein, the ohmic contact metal refers to a metal, an alloy or a stacked layer thereof that can produce ohmic contact with the semiconductor layer (eg, the channel layer 114 ), such as Ti, Ti/Al, Ti/Al/Ti/TiN, Ti /Al/Ti/Au, Ti/Al/Ni/Au or Ti/Al/Mo/Au, but not limited thereto.

Next, according to an embodiment of the present disclosure, as shown in FIG. 10, a second passivation layer 128-2 is formed to cover the first passivation layer 128-1, the doped semiconductor cap layer 118, the source electrode 122 and the drain electrode 124, The first passivation layer 128 - 1 and the second passivation layer 128 - 2 may be collectively referred to as the passivation layer 128 . Then, a contact hole 125 of the gate electrode 126 is formed in the second passivation layer 128 - 2 to expose the top surface of the doped semiconductor capping layer 118 . According to an embodiment of the present disclosure, in the case where an etch stop layer (not shown) is disposed on the top surface of the doped semiconductor cap layer 118 , the etch stop layer may be exposed to the contact holes 125 . The etch stop layer can be used to protect the doped semiconductor capping layer 118 to prevent the doped semiconductor capping layer 118 from directly contacting the etchant used for forming the contact hole 125 . Afterwards, a conductive material layer is deposited in the contact hole 125 and on the second passivation layer 128-2. After the conductive material layer is patterned by the shadow and etching process, the gate electrode 126 as shown in FIG. 1 is formed. According to one embodiment, the top surface of the gate electrode 126 is higher than the top surface of the passivation layer 128 . In another embodiment, a portion of the gate electrode 126 may also extend to the top surface of the passivation layer 128 .

According to an embodiment, the gate electrode 126 may be a single-layer or multi-layer structure, for example, a double-layer structure including a first conductive layer and a second conductive layer. The first conductive layer can directly contact the doped semiconductor capping layer 118, and its composition includes Schottky contact metal. Wherein, the Schottky contact metal refers to a metal, an alloy or a stacked layer thereof that can form a Schottky contact with a semiconductor layer (eg, the doped semiconductor cap layer 118 ), such as TiN, W, Pt, Ni or Ni, but not limited to this. The composition of the second conductive layer may include Ti, Al, Au, Mo, but is not limited thereto. According to an embodiment, the first conductive layer may further comprise metal nitrides of refractory metals, and the refractory metals may be selected from titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, onium, rhenium , the group consisting of ruthenium, osmium, rhodium and iridium.

According to an embodiment, the materials of the first passivation layer 128-1 and the second passivation layer 128-2 include aluminum oxide (Al ₂ O ₃ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or Silicon oxide (SiO ₂ ), and the materials of the first passivation layer 128-1 and the second passivation layer 128-2 may be the same. In another embodiment, the materials of the first passivation layer 128-1 and the second passivation layer 128-2 may be different.

According to one of the objectives of the embodiments of the present disclosure, the generation of a current transmission path between the superlattice structure and the electrical isolation layer can be avoided. According to another objective of the embodiments of the present disclosure, the problem of mutual interference of leakage current between adjacent HEMTs is avoided. This not only improves the accuracy of the bare die pin test (CP) test before packaging, but also more accurately determines whether the HEMT meets the electrical specifications, while maintaining the 2-DEG performance of the HEMT and improving the electrical performance of the HEMT.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: High electron mobility transistor

102: Substrate

104: Nucleation layer

106: Superlattice Structure

106-1: The first superlattice stack

106-2: Second Superlattice Stack

110: Composition of gradient layers

112: Electrical isolation layer

114: channel layer

116: Barrier layer

118: Doping semiconductor capping layer

120: Quarantine

122: source electrode

124: drain electrode

126: gate electrode

128: Passivation layer

130: Two-dimensional electron gas region

Claims (12)

A semiconductor structure, comprising: a superlattice structure disposed on a substrate; an electrical isolation layer disposed on the superlattice structure; a channel layer disposed on the electrical isolation layer; and a composition gradient layer, disposed between the electrical isolation layer and the superlattice structure, wherein the electrical isolation layer comprises carbon-doped gallium nitride (C-GaN), the compositionally graded layer and the superlattice structure comprise a same third Group elements, and the atomic percentage of the same Group III elements in the compositionally graded layer gradually decreases in the direction from the superlattice structure to the electrical isolation layer. The semiconductor structure of claim 1, further comprising a tensile stress layer disposed between the superlattice structure and the compositionally graded layer, wherein the tensile stress layer includes the same Group III element. The semiconductor structure of claim 2, wherein the average atomic concentration of the same Group III element in the tensile stress layer is higher than the average atomic concentration of the same Group III element in the compositionally graded layer. The semiconductor structure of claim 2, wherein the composition of the compositionally graded layer comprises aluminum gallium nitride ( _{AlxGa (1-x)} N), wherein 0.1<x<0.5, and the value of x is derived from the superlattice structure Decreasing in the direction of the electrical isolation layer, the composition of the tensile stress layer includes aluminum nitride (AlN). The semiconductor structure of claim 2, wherein the tensile stress layer has a thickness equal to the electrical spacer 0.2% to 2% of the thickness of the separation layer. The semiconductor structure of claim 1, wherein the compositionally graded layer comprises a dopant, and the dopant comprises carbon or iron. The semiconductor structure of claim 1, wherein the electrical isolation layer comprises another Group III element, and the compositionally graded layer comprises the other Group III element, the other Group III element in the compositionally graded layer The atomic percentage of elements gradually increases in the direction from the superlattice structure to the electrical isolation layer. The semiconductor structure of claim 1, wherein the electrical isolation layer comprises a carbon dopant, and the concentration of the carbon dopant in the electrical isolation layer gradually increases from the compositionally graded layer to the channel layer. The semiconductor structure of claim 1, wherein the average atomic concentration of the same Group III element in the compositionally graded layer is lower than the average atomic concentration of the same Group III element in the superlattice structure. The semiconductor structure of claim 1, wherein the superlattice structure comprises a first superlattice layer and a second superlattice layer stacked in pairs, and the first superlattice layer has tensile stress , the second superlattice layer has compressive stress, and the second superlattice layer is stacked on the first superlattice layer, the bottom of the composition graded layer contacts the second superlattice layer of the uppermost layer, the The average atomic concentration of the same Group III element in the compositionally graded layer is higher than the average atomic concentration of the same Group III element in the second superlattice layers. The semiconductor structure of claim 1, wherein the thickness of the compositionally graded layer is 0.5% to 5% of the thickness of the electrical isolation layer. A high electron mobility transistor, comprising: a semiconductor structure as claimed in claim 1; a barrier layer disposed on the channel layer; a doped semiconductor cap layer disposed on the barrier layer; a gate The electrode electrode is arranged on the doped semiconductor cap layer; and a source electrode and a drain electrode are respectively arranged on both sides of the gate electrode.

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