TW201909422A - Semiconductor power device and manufacturing method thereof - Google Patents

Abstract

A semiconductor power device includes a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a two-dimensional electron gas (2 DEG) located within the channel layer and adjacent to an interface between the channel layer and the barrier layer; a drain electrode, a gate electrode, and a source electrode, disposed on the barrier layer, respectively; a first region of p-type semiconductor layer disposed between the gate electrode and the barrier layer; and an isolation region forming layer, disposed on peripheral of the barrier layer; wherein the channel layer that is under the isolation region forming layer is devoid of the 2 DEG.

Description

Semiconductor power component and method of manufacturing same

The present invention relates to a semiconductor power device, and more particularly to a semiconductor power device including a nitride semiconductor.

In recent years, due to the increasing demand for high frequency and high power products, semiconductor power components such as aluminum gallium nitride-gallium nitride (AlGaN/GaN) based on gallium nitride have been achieved due to high-speed electron mobility. Very fast switching speed, component characteristics that can be operated in high frequency, high power and high temperature working environments, so it is widely used in power supply, DC/DC converter, DC/AC converter AC/DC inverter and industrial applications, including electronic products, uninterruptible power systems, automobiles, motors, wind power generation, etc.

The active region range of a semiconductor power device is generally defined by the area of the region through which the current flows under the component conduction, and the active region range is defined in the component process. When the active area ranges of the individual components are distinguished on the wafer, the individual components can be tested on the wafer to derive the electrical characteristics of the individual components; therefore, the isolation between the components must be ensured. In the conventional GaN semiconductor power device process, a portion of the semiconductor layer may be removed by dry etching or an ion implantation may be performed in the semiconductor layer to form an isolation region between the components, so that no conduction between the components is performed. Layers to complete separate multiple components on a single wafer.

The present application discloses a semiconductor power device comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas located in the channel layer adjacent to the channel layer and the barrier One interface; a drain electrode, a gate electrode, and a source electrode respectively on the barrier layer; a first region P-type semiconductor layer between the gate electrode and the barrier layer; and a The isolation region forms a layer around the barrier layer, and the channel layer under the isolation region formation layer does not have two-dimensional electron gas.

The present application further discloses a method for fabricating a semiconductor power device, comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer stack comprising: a channel layer; a barrier layer; and a P-type semiconductor layer Removing a portion of the P-type semiconductor layer to form a first region P-type semiconductor layer and a second region P-type semiconductor layer, wherein the second region P-type semiconductor layer is located around the barrier layer; forming a source a pole and a drain are on the barrier layer; and a gate is formed on the first region P-type semiconductor layer.

The implementation of the present invention is, for example, the same or similar parts as those shown in the drawings.

1A and 1B are diagrams showing a semiconductor power device 100 in an embodiment of the present application, and Fig. 1B is a cross-sectional view taken along line B-B' in Fig. 1A. The semiconductor power device 100 sequentially includes a substrate 10, a nucleation layer 20, a buffer structure 30, a channel layer 40, a barrier layer 50, a first region of the first conductivity type compound semiconductor layer 60a, and a second region. A first conductive type compound semiconductor layer 60b, a gate electrode G, a source electrode S and a drain electrode D in the region.

The material of the substrate 10 may be a semiconductor material or an oxide material, and the semiconductor material may include, for example, germanium (Si), gallium nitride (GaN), tantalum carbide (SiC), gallium arsenide (GaAs), or the like. The oxide material may, for example, comprise sapphire. In addition, when distinguished by conductivity, the substrate 10 itself may be a conductive substrate or an insulating substrate, and the conductive substrate includes a substrate of a bismuth (Si) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs). The above insulating substrate includes a substrate such as sapphire or silicon on insulator (SOI). In addition, the substrate 10 may selectively dope a substance therein to change its conductivity to form a conductive substrate or a non-conductive substrate. For a germanium (Si) substrate, the dopant may be boron (B) or arsenic. (As) or phosphorus (P). In the embodiment, the substrate 10 is a germanium substrate and has a thickness of about 1000 to 1200 um. The nucleation layer 20 is located above the substrate 10 and has a thickness of about several tens of nanometers or hundreds of nanometers to reduce the lattice difference between the substrate 10 and the barrier layer 50. The nucleation layer 20 is, for example, a tri-five material including materials such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN). The buffer structure 30 is located above the nucleation layer 20 and has a thickness of about several micrometers or tens of micrometers. The material of the buffer structure 30 can be a tri-five material, which is also used to reduce the lattice difference between the substrate 10 and the barrier layer 50, and reduce the crystal. Defects. In this embodiment, the buffer structure 30 may include a single layer structure or a multi-layer structure. When the buffer structure 30 is a multi-layer structure, the super-lattice laminate or the interaction of two or more layers may be included. Lamination. The material of the single-layer or multi-layer buffer structure 30 may include a group of three or five semiconductor materials, such as aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (AlGaN), and may be doped with other elements. For example, carbon (C) or iron (Fe) may be used, and the doping concentration may be gradual or fixed depending on the growth direction. In addition, when the buffer structure 30 is a superlattice laminate, it may be composed of two layers of epitaxial layers stacked with different materials, and the material may be a group of three or five semiconductor materials, for example, an aluminum nitride layer (AlN). It is formed by overlapping with an aluminum gallium nitride layer (AlGaN) or by overlapping a gallium nitride layer (GaN) and an indium gallium nitride layer (InGaN).

The channel layer 40 is formed on the buffer layer 30 and has a first energy gap. The barrier layer 50 is formed on the channel layer 40 and has a second energy gap. The second energy gap is higher than the first energy gap, and the barrier layer 50 has a smaller lattice constant than the channel layer 40. In this embodiment, the material of the channel layer 40 and the barrier layer 50 comprises aluminum indium gallium nitride (Al _x In _y Ga( _1-xy )N), where 0 ≦ x<1, 0 ≦ x + y ≦ 1 . In the present embodiment, the aluminum content of the barrier layer 50 may be between 0.1 and 0.3. The channel layer 40 and the barrier layer 50 themselves form spontaneous polarization, and the barrier layer 50 and the channel layer 40 are different from each other due to different lattice constants between the channel layer 40 and the layers in the lower epitaxial layer. The sum of the interactions forms a piezoelectric polarization to the upper barrier layer 50. The above two polarization phenomena affect the structure of the band of the two bands, causing the band to bend, and some of the bands are below the Fermi level. The electron can move two-dimensionally in the energy band under the Fermi level, and a two-dimensional electron gas (2DEG) is generated on the heterojunction between the channel layer 40 and the barrier layer 50, indicated by a broken line. In the picture). In this embodiment, the material of the channel layer 40 and the barrier layer 50 may be, for example, an intrinsic semiconductor without other elements, but other elements may be doped depending on the characteristics of the device. For example, the element cerium (Si) may be doped therein, and the concentration of the two-dimensional electron gas layer is adjusted by the doping element concentration.

Above the barrier layer 50, there is a first conductive type compound semiconductor layer 60, a first conductive type compound semiconductor layer 60a including a first region is located in a central region of the barrier layer 50, and a first conductive region of a second region The compound semiconductor layer 60b is located in a peripheral region of the barrier layer 50. The first conductive type compound semiconductor layers 60a and 60b of the first region and the second region are separated from each other, and the first conductive type compound semiconductor layer 60a of the first region is viewed from the upper side as a closed ring pattern.

The material of the first conductive type compound semiconductor layer 60 includes a p-type semiconductor material. In the present embodiment, the first conductive type compound semiconductor layer 60 is, for example, a p-type tri-five semiconductor such as a p-type gallium nitride layer (p-GaN). ). The function is to reduce the concentration of the two-dimensional electron gas 16 under the first conductive type compound semiconductor layer 60 or to dissipate the two-dimensional electron gas 16 under the first conductive type compound semiconductor layer 60, so that the semiconductor power device is not turned on in a state where the gate is not biased. Normally off. The first conductive type compound semiconductor layers 60a and 60b of the first region and the second region may have the same material characteristics, such as the same thickness, material composition, first conductive type dopant or first conductive type doping concentration. .

A gate electrode G is formed over the first conductive type compound semiconductor layer 60a of the first region, and the gate electrode G has a corresponding closed ring pattern with the first conductive type compound semiconductor layer 60a of the first region. The source electrode S and the drain electrode D are located above the barrier layer 50, the source electrode S is located in the gate electrode G of the closed loop pattern, and the drain electrode D is located on the side outside the gate electrode G of the closed loop pattern. In one embodiment, the distance between the drain electrode D and the gate electrode G is greater than the distance between the gate electrode G and the source electrode S. The first conductive type compound semiconductor layer 60b located in the second region around the barrier layer 50 simultaneously surrounds the gate electrode G, the source electrode S, and the drain electrode D. The material of the drain electrode D and the source electrode S may be selected from titanium (Ti) and aluminum (Al), and the material of the gate electrode G may be selected from nickel (Ni), gold (Au), tungsten (W), and nitride. Titanium (TiN), tungsten nitride (TiW), platinum (Pt), molybdenum (Mo), or a combination thereof.

2 to 5B illustrate a method of fabricating the semiconductor power device 100 disclosed in the present application.

Referring to Fig. 2, a semiconductor power device manufacturing method includes a wafer forming step. First, the nucleation layer 20, the buffer structure 30, the channel layer 40, the barrier layer 50, and the first conductivity type compound semiconductor layer 60 are sequentially grown on the substrate 10. The substrate 10 is, for example, a germanium substrate having a thickness of about 1000 to 1200 μm. The nucleation layer 20, the buffer structure 30, the channel layer 40, and the barrier layer 50 are epitaxially grown on the (111) surface of the substrate 10, and along the edge. [0001] The direction grows. The epitaxial method is, for example, metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). In other embodiments, a portion of the substrate 10 may be further removed to reduce leakage paths for the purpose of reducing leakage. For example, the substrate 10 is thinned relative to the surface of the semiconductor layer such as the nucleation layer 20; or after the substrate 10 is removed, the semiconductor layer such as the upper nucleation layer 20 is transposed and bonded to an insulating heat dissipation substrate; In an embodiment, after the substrate 10 is removed, the semiconductor layer having a higher epitaxial defect density can be further removed, for example, after the nucleation layer 20 and the buffer structure 30 are removed, and then transposed and bonded to the insulating heat dissipation substrate. Process.

Next, as shown in FIG. 3, the first conductive type compound semiconductor layer 60 is grown on the barrier layer 50 in the same manner as the epitaxial growth to obtain a wafer 1.

In the subsequent wafer forming step, the semiconductor power device manufacturing method includes a patterning step of the first conductive type compound semiconductor layer 60. As shown in FIGS. 4A and 4B, FIG. 4B is a cross-sectional view taken along line BB' of FIG. 4A, and the pattern of the first conductive type compound semiconductor layer 60 is defined by etching or the like, and the first portion of the removed portion is removed. The conductive compound semiconductor layer 60 forms the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region, and further utilizes the first conductive type compound semiconductor layer 60b of the second region. In the wafer 1, a plurality of active regions A1 and A2 are defined, and an element isolation region ISO is defined between the plurality of active regions A1 and A2, and the current is controlled within the respective active regions to form a subsequent Each of the semiconductor power components can operate independently without interference with each other.

In the upper view of FIG. 4A, the first conductive type compound semiconductor layer 60b of the second region is surrounded by the active regions A1 and A2 and located between the active regions A1 and A2, and is located in each of the active regions A1 and A2. Around the barrier layer 50, a lattice difference between the first conductive type compound semiconductor layer 60b of the second region and the barrier layer 50 is utilized to generate a reverse polarization effect, and the energy band is pulled up above the Fermi level. The two-dimensional electron gas 16 below the region is dissipated or the concentration is lowered to achieve the component isolation effect. The first conductive type compound semiconductor layer 60a of the first region is located in each of the active regions A1, A2, and has a closed ring shape in the upper view, and the first conductive type compound semiconductor layers 60b of the second region are separated from each other.

Following the patterning step of the first conductive type compound semiconductor layer 60, the semiconductor power device manufacturing method includes an electrode forming step. Fig. 5B is a cross-sectional view taken along line B-B' in Fig. 5A. As shown in FIGS. 5B and 5B, a drain electrode D and a source electrode S are respectively formed over the barrier layer 50, and a gate electrode G is formed over the first conductive type compound semiconductor layer 60a of the first region as An end point that is electrically connected to an external electronic component or an external power source. The gate electrode G and the first conductive type compound semiconductor layer 60a of the first region have a corresponding closed ring pattern in the upper view, and the source electrode S is located in the gate electrode G of the closed ring pattern, and the drain electrode The electrode D may be located on one side of the barrier layer outside the closed ring pattern. In this embodiment, the drain electrode D and the source electrode S and the barrier layer 50 may be selected by selecting appropriate materials of the drain electrode D and the source electrode S, and/or by a process (eg, thermal annealing). An ohmic contact is formed between them. Similarly, a Schottky contact or an ohmic contact can be formed between the gate electrode G and the first conductive type compound semiconductor layer 60a of the first region by selecting a material of the appropriate gate electrode G.

According to the semiconductor power device 100 formed by the manufacturing method of the present application, as shown in FIG. 5B, when the gate electrode G is not biased, the channel layer 40 under the first conductive type compound semiconductor layer 60a of the first region is formed. There is no two-dimensional electron gas 16 therein, and thus the semiconductor power device 100 is not turned on to assume a closed state. In addition, under the closed loop pattern of the first conductive type compound semiconductor layer 60a and the gate electrode G of the first region, the corresponding channel layer 40 does not have the two-dimensional electron gas 16 therein, thereby forming the germanium blocking region 18 to close the surrounding source. The electrode S has a current between the drain electrode D and the source electrode S so that the element can be surely turned off.

When a bias voltage is applied to the gate electrode G, as shown in FIG. 6, a two-dimensional electron gas 16 is formed in the channel layer under the first conductive type compound semiconductor layer 60a of the first region in each semiconductor power device 100, Therefore, each semiconductor power device 100 is turned on. And since the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region are separated from each other, that is, the first conductive type compound semiconductor layer 60a of the first region is isolated from the element. The area ISO has a pitch. Therefore, the two-dimensional electron gas 16 in the single semiconductor power device 100 is not affected by the surrounding element isolation region ISO, and the current can flow from the drain electrode D to the source electrode S; and in the element isolation region The two-dimensional electron gas 16 is not formed in the channel layer 40 of the ISO (i.e., the first conductive type compound semiconductor layer 60b of the second region), so that the elements can be electrically isolated from each other.

In an embodiment of the present application, the first conductive type compound semiconductor layer 60a of the first region under the gate electrode G and the first conductive type compound semiconductor layer 60b of the second region are formed in a manner of forming the first conductive After the compound semiconductor layer 60 is formed, the first conductive type compound semiconductor layer 60 is simultaneously etched, so that the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region can be The same characteristics, such as the same thickness, material composition, first conductivity type dopant or first conductivity type doping concentration. In addition, the semiconductor power device and the manufacturing method thereof disclosed in the present application are simplified in the process, and also have a process in which the device isolation region is formed by dry etching or ion implantation in a semiconductor layer. Lower production costs.

In another embodiment of the present application, after the semiconductor power device manufacturing method is completed, each of the semiconductor power devices 100 may be further divided along the first conductive type compound semiconductor layer 60b of the second region, for example, using a wheel cutter. Cutting or laser cutting to form individual semiconductor power devices 100 as shown in Figures 1A and 1B. In the divided semiconductor power device 100, there is no two-dimensional electron gas under the first conductive type compound semiconductor layer 60b in the second region, and the function of reducing the leakage current path is obtained. In one embodiment, the width of the first conductive type compound semiconductor layer 60b of the second region before the dicing is larger than the first conductive type compound semiconductor layer 60a of the first region; and the first conductive type compound semiconductor layer 60b of the second region The width is wide enough to allow the first conductive type compound semiconductor layer 60b of the second region to remain on the semiconductor power device after the first conductive type compound semiconductor layer 60b of the second region is removed in the dicing process The above functions.

In another embodiment of the present application, before forming the drain electrode D, the source electrode S, and the gate electrode G, a dielectric layer 32 may be formed on the upper surface of the barrier layer 50 as shown in FIG. on. A portion of the dielectric layer 32 is located below the gate electrode G and between the gate electrode G and the barrier layer 50, which can further reduce surface leakage current, and can improve the operating bias range of the gate electrode G, and improve the reliability of the component. degree. The dielectric layer 32 may be an oxide or a nitride, for example, an oxide such as ruthenium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride.

In another embodiment of the present application, after forming the drain electrode D, the source electrode S, and the gate electrode G, a protective layer (not shown) may be further formed to cover the dielectric layer 32 and the drain electrode. D, the surface of the source electrode S and the gate electrode G to prevent the electrical properties of the channel layer 40 from being affected. In this embodiment, the protective layer may be an oxide or a nitride, such as an oxide such as ruthenium oxide or aluminum oxide, or a nitride such as tantalum nitride or gallium nitride. Then, the protective layer is further etched to expose a part of the drain electrode D, the source electrode S and the gate electrode G, that is, the drain electrode D, the source electrode S and the gate electrode G may have a part of the surface unprotected layer Coverage to increase the convenience of electrical connection with the outside world.

8A to 8D are diagrams showing a semiconductor power device 200 in another embodiment of the present application, wherein FIG. 8B is a cross-sectional view taken along line BB′ in FIG. 8A, and FIG. 8C is a cross-sectional view along C-B in FIG. 8A. A cross-sectional view of the C' line segment, and Fig. 8D is a cross-sectional view taken along line D-D' in Fig. 8A.

The semiconductor power device 200 is similar to the semiconductor power device 100, and includes the substrate 10, the nucleation layer 20, the buffer structure 30, the channel layer 40, and the barrier layer 50, the first conductive type compound semiconductor layer 60a of the first region, and the second. The first conductive type compound semiconductor layer 60b, the gate electrode G, the source electrode S, and the drain electrode D in the region. Above the barrier layer 50, the first conductive type compound semiconductor layer 60a having the first region is located in the central region of the barrier layer 50, and the first conductive type compound semiconductor layer 60b of the second region is located around the barrier layer 50. The region, and the first conductive type compound semiconductor layers 60a and 60b of the first region and the second region are separated from each other. The materials, formation modes, and functions of the first conductive type compound semiconductor layers 60a and 60b of the first region and the second region are the same as those of the semiconductor power device 100 described above, and will not be described herein. Unlike the semiconductor power device 100, the first conductive type compound semiconductor layer 60a of the first region of the semiconductor power device 200 is viewed from a top view as a stripe pattern. Further, as shown in FIGS. 8C and 8D, in order to achieve the function of closing and isolating the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region by the semiconductor power device 200, In this embodiment, the first conductive type compound semiconductor layers 60a and 60b of the first region and the second region are electrically insulated by a recess 28 and an insulating layer 42 on the recess 28, which is a closed loop in the semiconductor power device 100. A variation of one of the first conductivity type compound semiconductor layers 60a. Between the two ends of the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region, a portion of the barrier layer 50 and the channel layer 40 are etched away to form the recess 28, The bottom surface of the recess 28 is a surface 401 that the channel layer 40 is etched to expose. The insulating layer 42 is formed on the bottom surface of the concave portion 28, the side wall, and a part of the upper surface of the first conductive type compound semiconductor layer 60.

The gate electrode G is disposed above the first conductive type compound semiconductor layer 60a of the first region, and has a strip pattern similar to that of the first conductive type compound semiconductor layer 60a of the first region. The gate electrode G is disposed along the first conductive type compound semiconductor layer 60a of the first region, and extends from both ends of the first conductive type compound semiconductor layer 60a of the first region to the insulating layer 42 in the recess 28. The source electrode S and the drain electrode D are respectively disposed on the barrier layer 50 and on both sides of the gate electrode G.

9A through 10 are schematic views showing operational states of a plurality of semiconductor power devices 200. As in the manufacturing process of the semiconductor power device described above, the state of each semiconductor power device 200, the component that does not bias the gate electrode G is as shown in FIGS. 9A to 9C, and the image of FIG. 9B is the B-B' in FIG. 9A. A cross-sectional view of the line segment, and Fig. 9C is a cross-sectional view taken along line C-C' in Fig. 9A. The channel layer 40 under the first conductive type compound semiconductor layer 60a of the first region does not have the two-dimensional electron gas 16 therein, and thus the semiconductor power device 200 is not turned on to assume a closed state. Further, as shown in FIG. 9C, in the recess 28 at both ends of the gate electrode G and the first conductive type compound semiconductor layer 60a of the first region, since the barrier layer 50 and a portion of the channel layer 40 have been removed by etching, Therefore, the two-dimensional electron gas 16 in the concave portion 28 cannot be formed and blocked, so that no current flows between the drain electrode D and the source electrode S, and the respective elements can be surely turned off.

When a bias voltage is applied to the gate electrode G, as shown in FIG. 10, a two-dimensional electron gas 16 is formed in the channel layer under the first conductive type compound semiconductor layer 60a of the first region in each semiconductor power device 200, Therefore, each of the semiconductor power elements 200 is turned on. On the other hand, in the channel layer 40 under the first conductive type compound semiconductor layer 60b in the second region, that is, the two-dimensional electron gas 16 is not formed in the element isolation region ISO, the elements can be electrically isolated. And because the first conductive type compound semiconductor layer 60a of the first region and the first conductive type compound semiconductor layer 60b of the second region are separated from each other, the two-dimensional electron gas 16 in the semiconductor power device 200 and the surrounding element isolation region ISO Without being affected by each other, the electrical characteristics of the individual semiconductor power components can be accurately measured on a single wafer.

However, the above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present application is as set forth in the scope of the patent application described below.

1‧‧‧ wafer

10‧‧‧Substrate

18‧‧‧Blocking area

20‧‧‧Nuclear layer

28‧‧‧ recess

30‧‧‧buffer structure

32‧‧‧Dielectric layer

40‧‧‧Channel layer

42‧‧‧Insulation

50‧‧‧Barrier layer

60‧‧‧First Conductive Compound Semiconductor Layer

60a‧‧‧First Conductive Compound Semiconductor Layer in the First Region

60b‧‧‧First Conductive Compound Semiconductor Layer in the Second Region

100,200‧‧‧Semiconductor power components

A1, A2‧‧‧ active area

S‧‧‧ source electrode

D‧‧‧汲electrode

G‧‧‧gate electrode

ISO‧‧‧ Component isolation area

[Figs. 1A to 1B] are semiconductor power elements disclosed in an embodiment of the present invention. [Fig. 2 to 5B] is a method of manufacturing a semiconductor power device disclosed in an embodiment of the present invention. [Fig. 6] is an operational state of a semiconductor power device disclosed in an embodiment of the present invention. [Fig. 7] A semiconductor power device disclosed in another embodiment of the present invention. [8A to 8D] is a semiconductor power device disclosed in another embodiment of the present invention. [9A to 9C] is an operational state of the semiconductor power device disclosed in another embodiment of the present invention. [Fig. 10] is an operational state of a semiconductor power device disclosed in another embodiment of the present invention.

Claims (11)

A semiconductor power device comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas located in the channel layer adjacent to the channel layer and the resistor One interface between the barrier layers; a drain electrode, a gate electrode, and a source electrode respectively on the barrier layer; a first region P-type semiconductor layer located at the gate electrode and the barrier layer And an isolation region forming layer located around the barrier layer, and the channel layer under the isolation layer forming layer does not have the two-dimensional electron gas. The semiconductor power device of claim 1, wherein the isolation region forming layer comprises a second region P-type semiconductor layer. A method for fabricating a semiconductor power device, comprising: providing a substrate; forming an epitaxial layer on the substrate, the epitaxial layer stack comprising: a channel layer; a barrier layer; and a P-type semiconductor layer; Removing a portion of the P-type semiconductor layer to form a first region P-type semiconductor layer and a second region P-type semiconductor layer, wherein the second region P-type semiconductor layer is located around the barrier layer; forming A source and a drain are on the barrier layer; and a gate is formed on the first region P-type semiconductor layer. The method of fabricating a semiconductor power device according to claim 3, wherein a two-dimensional electron gas is contained in the channel layer and adjacent to an interface between the channel layer and the barrier layer. The method of manufacturing a semiconductor power device according to claim 2, wherein the first region P-type semiconductor layer and the second region P-type semiconductor layer are separated from each other . The method of manufacturing a semiconductor power device according to claim 2, wherein the first region P-type semiconductor layer and the second region P-type semiconductor layer have the same Material properties. The method of manufacturing a semiconductor power device according to claim 2, wherein the first region P-type semiconductor layer and the second region P-type semiconductor layer have the same Material properties of thickness, same material, same conductivity type dopant or one of the same doping concentrations. The method of manufacturing a semiconductor power device according to claim 2, wherein the gate electrode is located between the source electrode and the drain electrode, and the method A gate electrode surrounds the source electrode. The method of manufacturing a semiconductor power device according to claim 2, wherein the channel layer and the barrier layer comprise an aluminum indium gallium nitride layer (Al _x). In _y Ga _(1-xy) N), where 0 ≦ x < 1, 0 ≦ x + y ≦ 1, and the energy gap of the barrier layer is greater than the energy gap of the channel layer. The method of manufacturing a semiconductor power device according to claim 1, wherein the second region P-type semiconductor layer surrounds the gate electrode in a top view, a gate electrode and the source electrode. The method of manufacturing a semiconductor power device according to claim 2, wherein the first region P-type semiconductor layer is a closed ring or strip in the upper view. shape.