CN108598154A - Enhanced gallium nitride transistor and preparation method thereof - Google Patents

Abstract

The invention discloses an enhanced gallium nitride transistor and a preparation method thereof. The transistor includes: a substrate, the substrate includes a source region and a drain region, and a gate region located between the source region and the drain region; a gallium nitride modulation gate is located in the gate region, and the gallium nitride modulation gate includes nitrogen doped with P-type ions Gallium nitride material; source and drain, the source is located in the source region, and the drain is located in the drain region; the gate metal layer is located on the surface of the gallium nitride modulation gate away from the substrate, and the gate metal layer includes at least a lanthanide metal layer , the lanthanide metal layer is in contact with the gallium nitride modulation gate. In the enhancement mode gallium nitride transistor provided by the embodiment of the present invention, a lanthanide metal layer is arranged on the side of the gallium nitride modulation gate away from the substrate, and the lanthanide metal layer is in contact with the gallium nitride modulation gate. When the gallium transistor is working, a higher voltage needs to be provided to turn on the channel between the source and the drain. Therefore, the gate threshold voltage of the enhancement mode gallium nitride transistor is increased and the gate leakage current is reduced.

Description

A kind of enhancement mode gallium nitride transistor and its preparation method

technical field

Embodiments of the present invention relate to the technical field of preparation of broadband power devices, and in particular to an enhancement mode gallium nitride transistor and a preparation method thereof.

Background technique

Gallium nitride is a semiconductor material with the characteristics of large band gap, high electron saturation drift velocity, high breakdown field strength and good thermal conductivity, and has become an important third-generation semiconductor material. In the field of electronic devices, compared with silicon materials, gallium nitride materials are more suitable for manufacturing high-temperature, high-frequency, high-voltage and high-power devices, and have good application prospects.

In order to obtain high-temperature, high-frequency, high-voltage and high-power gallium nitride devices, it is first necessary to prepare gallium nitride high electron mobility transistors (Gallium Nitride High Electron Mbility Transistors, GaN HEMT) with a higher gate threshold voltage. For traditional silicon material transistors, the gate turn-on voltage is often adjusted by adjusting the doping concentration of the substrate. But for the enhancement-mode gallium nitride transistor, the conductive channel is formed by the heterojunction to form a two-dimensional electron gas (Two-Dimensional Electron Gas, 2DEG), so the threshold voltage of the gate cannot be adjusted by doping.

In the prior art, there are two commonly used methods for increasing the gate threshold voltage of GaN transistors. One is to etch the gate trench to reduce the two-dimensional electron gas density in the conductive channel by reducing the thickness of the barrier layer, but this method will introduce additional etching damage, and this method can only reduce the gallium nitride The threshold voltage of the device is raised to around 1V.

Contents of the invention

The invention provides an enhanced gallium nitride transistor and a preparation method thereof, so as to increase the turn-on voltage of the enhanced gallium nitride transistor and reduce gate leakage current.

In a first aspect, an embodiment of the present invention provides an enhancement mode gallium nitride transistor, including:

a substrate comprising a source region and a drain region, and a gate region between the source region and the drain region;

a gallium nitride modulation gate located in the gate region, the gallium nitride modulation gate comprising a gallium nitride material doped with p-type ions;

a source and a drain, the source is located in the source region, and the drain is located in the drain region;

a gate metal layer located on the surface of the gallium nitride modulation gate away from the substrate, the gate metal layer at least includes a lanthanide metal layer, and the lanthanide metal layer is in contact with the gallium nitride modulation gate .

Further, the gate metal layer further includes a cap metal protection layer, and the cap metal protection layer is located on a side of the lanthanide metal layer away from the substrate.

Further, the material of the cap metal protection layer includes gold, silver, copper or titanium.

Further, the thickness of the lanthanide metal layer is greater than 5 nm.

Further, the thickness of the cap metal protection layer is greater than or equal to 40nm.

Further, the P-type ion doping concentration of the gallium nitride modulation gate is 1×10 ¹⁷ cm ^-3 -1×10 ¹⁹ cm ^-3 .

In the second aspect, the embodiment of the present invention also provides a method for manufacturing an enhancement mode gallium nitride transistor, the method comprising:

A P-type gallium nitride epitaxial wafer is provided, wherein the P-type gallium nitride epitaxial wafer includes a substrate and a gallium nitride modulation layer on the substrate, the substrate includes a plurality of transistor units, each of the transistors The unit includes a source region and a drain region, and a gate region located between the source region and the drain region, and the gallium nitride modulation layer includes a gallium nitride material doped with P-type ions;

Etching the gallium nitride modulation layer to form a gallium nitride modulation gate in the gate region;

Etching a part of the base of the adjacent region of the transistor unit to perform leakage isolation to define a plurality of enhancement mode gallium nitride transistors;

forming a source in the source region and forming a drain in the drain region;

A gate metal layer is formed on the surface of the gallium nitride modulation gate away from the substrate, the gate metal layer at least includes a lanthanide metal layer, and the lanthanide metal layer is in contact with the gallium nitride modulation gate .

Further, a gate metal layer is formed on the surface of the gallium nitride modulation gate far away from the substrate, including:

Depositing the lanthanide metal layer on the surface of the gallium nitride modulation grid far away from the substrate by magnetron sputtering;

A cap metal protection layer is deposited in-situ on the lanthanide metal layer.

Further, the material of the cap metal protection layer includes gold, silver, copper or titanium.

Further, the thickness of the lanthanide metal layer is greater than 5 nm.

In the enhancement mode gallium nitride transistor provided by the embodiment of the present invention, a lanthanide metal layer is arranged on the side of the gallium nitride modulation gate away from the substrate, and the lanthanide metal layer is in contact with the gallium nitride modulation gate. When the gallium transistor is working, a higher voltage needs to be provided to turn on the channel between the source and the drain. Therefore, the gate threshold voltage of the enhancement mode gallium nitride transistor is increased and the gate leakage current is reduced.

Description of drawings

FIG. 1 is a schematic structural diagram of an enhancement mode gallium nitride transistor provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of another enhancement mode gallium nitride transistor provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another enhancement mode gallium nitride transistor provided by an embodiment of the present invention;

4 is a schematic diagram of the threshold voltage of the gallium nitride control gate when the gate metal layer respectively includes metal lanthanum or metal nickel provided by an embodiment of the present invention;

5 is a schematic diagram of the gate leakage current when the gate metal layer respectively includes metal lanthanum or metal nickel provided by an embodiment of the present invention;

FIG. 6 is a flow chart of a method for fabricating an enhancement mode gallium nitride transistor according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a transistor corresponding to step 10 provided by the embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a transistor corresponding to step 20 provided by an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a transistor corresponding to step 30 provided by an embodiment of the present invention;

FIG. 10 is a schematic structural diagram of a transistor corresponding to step 40 provided by an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a transistor corresponding to step 50 provided by an embodiment of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

FIG. 1 is a schematic structural diagram of an enhancement mode gallium nitride transistor provided by an embodiment of the present invention. Optionally, please refer to FIG. 1, the enhancement mode gallium nitride transistor includes: a substrate 100, the substrate 100 includes a source region and a drain region, and a gate region located between the source region and the drain region; a gallium nitride modulation gate 101, Located in the gate area, the gallium nitride modulation gate 101 includes gallium nitride material doped with P-type ions; the source electrode 103 and the drain electrode 104, the source electrode 103 is located in the source area, and the drain electrode 104 is located in the drain area; the gate metal layer 102, Located on the surface of the GaN modulation gate 101 away from the substrate 100 , the gate metal layer 102 includes at least a lanthanide metal layer 112 , and the lanthanide metal layer 112 is in contact with the GaN modulation gate 101 .

Specifically, when the value of the work function of the semiconductor material is different from the value of the Fermi level of the metal material, the contact between the two will form a gold half-contact barrier, and the value of the work function of the semiconductor material is different from the Fermi level of the metal material. The greater the difference in the values of the energy levels, the greater the gold half-contact potential barrier formed. The gallium nitride modulation gate 101 is a semiconductor material, and the gate metal layer 102 is a metal material. Generally speaking, the work function of the gallium nitride modulation gate 101 is different from the Fermi level of the gate metal layer 102. Therefore, the gallium nitride The contact between the modulation gate 101 and the gate metal layer 102 will generate a gold half-contact barrier. Moreover, when other conditions (including the doping concentration of the GaN modulation gate 101 ) are determined, the larger the gold half-contact barrier, the higher the gate threshold voltage of the enhancement GaN transistor.

For the enhancement mode gallium nitride transistor, when the actual voltage applied to the gate metal layer 102 is greater than the threshold voltage, the channel between the source 103 and the drain 104 is turned on, and the transistor can start to work. For the enhancement mode GaN transistor, when the gate metal layer 102 in contact with the GaN modulation gate 101 is a lanthanide metal material, a higher threshold voltage of the enhancement mode GaN transistor can be formed. This is because, compared with other metal materials, the work function of the lanthanide metal is smaller, usually only about 3.5eV, therefore, the contact between the lanthanide metal layer 112 and the GaN modulation gate 101 can form a higher gold half-contact potential barrier, and a higher gate threshold voltage. Therefore, when the enhancement mode GaN transistor is working, a higher voltage needs to be applied to the GaN modulation gate 101 to make the channel between the source 103 and the drain 104 conduct. Since the threshold voltage of the enhancement-mode gallium nitride transistor increases, a larger voltage needs to be applied to the gallium nitride modulation gate 101 when the transistor is working, which makes it more difficult for carriers in the channel to enter the gate metal layer 102, Thus, gate leakage current can be reduced.

In the enhancement mode gallium nitride transistor provided in this embodiment, a lanthanide metal layer is arranged on the side of the gallium nitride modulation gate away from the substrate, and the lanthanide metal layer is in contact with the gallium nitride modulation gate. When the transistor is working, a higher voltage needs to be provided to turn on the channel between the source and the drain. Therefore, the gate threshold voltage of the enhancement-mode gallium nitride transistor is increased and the gate leakage current is reduced.

FIG. 2 is a schematic structural diagram of another enhancement mode gallium nitride transistor provided by an embodiment of the present invention. Optionally, please refer to FIG. 1 and FIG. 2, the substrate 100 of the enhancement mode gallium nitride transistor may include a barrier layer 105, a channel layer 106 and a substrate layer 107; wherein, the barrier layer 105 is located between the channel layer 106 and the nitrogen Between GaN modulation gates 101. The material of the barrier layer 105 may be AlGaN, and the material of the channel layer 106 may be GaN. The contact between the barrier layer 105 and the channel layer 106 can form a heterojunction structure, and a two-dimensional electron gas is formed on the side of the contact surface of the barrier layer 105 and the channel layer 106 close to the channel layer 106, and the two-dimensional electron gas is equivalent to In the conduction channel of the enhancement mode gallium nitride transistor, electrons in the two-dimensional electron gas form a current when they move directionally between the source 103 and the drain 104 of the transistor. Due to the existence of the gallium nitride modulation gate 101, the two-dimensional electron gas at the corresponding position of the gallium nitride modulation gate 101 will be exhausted to form a normally-off transistor, wherein the corresponding position means that the gallium nitride modulation gate 101 is on the substrate 100 The position where the projection in the direction coincides with the projection of the two-dimensional electron gas in the direction of the substrate 100 .

FIG. 3 is a schematic structural diagram of another enhancement mode gallium nitride transistor provided by an embodiment of the present invention. Optionally, referring to FIG. 3 , the substrate layer 107 may further include a substrate 137 , a nucleation layer 127 and a buffer layer 117 stacked in sequence, wherein the buffer layer 117 is located between the channel layer 106 and the nucleation layer 127 . The substrate 137 may be a silicon substrate. Since the lattice structure of the silicon substrate is different from that of gallium nitride, in order to ensure the lattice quality of the channel layer 106, the nucleation layer 127 and buffer layer 127 may be successively grown on the substrate 137. layer 117, the lattice matching degree of the channel layer 106 and the buffer layer 117 is much higher than the lattice matching degree of the channel layer 106 and the silicon substrate, therefore, growing the channel layer 106 on the buffer layer 117 can improve the channel The lattice growth quality of layer 106 ensures the formation of two-dimensional electron gas. Optionally, both the buffer layer 117 and the nucleation layer 127 may be GaN material, wherein the buffer layer 117 is a crystalline GaN structure.

Optionally, please continue to refer to FIG. 2 , the gate metal layer 102 further includes a cap metal protection layer 122 , and the cap metal protection layer 122 is located on a side of the lanthanide metal layer 112 away from the substrate 100 . Specifically, the cap metal protection layer 122 can be used to protect the lanthanide metal layer 112 . The lanthanide metal layer 112 is easily oxidized, and a cap metal protection layer 122 is provided on the side of the lanthanide metal layer 112 away from the substrate 100 to protect the lanthanide metal layer 112 and prevent the lanthanide metal layer from being oxidized.

Optionally, the material of the cap metal protection layer 122 includes gold, silver, copper or titanium. Specifically, the cap metal protection layer 122 is a part of the gate metal layer 102 and needs to have good electrical conductivity. Therefore, materials such as gold, silver, copper, or titanium can be selected. It should be noted that the cap metal protection layer 122 provided in this embodiment includes but not limited to gold, silver, copper or titanium materials.

Optionally, the thickness of the lanthanide metal layer 112 is greater than 5 nm. Specifically, if the thickness of the lanthanide metal layer 112 is too small, the lanthanide metal layer 112 cannot play a good role in raising the threshold voltage. For example, if the thickness of the lanthanide metal layer 112 is 1 nm, the corresponding lanthanide The thickness of the metal layer 112 is only a few lanthanum atoms. Therefore, the free electrons in the cap metal protection layer 122 can easily pass through the metal layer 112 to interact with the gallium nitride modulation gate 101, which is equivalent to a part of the cap layer. The metal protection layer 122 is in contact with the GaN modulation gate 101, resulting in lowering of the threshold voltage of the transistor. Considering the structure of the transistor in practical applications, the thickness of the lanthanide metal layer 122 is usually not greater than 50nm; but it should be noted that in practical applications, the thickness of the lanthanide metal layer 122 can be set as required, and this embodiment does not make specific limit.

Optionally, the cap metal protection layer 122 has a thickness greater than or equal to 40 nm. Specifically, on the one hand, the capping metal protection layer 122 is a part of the gate metal layer 102, and needs to have good electrical conductivity, so an appropriate thickness needs to be set; on the other hand, the capping metal protection layer 122 is used to protect the lanthanum The metal series metal layer 112 is not oxidized, therefore, the capping metal protection layer 122 needs to be able to fully cover the lanthanide metal layer 112, and therefore, the thickness of the capping metal protection layer 122 cannot be too small. It should be noted that, in practical applications, the thickness of the cap protection metal layer 122 can be set according to needs, which is not specifically limited in this embodiment.

Exemplarily, the gate metal layer 102 may have a La/Ti structure, that is, the lanthanide metal layer 112 is metal lanthanum, the cap metal protection layer 122 is metal titanium, and the thickness of the metal lanthanum can be 20 nm, and the metal titanium The thickness is 100nm. The lanthanide metal layer 112 with a thickness of 20nm is in contact with the GaN modulation gate 101, which can form a gold half-contact well, and the relatively thin lanthanide metal layer 112 can also reduce the manufacturing cost. Compared with gold or silver, the cost of metal titanium is lower, and it is more suitable to prepare the cap metal protective layer 122 by magnetron sputtering. The thickness of 100nm can make the cap metal protective layer 122 better protect the lanthanide metal layer 112 from It is oxidized and has good electrical conductivity.

Optionally, the P-type ion doping concentration of the gallium nitride modulation gate 101 is 1×10 ¹⁷ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ . Specifically, in order to make the GaN modulation gate 101 deplete the two-dimensional electron gas corresponding to the GaN modulation gate 101 and form a normally-off enhancement mode GaN transistor, the GaN modulation gate 101 needs to have A sufficient number of holes, so the GaN modulation gate 101 needs to have a higher doping concentration. If the doping concentration of the GaN modulation gate 101 is too low, the two-dimensional electron gas at the corresponding position cannot be depleted. However, if the doping concentration of the GaN modulation gate 101 is too high, on the one hand, impurity atoms will destroy the lattice structure of the GaN modulation gate 101, destroy the two-dimensional electron gas structure, and reduce the high-frequency characteristics of the enhancement mode GaN transistor; On the other hand, too high doping concentration will also cause the lanthanide metal layer 112 and the gallium nitride modulation layer 101 to change from a gold half-contact to an ohmic contact, and the lanthanide metal layer 112 and the gallium nitride modulation layer 101 cannot generate voltage. drop, at the detriment of raising the threshold voltage.

Optionally, both the source electrode 103 and/or the drain electrode 104 can have a Ti/Al/Ti/Au structure, wherein the Ti layer is in contact with the substrate 100, and the Au layer is away from the substrate 100; and, in the Ti/Al/Ti/Au structure , the thickness of each layer is 20nm, 110nm, 40nm and 50nm in turn. Optionally, the source 103 and the drain 104 may also have other structures, which are not specifically limited in this embodiment.

Optionally, the intrinsic GaN material generally has the characteristics of an N-type semiconductor, and in order to convert the GaN modulation gate 101 into a P-type, divalent elements need to be doped. For example, you can choose to dope magnesium, because the atomic radius of magnesium is smaller than that of gallium, the doping process is relatively easy to complete, and magnesium nitride is also a wide bandgap semiconductor material, doping magnesium is beneficial to maintain the nitride Gallium's wide bandgap properties. It should be noted that, when forming the P-type GaN modulation gate 101 , other doping elements can also be selected, which is not specifically limited in this embodiment.

4 is a schematic diagram of the threshold voltage of the gallium nitride control gate when the gate metal layer respectively includes metal lanthanum or metal nickel provided by the embodiment of the present invention. FIG. Schematic diagram of gate leakage current for nickel metal. Optionally, please refer to FIG. 1, FIG. 4 and FIG. 5. In order to ensure the reliability of the test results, when metal nickel is formed on the side of the gallium nitride modulation gate 101 away from the substrate 100, the preparation process of the metal nickel is the same as that of the lanthanide metal. The preparation process of layer 112 is the same. Analysis of test results shows that when the lanthanide metal layer 112 is replaced by metal nickel, the threshold voltage of the enhancement-mode GaN transistor is significantly reduced; at the same time, when the same voltage is applied to the enhancement-mode GaN transistor, the lanthanide The gate leakage current of the transistor of the metal layer 112 is smaller than that of the transistor including the metal nickel. It can be seen that using the gate metal layer 102 including the lanthanide metal layer 112 to form a gold half-contact with the GaN modulation gate 101 can increase the threshold voltage of the enhancement-mode GaN transistor and reduce the leakage current of the enhancement-mode GaN transistor .

This embodiment also provides a method for manufacturing an enhancement-mode gallium nitride transistor. Fig. 6 is a flow chart of a method for manufacturing an enhancement-mode gallium nitride transistor provided in an embodiment of the present invention, and the method specifically includes:

Step 10, providing a P-type GaN epitaxial wafer, wherein the P-type GaN epitaxial wafer includes a substrate and a GaN modulation layer on the substrate, the substrate includes a plurality of transistor units, and each transistor unit includes a source region and a The drain region, and the gate region located between the source region and the drain region, the gallium nitride modulation layer includes gallium nitride material doped with P-type ions.

FIG. 7 is a schematic structural diagram of a transistor corresponding to step 10 provided by an embodiment of the present invention. Optionally, referring to FIG. 7 , the GaN modulation layer 111 is used to form a GaN modulation gate in a subsequent process, and the substrate 100 can define a plurality of transistor units after a subsequent etching process. It should be noted that when forming the gallium nitride modulation layer 111 on the substrate 100, various preparation processes may be used, which are not specifically limited in this embodiment.

Step 20, etching the GaN modulation layer to form a GaN modulation gate in the gate area.

FIG. 8 is a schematic structural diagram of a transistor corresponding to step 20 provided by an embodiment of the present invention. Optionally, please refer to FIG. 8 , after an etching process, a plurality of GaN modulation gates 101 may be formed on one side of the substrate 100 .

Step 30 , etching a part of the base of the adjacent area of the transistor unit for leakage isolation, and defining a plurality of enhancement mode gallium nitride transistors.

FIG. 9 is a schematic structural diagram of a transistor corresponding to step 30 provided by the embodiment of the present invention. Optionally, please refer to FIG. 9 , by etching the substrate 100 , a plurality of transistors can be defined, each transistor includes a GaN modulation gate 101 , and the number of transistors is the same as the number of GaN modulation gates 101 .

Step 40 , forming a source in the source region and forming a drain in the drain region.

FIG. 10 is a schematic structural diagram of a transistor corresponding to step 40 provided by the embodiment of the present invention. Optionally, referring to FIG. 10 , the source 103 and the drain 104 are respectively located on two sides of the GaN modulation gate 101 . When forming the source electrode 103 and the drain electrode 104, firstly, the photoresist is coated on the surface of the substrate 100 near the source electrode and the drain electrode, the photoresist is patterned, and the source region and the drain region are formed by electron beam evaporation. The source electrode 103 and the drain electrode 104 are deposited and formed respectively. The source 103 and drain 104 can be of the same or different compositions. Exemplarily, if the photoresist is patterned using a double-layer adhesive stripping process, a double-layer stripping photoresist coated on the side of the substrate close to the source electrode 103 and the drain electrode 104 can be used at a speed of 4000 rpm. . It should be noted that this embodiment does not specifically limit the method of forming the source electrode 103 and the drain electrode 104 , and methods such as patterning photoresist.

Optionally, after the source 103 and the drain 104 are formed, the enhancement mode gallium nitride transistor may be subjected to rapid annealing, the annealing temperature is 850° C., and the annealing time is 45s. The rapid annealing treatment helps the source 103 and the drain 104 to form better ohmic contact with the substrate 100 .

Step 50 , forming a gate metal layer on the surface of the GaN modulation gate away from the substrate, the gate metal layer at least includes a lanthanide metal layer, and the lanthanide metal layer is in contact with the GaN modulation gate.

FIG. 11 is a schematic structural diagram of a transistor corresponding to step 50 provided by an embodiment of the present invention. Optionally, referring to FIG. 11 , when forming the gate metal layer 102 , it is necessary to first deposit a lanthanide metal layer 112 on the surface of the gallium nitride modulation gate 101 away from the substrate 100 , and then form a metal layer 112 on the lanthanide metal layer 112 A layer of protective structure.

Optionally, forming a gate metal layer on the surface of the gallium nitride modulation gate far away from the substrate includes: depositing a lanthanide metal layer on the surface of the gallium nitride modulation gate far from the substrate by using magnetron sputtering; A cap metal protection layer is deposited in-situ on the metal layer. Specifically, before depositing the lanthanide metal layer and the cap metal protection layer, it is necessary to coat the photoresist on the side of the gallium nitride modulation gate away from the substrate, and the photoresist can be coated and patterned with the same The same process steps in step 40 may also be performed in different processes. After patterning the photoresist, the transistor with the photoresist pattern is placed in the vacuum chamber of the magnetron sputtering equipment, and the lanthanide metal layer is deposited by the magnetron sputtering method; after the deposition of the lanthanide metal layer is completed, keep The position of the transistor in the vacuum chamber remains unchanged, and other metal targets are used to form a cap metal protection layer on the lanthanide metal layer by adjusting the target position. Since the in-situ deposition method is used to deposit the cap metal protective layer, it can ensure that the cap metal protective layer accurately covers the lanthanide metal layer, thereby ensuring the quality of the gate metal layer.

It should be noted that when forming the lanthanide metal layer and cap metal protective layer by sputtering, an alignment process needs to be adopted. In order to ensure the accuracy of the alignment, it is necessary to keep the gallium nitride modulation gate Photoresist exists on the side away from the substrate. Therefore, in this embodiment, the dimensions of the lanthanide metal layer and the capping metal protection layer in the extending direction of the substrate are both smaller than the dimension of the gallium nitride control gate in the extending direction of the substrate. In order to improve the properties of the transistor, before magnetron sputtering, the thickness of the photoresist after patterning should be reduced as much as possible, so that the lanthanide metal layer and the cap metal protective layer are as far as possible in the direction of extension of the substrate. The size is close to the size of the gallium nitride control gate in the extending direction of the substrate. It can be understood that, in an ideal state, the dimensions of the lanthanide metal layer and the cap metal protective layer in the direction of extension of the substrate should be infinitely close to the dimension of the gallium nitride control gate in the direction of extension of the substrate.

Optionally, after the preparation of the enhancement mode gallium nitride transistor is completed, a probe station can also be used to conduct an electrical test on the sample.

Optionally, the material of the cap metal protection layer includes gold, silver, copper or titanium. Specifically, gold, silver, copper or titanium are all good conductor materials, which can meet the conductive requirements of the gate metal layer, and can protect the lanthanide metal layer from oxidation. It should be noted that the cap metal protection layer provided in this embodiment includes but is not limited to gold, silver, copper or titanium materials.

Optionally, the thickness of the lanthanide metal layer is greater than 5 nm. Specifically, in order to significantly increase the threshold voltage, the thickness of the lanthanide metal layer cannot be too small.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the appended claims.

Claims (10)

1. a kind of enhancement type gallium nitride transistor, which is characterized in that including：

Substrate, the substrate include source region and drain region, and the grid region between the source region and the drain region；

Gallium nitride intensity grid is located at the grid region, and the gallium nitride intensity grid includes the gallium nitride material of doped p-type ion；

Source electrode and drain electrode, the source electrode are located at the source region, and the drain electrode is located at the drain region；

Gate metal layer is located on the surface far from the substrate of the gallium nitride intensity grid, and the gate metal layer is at least Including lanthanide series metal layer, the lanthanide series metal layer is contacted with the gallium nitride intensity grid.

2. enhancement type gallium nitride transistor according to claim 1, which is characterized in that the gate metal layer further includes cap Layer coat of metal, the cap layers coat of metal are located at the side of the lanthanide series metal layer far from the substrate.

3. enhancement type gallium nitride transistor according to claim 2, which is characterized in that the material of the cap layers coat of metal Material includes gold, silver, copper or titanium.

4. enhancement type gallium nitride transistor according to claim 1, which is characterized in that the thickness of the lanthanide series metal layer is big In 5nm.

5. enhancement type gallium nitride transistor according to claim 2, which is characterized in that the thickness of the cap layers coat of metal Degree is greater than or equal to 40nm.

6. enhancement type gallium nitride transistor according to claim 1, which is characterized in that the p-type of the gallium nitride intensity grid Ion doping a concentration of 1 × 10¹⁷cm^-3-1×10¹⁹cm^-3。

7. a kind of preparation method of enhancement type gallium nitride transistor, which is characterized in that including：

There is provided p-type gallium nitride epitaxial slice, wherein the p-type gallium nitride epitaxial slice includes substrate and on the substrate Gallium nitride modulating layer, the substrate include multiple transistor units, and each transistor unit includes source region and drain region, and Grid region between the source region and the drain region, the gallium nitride modulating layer include the gallium nitride material of doped p-type ion；

The gallium nitride modulating layer is etched, gallium nitride intensity grid is formed in the grid region；

The part of substrate for etching the transistor unit adjacent area is limited multiple described enhanced with carrying out electric leakage isolation Gallium nitride transistor；

It forms source electrode in the source region and is formed in the drain region and drain；

Gate metal layer is formed on the surface far from the substrate of the gallium nitride intensity grid, the gate metal layer is at least Including lanthanide series metal layer, the lanthanide series metal layer is contacted with the gallium nitride intensity grid.

8. the preparation method of enhancement type gallium nitride transistor according to claim 7, which is characterized in that in the gallium nitride Gate metal layer is formed on the surface far from the substrate of intensity grid, including：

The lanthanide series metal layer is deposited on the surface far from the substrate of the gallium nitride intensity grid using magnetron sputtering method；

The in-situ deposition cap layers coat of metal on the lanthanide series metal layer.

9. the preparation method of enhancement type gallium nitride transistor according to claim 8, which is characterized in that the cap layers metal The material of protective layer includes gold, silver, copper or titanium.

10. the preparation method of enhancement type gallium nitride transistor according to claim 7, which is characterized in that the group of the lanthanides gold The thickness for belonging to layer is more than 5nm.