[go: up one dir, main page]

TWI634686B - Hydrophobic bank - Google Patents

Hydrophobic bank Download PDF

Info

Publication number
TWI634686B
TWI634686B TW103128177A TW103128177A TWI634686B TW I634686 B TWI634686 B TW I634686B TW 103128177 A TW103128177 A TW 103128177A TW 103128177 A TW103128177 A TW 103128177A TW I634686 B TWI634686 B TW I634686B
Authority
TW
Taiwan
Prior art keywords
layer
bank
region
solution
photoresist
Prior art date
Application number
TW103128177A
Other languages
Chinese (zh)
Other versions
TW201513427A (en
Inventor
強納森 埃塞克
蓋瑞 威廉斯
丹尼爾 弗塞斯
李歐 班柏
Original Assignee
劍橋顯示科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 劍橋顯示科技有限公司 filed Critical 劍橋顯示科技有限公司
Publication of TW201513427A publication Critical patent/TW201513427A/en
Application granted granted Critical
Publication of TWI634686B publication Critical patent/TWI634686B/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/122Pixel-defining structures or layers, e.g. banks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/10OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/18Carrier blocking layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H01L21/0212Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)

Abstract

本發明揭示一種製作具有包括界定井之側壁之電絕緣堤部結構之電子裝置的方法,該方法包括:形成該堤部結構,使得該側壁包括自表面層區域延伸之第一斜面及自該第一斜面延伸之第二較陡峭斜面,該側壁具有在該第二斜面上與該第一斜面間隔開之點處之表面能量不連續性;藉由在該井中沈積有機半導電性材料之溶液來形成具有包括該材料之至少一個層之層結構,其中該經沈積溶液潤濕該第一斜面及該第二斜面直至該表面能量不連續性處之釘紮點;及乾燥該經沈積溶液。 The invention discloses a method for fabricating an electronic device having an electrically insulating bank structure including a sidewall defining a well, the method comprising: forming the bank structure such that the sidewall includes a first inclined surface extending from a surface layer region and from the first A second steeper slope extending from an inclined surface, the side wall having a discontinuity in surface energy at a point where the second inclined surface is spaced from the first inclined surface; by depositing a solution of an organic semiconductive material in the well Forming a layer structure having at least one layer including the material, wherein the deposited solution wets the first bevel and the second bevel to a pinning point at the surface energy discontinuity; and drying the deposited solution.

Description

疏水性堤部 Hydrophobic bank

本發明大體而言係關於製作包括具有表面層及該表面層上之界定井之堤部結構之基板之電子裝置的方法,以及包括具有表面層及該表面層上之界定井之堤部結構之基板之電子裝置。 The present invention generally relates to a method for fabricating an electronic device including a substrate having a surface layer and a bank structure defining a well on the surface layer, and a method including a bank structure having a surface layer and defining a well on the surface layer. Electronic device of substrate.

已對用於製造電子裝置之涉及自溶液沈積活性組分(溶液處理)之方法進行了廣泛研究。若活性組分係自溶液沈積,則該等活性組分較佳地含於基板之所要區中。此可藉由提供包括界定可在其中自溶液沈積活性組分之井之經圖案化堤部層之基板來達成。該等井在溶液變乾燥時含納該溶液,使得活性組分保持在基板之由該等井界定之區中。 Extensive research has been conducted on methods for manufacturing electronic devices involving deposition of active components from solution (solution treatment). If the active components are deposited from a solution, they are preferably contained in a desired region of the substrate. This can be achieved by providing a substrate including a patterned bank layer defining a well in which an active component can be deposited from a solution. The wells contain the solution as the solution becomes dry, so that the active component remains in the area of the substrate defined by the wells.

已發現此等方法對自溶液沈積有機材料尤其有用。該等有機材料可係導電的、半導電的及/或光電活性的,使得其可在有電流通過時發射光或藉由當光照射在其上時產生電流來偵測光。利用此等材料之裝置被稱為有機電子裝置。若有機材料係發光材料,則該裝置被稱為有機發光裝置(OLED)。此外,溶液處理允許薄膜電晶體(TFT)且特定而言有機薄膜電晶體(OTFT)之低成本、低溫製造。在此等裝置中,尤其期望在合宜區且尤其該裝置之通道內含納有機半導體(OSC),且可提供界定井以便含納OSC之堤部。 These methods have been found to be particularly useful for depositing organic materials from solution. The organic materials may be conductive, semi-conductive, and / or photoactive, such that they can emit light when a current is passed or detect light by generating a current when the light is irradiated thereon. Devices using these materials are called organic electronic devices. If the organic material is a light emitting material, the device is referred to as an organic light emitting device (OLED). In addition, solution processing allows low-cost, low-temperature manufacturing of thin-film transistors (TFTs), and particularly organic thin-film transistors (OTFTs). In such devices, it is particularly desirable to include organic semiconductors (OSCs) in the expedient area, and in particular, the channels of the devices, and banks can be provided that define wells to contain the OSCs.

某些裝置可需要多於單個經溶液沈積層。典型OLED(諸如,在顯示器中所使用的)可具有兩個有機半導體材料層,其中一者可係諸 如發光聚合物(LEP)之發光材料層,且另一者可係諸如聚噻吩衍生物或聚苯胺衍生物之電洞輸送材料層。 Some devices may require more than a single solution-deposited layer. A typical OLED, such as that used in displays, may have two layers of organic semiconductor materials, one of which may be A light emitting material layer such as a light emitting polymer (LEP), and the other may be a hole transporting material layer such as a polythiophene derivative or a polyaniline derivative.

有利的簡單堤部結構具有經設計以又含有所有此等經沈積液體之單個材料/層。然而,對於具有用於所有經沈積液體之單個堤部材料及單個釘紮點之裝置,在經溶液沈積層之任一側上之電極之間存在電洩漏路徑或短路電路風險。舉例而言,在包括陽極-HIL-IL-EL-陰極結構之OLED結構中,洩漏電流可經由HIL之邊界上之洩漏路徑在陽極與陰極之間流動。類似地,洩漏路徑可由陰極與堤部上之電洞注入層(HIL)直接接觸、堤部上之極薄裝置堆疊或釘紮點處之點接觸所致使。經完全印刷裝置之JV(電流密度-電壓)曲線可(舉例而言)在被反向驅動時及/或在接通之前展示高洩漏(強電流)。在具有經旋塗中間層(IL)及電致發光層(EL)之情況下,洩漏要低得多的,此乃因HIL被頂部上之經旋塗膜完全覆蓋。可導致低得多的效率。 An advantageous simple bank structure has a single material / layer that is designed to again contain all such deposited liquids. However, for devices with a single bank material and a single pinning point for all deposited liquids, there is a risk of electrical leakage paths or short circuits between the electrodes on either side of the solution deposited layer. For example, in an OLED structure including an anode-HIL-IL-EL-cathode structure, a leakage current may flow between the anode and the cathode via a leakage path on the boundary of the HIL. Similarly, the leak path can be caused by the cathode in direct contact with the hole injection layer (HIL) on the bank, the point where the very thin device stacks on the bank or the pinned points. The JV (current density-voltage) curve of a fully printed device can, for example, exhibit high leakage (high current) when driven in reverse and / or before switching on. With the spin-coated intermediate layer (IL) and the electroluminescent layer (EL), the leakage is much lower because the HIL is completely covered by the spin-coated film on top. Can lead to much lower efficiency.

目前,低洩漏裝置通常需要雙重堤部系統,以分離陽極釘紮點與陰極。然而,與雙重堤部架構相比,單個堤部可減小複雜性。另外或另一選擇係,藉助光微影經圖案化之單個堤部可提供用於像素(堤部)界定之價廉方法。然而,此堤部可使陽極區曝光於烴(抗蝕劑殘餘物)及/或提供用於所有經溶液處理層(HIL、IL及EL)之單個流體釘紮點。已展示,高導電HIL加上陽極(ITO)表面與HIL-IL-EL-陰極重合釘紮點之間之短路路徑長度將會造成高洩漏裝置。 Currently, low-leakage devices often require a dual bank system to separate the anode pinning point from the cathode. However, a single bank can reduce complexity compared to a dual bank structure. Additionally or alternatively, a single bank patterned by means of light lithography can provide an inexpensive method for pixel (bank) definition. However, this bank can expose the anode region to hydrocarbons (resist residues) and / or provide a single fluid pinning point for all solution-treated layers (HIL, IL, and EL). It has been shown that a highly conductive HIL plus a short circuit path length between the anode (ITO) surface and the HIL-IL-EL-cathode pinning point will result in a high leakage device.

類似地,具有堤部結構之發光裝置可具有跨越作用區之不良色彩均勻性及/或發光效率。 Similarly, a light emitting device having a bank structure may have poor color uniformity and / or luminous efficiency across the active area.

因此,需要提供一種允許不同液體含納於井內之經改良結構及/或一種用於製作此結構之製程。該經改良結構可具有諸如以下各項中之任一或多者之優點:尤其,跨越該裝置之經改良色彩均勻性、較低及/或可調諧電洩漏、跨越裝置之作用區之經增加總功率效率及/或效 率均勻性、(例如,OLED發射之)經改良使用壽命穩定性(較佳地,舉例而言,在使用壽命測試時較穩定及/或較可重複性裝置照度)、較緊湊裝置,以及經減小結構複雜性及/或經由較少處理步驟進行製作之能力(其中任一者皆可導致裝置製造之經改良時間或成本效率、經改良裝置良率、可重複性、可(舉例而言)導致成本降低之關於對組成材料之體積及/或數目之經減小要求)。 Therefore, there is a need to provide an improved structure that allows different liquids to be contained in a well and / or a process for making such a structure. The improved structure may have advantages such as any one or more of the following: inter alia, improved color uniformity across the device, lower and / or tunable electrical leakage, increased coverage across the device's active area Total power efficiency and / or efficiency Rate uniformity, (e.g., OLED emission), improved lifetime stability (preferably, for example, more stable and / or more repeatable device illumination during lifetime testing), more compact devices, and The ability to reduce structural complexity and / or make it with fewer processing steps (any of which can lead to improved time or cost efficiency in device manufacturing, improved device yield, repeatability, can (for example ) Reduced requirements on the volume and / or number of constituent materials that result in reduced costs).

參考以下揭示內容以供在理解本發明中使用:- US 8,063,551(杜邦公司(Du Pont));- US2006/197086(三星電子有限公司(Samsung Electronics Co Ltd.));- US2010/271353(索尼公司(Sony Corp));- WO2009042792(發明人Tsai Yaw-Ming A等人);- US2007/085475(半導體能源實驗室(Semiconductor Energy Lab));- US7799407(精工愛普生公司(Seiko Epson Corp));- US7604864(大日本網屏製造公司(Dainippon Screen MFG));- WO9948339(精工愛普生公司);- JP2007095425A(精工愛普生公司);- WO 2009/077738(PCT/GB2008/004135,於2009年6月25日公開,發明人係Burroughes及Dowling);及- WO2011/070316 A2(PCT/GB2010/002235,於2011年6月16日公開,發明人係Crankshaw及Dowling)。 Reference is made to the following disclosure for use in understanding the present invention:-US 8,063,551 (Du Pont);-US2006 / 197086 (Samsung Electronics Co Ltd.);-US2010 / 271353 (Sony Corporation (Sony Corp));-WO2009042792 (Inventor Tsai Yaw-Ming A et al.);-US2007 / 085475 (Semiconductor Energy Lab);-US7799407 (Seiko Epson Corp);- US7604864 (Dainippon Screen MFG);-WO9948339 (Seiko Epson Corporation);-JP2007095425A (Seiko Epson Corporation);-WO 2009/077738 (PCT / GB2008 / 004135, June 25, 2009 Disclosed, the inventors are Burroughes and Dowling); and-WO2011 / 070316 A2 (PCT / GB2010 / 002235, published on June 16, 2011, the inventors are Crankshaw and Dowling).

本發明係關於一種製作具有包括界定井之側壁之電絕緣堤部結構之電子裝置的方法,該方法包括:形成該堤部結構,使得該側壁包括自表面層區域延伸之第一斜面及自該第一斜面延伸之第二較陡峭斜 面,該側壁具有在該第二斜面上與該第一斜面間隔開之點處之表面能量不連續性;藉由在該井中沈積有機半導電性材料之溶液來形成具有包括該材料之至少一個層之層結構,其中該經沈積溶液潤濕該第一斜面及該第二斜面直至該表面能量不連續性處之釘紮點;及乾燥該經沈積溶液。 The invention relates to a method for manufacturing an electronic device having an electrically insulating bank structure including a sidewall defining a well, the method comprising: forming the bank structure such that the sidewall includes a first inclined surface extending from a surface layer region and Second steeper slope extending from first slope Surface, the side wall has a discontinuity in surface energy at a point spaced from the second slope to the first slope; forming at least one material including the material by depositing a solution of an organic semiconductive material in the well The layer structure of the layer, wherein the deposited solution wets the first inclined surface and the second inclined surface to a pinning point at the surface energy discontinuity; and the deposited solution is dried.

根據本發明之第一態樣,提供一種製作包括具有表面層及該表面層上之界定井之堤部結構之基板之電子裝置的方法,該堤部結構包括電絕緣材料且具有圍繞該表面層之一區域以藉此界定該井之側壁,該表面層區域包括第一電極,且該裝置進一步包括第二電極及安置於該第一電極與該第二電極之間之半導電性材料,該方法包括:形成具有包括自該表面層區域延伸之第一斜面及自該第一斜面延伸之第二斜面之該側壁之該堤部結構,其中該第二斜面比該第一斜面陡峭,其中該側壁具有在該第二斜面上與該第一斜面間隔開之點處之表面能量不連續性;形成具有至少一個層之層結構,該層結構安置於該第一電極與該第二電極之間且具有該半導電性材料,其中該形成該層結構包括:在該表面層區域上及該側壁之該第一斜面及該第二斜面上沈積有機溶液以形成可溶液處理之該層,其中該經沈積有機溶液潤濕該第一斜面及該第二斜面直至該表面能量不連續性處之釘紮點;及乾燥該經沈積有機溶液。 According to a first aspect of the present invention, there is provided a method for fabricating an electronic device including a substrate having a surface layer and a bank portion structure defining a well on the surface layer, the bank portion structure including an electrically insulating material and having a surface layer surrounding the surface layer. An area to thereby define the sidewall of the well, the surface layer area including the first electrode, and the device further including a second electrode and a semi-conductive material disposed between the first electrode and the second electrode, the The method includes: forming the bank structure having the side wall including a first inclined surface extending from the surface layer region and a second inclined surface extending from the first inclined surface, wherein the second inclined surface is steeper than the first inclined surface, wherein the The side wall has a discontinuity in surface energy at a point spaced apart from the first slope; the layer structure having at least one layer is disposed between the first electrode and the second electrode And having the semi-conductive material, wherein forming the layer structure includes: depositing an organic solution on the surface layer region and the first inclined surface and the second inclined surface of the sidewall to form a This layer of processing liquid, wherein the organic solution was deposited wets the first inclined surface and the second inclined surface until the staple of the discontinuity of the surface energy of tie points; and drying the deposited organic solution.

因此,實施例可提供用於至少一個可溶液處理層之釘紮點(較佳地,複數個可溶液處理層全部釘紮在相同點處),使得該釘紮點藉由藉助沿著其全長具有不同斜度而與直線背離之路徑與表面層區域分離。此可減小(若干)經溶液沈積層之任一側上之電極(例如,陽極與陰極)之間之漏電路徑或短路電路之風險。舉例而言,在包括陽極-HIL-IL-EL-陰極結構之OLED結構中,延長陽極與陰極之間沿著較佳地高阻性HIL之邊界之任何洩漏路徑。經延長路徑較佳地具有足夠高的阻 力以防止洩漏,否則,該洩漏可使(例如)效率、可靠性及/或使用壽命、色彩變化等顯著地降級。 Therefore, embodiments may provide a pinning point for at least one solution-treatable layer (preferably, the plurality of solution-treatable layers are all pinned at the same point), so that the pinning point is provided by Paths with different slopes that deviate from the straight line are separated from the surface layer region. This can reduce the risk of leakage paths or short circuits between electrodes (eg, anode and cathode) on either side of the solution-deposited layer. For example, in an OLED structure including an anode-HIL-IL-EL-cathode structure, any leakage path between the anode and the cathode along the boundary of a preferably high-resistance HIL is extended. The extended path preferably has a sufficiently high resistance Efforts to prevent leaks that could significantly degrade, for example, efficiency, reliability and / or service life, color variations, and the like.

更具體地考量所得之裝置結構,應注意較佳地藉由造成潤濕(例如,親水性)區域與未潤濕(例如,疏水性)區域之間之邊界之(若干)製程步驟來形成表面能量不連續性。此邊界較佳地在該第二斜面之頂部處。該第二斜面之頂部較佳地毗鄰該堤部結構之相對平坦表面,該平坦表面與該表面層對置且平行。無論如何,表面能量不連續性較佳地遠離該第一斜面且因此遠離該表面層區域。 Considering the resulting device structure more specifically, it should be noted that the surface is preferably formed by the (several) process steps that create the boundary between the wet (e.g., hydrophilic) area and the non-wet (e.g., hydrophobic) area. Energy discontinuities. This boundary is preferably at the top of the second bevel. The top of the second inclined surface is preferably adjacent to a relatively flat surface of the bank structure, and the flat surface is opposite to and parallel to the surface layer. In any case, the surface energy discontinuity is preferably far away from the first bevel and thus away from the surface layer region.

該方法可包括:在該可溶液處理層上方沈積至少另一溶液(例如,EL(發光層)及/或IL(中間層)),其中該至少另一溶液潤濕直至該釘紮點;及乾燥該經沈積至少另一溶液。因此,複數個此等可溶液處理層可具有相同釘紮點。 The method may include: depositing at least another solution (eg, EL (light emitting layer) and / or IL (intermediate layer)) over the solution-treatable layer, wherein the at least another solution is wetted to the pinning point; and Dry the deposited at least another solution. Therefore, a plurality of these solution-treatable layers may have the same pinning point.

可進一步提供該方法,其中該形成該堤部結構包括:形成包括該基板之該表面層上之光阻劑之第一堤部層;光圖案化並顯影該第一堤部層以曝光該表面層之該區域;將氟化光阻劑溶液沈積至該第一堤部層及該表面層之經曝光區域上以形成第二堤部層;進行烘烤以使該第二堤部層變硬,其中該氟化光阻劑溶液之含氟化合物在該烘烤期間遷移至該第二堤部層之表面以增加該有機溶液與該表面之接觸角;及光圖案化並顯影該第二堤部層以重新曝光該表面層之該區域及曝光該第一堤部層之區域,使得該第一堤部層區域具有該第一斜面且該第二堤部層具有該第二斜面,其中經增加接觸角高於該有機溶液與該第一斜面及該第二斜面之接觸角,且該釘紮點係在具有經遷移含氟化合物之該第二堤部層表面之邊界處。該等化合物在該烘烤期間遷移至之表面通常可被稱作「自由表面」,亦即,與外部環境(例如,空氣)介接。如在使用此氟化光阻劑之任何實施例中,該光阻劑可係由光阻劑製造商進行氟化而供應,或該製程可具有將含氟化合物添加至非氟化 光阻劑之額外步驟。無論如何,在該第二堤部層已變硬之後,該第二堤部層較佳地包括比該第一堤部層高之含氟化合物濃度。此外,在該第二堤部層已經顯影以移除該第二堤部層之部分之後,先前係「自由表面」之部分之部分較佳地具有與藉由該移除曝光之該第二堤部層之邊緣之潤濕/未潤濕邊界,此邊緣係該側壁之部分。因此,除雙重傾斜側壁之外,亦可形成釘紮點。 The method may be further provided, wherein the forming the bank structure includes: forming a first bank layer including a photoresist on the surface layer of the substrate; light patterning and developing the first bank layer to expose the surface Depositing the fluorinated photoresist solution on the exposed area of the first bank layer and the surface layer to form a second bank layer; baking to harden the second bank layer Wherein the fluorine-containing compound of the fluorinated photoresist solution migrates to the surface of the second bank layer during the baking to increase the contact angle between the organic solution and the surface; and photo-patterning and developing the second bank Layer to re-expose the area of the surface layer and the area of the first bank layer, so that the first bank layer area has the first slope and the second bank layer has the second slope, wherein The increased contact angle is higher than the contact angle of the organic solution with the first inclined surface and the second inclined surface, and the pinning point is at the boundary of the surface of the second bank layer layer with the migrated fluorine-containing compound. The surface to which these compounds migrate during this baking may generally be referred to as a "free surface", that is, interfacing with the external environment (eg, air). As in any embodiment using the fluorinated photoresist, the photoresist may be supplied by a photoresist manufacturer for fluorination, or the process may have the addition of a fluorinated compound to a non-fluorinated compound. Photoresist Extra Step. In any case, after the second bank layer has hardened, the second bank layer preferably includes a higher fluorine-containing compound concentration than the first bank layer. In addition, after the second bank layer has been developed to remove a portion of the second bank layer, a portion of the portion that was previously a "free surface" preferably has the second bank exposed by the removal. Wetting / unwetting boundary of the edge of the sublayer, this edge being part of the side wall. Therefore, in addition to the double inclined sidewalls, pinning points can also be formed.

可進一步提供該方法,其中該形成該堤部結構可包括:藉由在該表面層上沈積氟化光阻劑溶液來形成堤部結構層,且乾燥該經沈積溶液以使該堤部結構層變硬,其中該氟化光阻劑溶液之含氟化合物在該烘烤期間遷移至該堤部結構層之表面以增加該有機溶液與該表面之接觸角;在該堤部結構層上沈積並乾燥光阻劑層,且光圖案化並顯影該光阻劑層;乾式蝕刻步驟,其用以蝕刻該堤部結構層穿過該經顯影光阻劑層以曝光該表面層區域,使得該經蝕刻堤部結構層具有圍繞該經曝光表面層區域之該側壁且包括該第一斜面及該第二斜面;及移除該經顯影光阻劑層以曝光該堤部結構層之表面,該經曝光表面包括該經遷移含氟化合物,其中該表面能量不連續性係在包括該經遷移含氟化合物之該經曝光表面與該經蝕刻側壁之間的界面處。該乾式蝕刻步驟可包括較佳地使用氧氣電漿之反應性離子蝕刻。與上文類似地,先前係該堤部層之「自由表面」之部分之部分較佳地具有與藉由移除該堤部層之部分之顯影曝光之該堤部層之邊緣的潤濕/未潤濕邊界,此邊緣係該側壁之部分。因此,除雙重傾斜側壁之外,亦可形成釘紮點。 The method may be further provided, wherein forming the bank structure may include forming a bank structure layer by depositing a fluorinated photoresist solution on the surface layer, and drying the deposited solution to make the bank structure layer Hardening, wherein the fluorinated compound of the fluorinated photoresist solution migrates to the surface of the bank structure layer during the baking to increase the contact angle between the organic solution and the surface; and deposits on the bank structure layer and The photoresist layer is dried, and the photoresist layer is patterned and developed. A dry etching step is used to etch the bank structure layer through the developed photoresist layer to expose the surface layer area, so that the process Etching the bank structure layer has the side wall surrounding the exposed surface layer region and includes the first and second slopes; and removing the developed photoresist layer to expose the surface of the bank structure layer, the process The exposed surface includes the migrated fluorine-containing compound, wherein the surface energy discontinuity is at an interface between the exposed surface including the migrated fluorine-containing compound and the etched sidewall. The dry etching step may include reactive ion etching, preferably using an oxygen plasma. Similar to the above, the portion that was previously the "free surface" portion of the bank layer preferably has a wetting / edge of the bank layer that is exposed by development of the portion of the bank layer removed Unwet boundary, this edge is part of the side wall. Therefore, in addition to the double inclined sidewalls, pinning points can also be formed.

可仍進一步提供該方法,其中該形成該堤部結構可包括:顯影及光圖案化該堤部結構層以曝光由該堤部結構層之側壁圍繞之該表面層區域,其中該在該堤部結構層上沈積該光阻劑層包括在該經光圖案化堤部結構層上沈積光阻劑溶液,且該顯影該光阻劑層包括重新曝光 該表面層區域,且用以曝光該表面層區域之該乾式蝕刻步驟藉由薄化該堤部結構層以藉此形成該第一斜面及該第二斜面而使該經曝光區域延伸。 The method may be further provided, wherein the forming the bank structure may include developing and photo-patterning the bank structure layer to expose a surface layer region surrounded by a sidewall of the bank structure layer, wherein the at the bank portion Depositing the photoresist layer on the structure layer includes depositing a photoresist solution on the photopatterned bank structure layer, and developing the photoresist layer includes re-exposing The surface layer region, and the dry etching step for exposing the surface layer region extends the exposed region by thinning the bank structure layer to thereby form the first inclined surface and the second inclined surface.

可進一步提供該方法,其中:該光圖案化該光阻劑層可包括穿過具有實質上非透射性區域、部分透射性區域及實質上完全透射性區域(至少具有比該部分透射性區域大之透射率)之遮罩輻射該光阻劑層;且該顯影該光阻劑層包括完全移除光阻劑之區域且部分地移除穿過該部分透射性區域曝光於輻射之光阻劑區域。 The method may be further provided, wherein the photo-patterning the photoresist layer may include passing through a region having substantially non-transmittance, a partially transmissive region, and a substantially fully transmissive region (at least having a size greater than the partially transmissive region) The photoresist layer is radiated by a mask of (transmittance); and developing the photoresist layer includes completely removing the photoresist area and partially removing the photoresist that is exposed to the radiation through the partially transmissive area. region.

可又進一步提供該方法,其中該形成該堤部結構包括:藉由在該表面層上沈積氟化光阻劑溶液來形成堤部層;進行烘烤以使該堤部層變硬,其中該光阻劑溶液之氟化合物在該烘烤期間遷移至該堤部層之表面以藉此增加該有機溶液與該表面之接觸角;光圖案化該變硬堤部層,該光圖案化包括以第一輻射劑量輻射該堤部層之第一區域以及以第二輻射劑量輻射該堤部層之第二區域,該第二輻射劑量小於該第一輻射劑量;顯影該堤部層以曝光該表面層之該區域並部分地移除藉助該第二輻射劑量輻射之該堤部層之區域,該部分移除藉此提供圍繞該經曝光區域且具有第一斜面及第二斜面之側壁,其中該釘紮點係在具有該等經遷移含氟化合物之該堤部層表面與該側壁之間的邊界處。該第一區域可在該表面區域上方或在將保留之該堤部結構之部分上方,此取決於是使用負型光阻劑還是使用正型光阻劑。該部分移除較佳地薄化延伸至該表面層之一區域的該堤部層之區域,以給出沿著該側壁且因此沿著待沈積於井中之可溶液處理層之邊緣之較長路徑長度之托架結構。 The method may be further provided, wherein the forming the bank structure comprises: forming a bank layer by depositing a fluorinated photoresist solution on the surface layer; and baking to harden the bank layer, wherein The fluorine compound of the photoresist solution migrates to the surface of the bank layer during the baking to thereby increase the contact angle between the organic solution and the surface; the light patterning of the hardened bank layer includes: A first radiation dose irradiates a first area of the bank layer and a second radiation dose irradiates a second area of the bank layer, the second radiation dose is less than the first radiation dose; developing the bank layer to expose the surface The area of the layer and partially removes the area of the bank layer irradiated by the second radiation dose, the partial removal thereby providing a sidewall surrounding the exposed area and having a first slope and a second slope, wherein the The pinning point is at the boundary between the surface of the bank layer and the sidewall with the migrated fluorine-containing compounds. The first region may be above the surface region or above a portion of the bank structure to be retained, depending on whether a negative photoresist or a positive photoresist is used. The portion removes the area of the bank layer that preferably thins to an area of the surface layer to give a longer length along the side wall and therefore along the edge of the solution-treatable layer to be deposited in the well. Path length bracket structure.

可進一步提供該方法,其中:該光圖案化包括同時穿過第一遮罩及第二遮罩輻射該堤部層,其中該以該第一劑量輻射該第一區域包括穿過該第一遮罩及該第二遮罩之完全透射性區域輻射該第一區域, 且該以該第二劑量輻射該第二區域包括穿過該第一遮罩及該第二遮罩中之每一者之至少部分透射性區域輻射該第二區域。該至少部分透射性區域可包括該第一遮罩之完全透射性區域及/或該第二遮罩之部分透射性區域。此等區域中之至少一者較佳地係具有透射梯度之部分透射性區域。 The method may be further provided, wherein the light patterning includes radiating the bank layer through a first mask and a second mask simultaneously, wherein irradiating the first region with the first dose includes passing through the first mask The fully transmissive region of the mask and the second mask radiates the first region, And, irradiating the second region with the second dose includes radiating the second region through at least a portion of a transmissive region of each of the first mask and the second mask. The at least partially transmissive region may include a fully transmissive region of the first mask and / or a partially transmissive region of the second mask. At least one of these regions is preferably a partially transmissive region with a transmission gradient.

可進一步提供該方法,其中:該光圖案化包括穿過具有部分透射性區及更具(較佳地,完全)透射性區之遮罩輻射該堤部層,其中該以該第一劑量輻射該第一區域包括穿過該更具透射性區輻射該第一區域,且該以該第二劑量輻射該第二區域包括穿過該部分透射性區輻射該第二區域。 The method may be further provided, wherein: the light patterning includes radiating the bank layer through a mask having a partially transmissive region and more (preferably, completely) a transmissive region, wherein the radiation is emitted at the first dose The first region includes radiating the first region through the more transmissive region, and the radiating the second region at the second dose includes radiating the second region through the partially transmissive region.

可又進一步提供該方法,其包括在該表面層之區上沈積反射體層,其中:該沈積該氟化光阻劑溶液將該氟化溶液沈積於該反射體層上及該表面層上;及該光圖案化包括穿過遮罩輻射該堤部層,其中該輻射該第一區域包括該第一區域吸收直接穿過該遮罩接收之該第一劑量之一部分且吸收自該第一遮罩接收並藉由該反射體層反射回至該第一區域中之劑量之一部分。 The method may be further provided, comprising depositing a reflector layer on a region of the surface layer, wherein: depositing the fluorinated photoresist solution, depositing the fluorinated solution on the reflector layer and the surface layer; and the Light patterning includes radiating the bank layer through a mask, wherein the first region of the radiation includes the first region absorbing a portion of the first dose received directly through the mask and receiving from the first mask. A part of the dose in the first region is reflected back by the reflector layer.

可進一步提供該方法,其中該電子裝置係光電子裝置,諸如發光裝置或吸光裝置,較佳地係諸如有機光伏打裝置(OPV;例如,太陽能電池)之吸光裝置或諸如有機發光二極體(OLED)之發光裝置。另一選擇係,該裝置係薄膜電晶體。 The method may be further provided, wherein the electronic device is an optoelectronic device such as a light emitting device or a light absorbing device, preferably a light absorbing device such as an organic photovoltaic device (OPV; for example, a solar cell) or an organic light emitting diode (OLED) ) 的 luminescent device. Alternatively, the device is a thin film transistor.

可又進一步提供該方法,其中該電子裝置係有機發光二極體且該有機溶液係用於提供電洞注入層(HIL)。此外,可在該可溶液處理層上及在該第一電極與該第二電極之間形成至少另一可溶液處理層,該(等)另一可溶液處理層用於分別地提供中間層(IL)及/或發光層(EL)。 The method may be further provided, wherein the electronic device is an organic light emitting diode and the organic solution is used to provide a hole injection layer (HIL). In addition, at least another solution-treatable layer may be formed on the solution-treatable layer and between the first electrode and the second electrode, and the other solution-treatable layer is used to separately provide an intermediate layer ( IL) and / or light emitting layer (EL).

可進一步提供該方法,其中該有機溶液在沈積於該第一斜面及 自該第一斜面延伸至該釘紮點之第二斜面區域中之至少一者上時之接觸角係10°或更小。此接觸角通常允許表面之良好潤濕。 The method may be further provided, wherein the organic solution is deposited on the first inclined surface and The contact angle when extending from the first inclined plane to at least one of the second inclined plane regions of the pinning point is 10 ° or less. This contact angle usually allows good wetting of the surface.

可進一步提供該方法,其中該有機溶液在沈積於自該釘紮點延伸遠離該第一斜面的該堤部結構之一區域上時之接觸角係50°或更大。此接觸角通常不允許表面之良好潤濕,亦即,未潤濕。 The method may be further provided, wherein the contact angle of the organic solution when deposited on an area of the bank structure extending away from the first slope from the pinning point is 50 ° or greater. This contact angle generally does not allow good wetting of the surface, that is, non-wetting.

根據本發明之第二態樣,提供一種電子裝置,其包括具有表面層及該表面層上之界定井之堤部結構之基板,該堤部結構包括電絕緣材料且具有圍繞該表面層之一區域以藉此界定該井之側壁,該表面層區域包括第一電極,且該裝置進一步包括第二電極及安置於該第一電極與該第二電極之間的半導電性材料,其中:該側壁具有自該表面層區域延伸之第一斜面及自該第一斜面延伸之第二斜面,其中該第二斜面比該第一斜面陡峭;以及該裝置包括具有至少一個層之層結構,至少一個該層係可溶液處理層,該層結構具有該半導電性材料且安置於該第一電極與該第二電極之間,其中:至少一個該可溶液處理層具有在該第二斜面上與該第一斜面間隔開之點處之釘紮點,該可溶液處理層安置於該表面層區域上及該側壁之該第一斜面及該第二斜面上。 According to a second aspect of the present invention, there is provided an electronic device including a substrate having a surface layer and a bank portion structure defining a well on the surface layer, the bank portion structure including an electrically insulating material and having one of the surface layers surrounding the surface layer. A region to thereby define a sidewall of the well, the surface layer region including a first electrode, and the device further including a second electrode and a semi-conductive material disposed between the first electrode and the second electrode, wherein: the The side wall has a first inclined surface extending from the surface layer region and a second inclined surface extending from the first inclined surface, wherein the second inclined surface is steeper than the first inclined surface; and the device includes a layer structure having at least one layer, at least one The layer is a solution-treatable layer, the layer structure has the semi-conductive material and is disposed between the first electrode and the second electrode, wherein: at least one of the solution-treatable layer has The pinning points at the points where the first inclined plane is spaced apart, the solution-treatable layer is disposed on the surface layer region and the first inclined plane and the second inclined plane of the side wall.

因此,且與第一態樣類似地,實施例可提供用於(若干)可溶液處理層之釘紮點,該釘紮點藉由藉助沿著其全長具有不同斜度而與直線背離之路徑與表面層區域分離。此又可減小(若干)經溶液沈積層之任一側上之電極(例如,陽極與陰極)之間之漏電路徑或短路電路之風險。舉例而言,該陽極與該陰極之間沿著OLED之較佳地高阻性HIL之邊界之任何洩漏路徑較佳地經延長以具有足夠高的阻力以防止洩漏,否則,該洩漏可使(例如)效率、可靠性及/或使用壽命、色彩變化等顯著地降級。 Therefore, and similar to the first aspect, the embodiment may provide a pinning point for the (several) solution-treatable layer, the pinning point deviating from a straight line by having a different slope along its entire length Separate from the surface layer area. This in turn can reduce the risk of leakage paths or short circuits between electrodes (eg, anode and cathode) on either side of the solution-deposited layer. For example, any leakage path between the anode and the cathode along the boundary of the OLED's preferably high-resistance HIL is preferably extended to have a sufficiently high resistance to prevent leakage, otherwise, the leakage may ( For example) the efficiency, reliability and / or service life, color change, etc. are significantly degraded.

更具體地考量該裝置結構,應注意該表面層可包括電極(例如,陽極)及/或部分反射性層中之一者。對於底部發射裝置實施例,該表 面層(例如,氧化錫,諸如氧化銦錫(ITO))及基板(玻璃)較佳地係至少部分透明的。該表面層之單獨子層(例如,銀層)可提供上文述及之部分反射性層,該部分反射性層可經配置以形成可具有足夠小之尺寸以允許導致來自發光裝置之較窄發射光譜之可見量子效應之光學腔,或具體而言,微腔。對於包括此(例如,Ag)反射性層之裝置,該裝置之製作可包括:毯覆式Ag(合金)沈積;毯覆式ITO沈積;圖案化ITO以形成至少一個電極;堤部旋塗;及然後堤部圖案化。另一選擇係,該表面層之電極層可進一步起作用為此部分反射性層。 Considering the device structure more specifically, it should be noted that the surface layer may include one of an electrode (eg, an anode) and / or a partially reflective layer. For the bottom emission device embodiment, the table The surface layer (eg, tin oxide, such as indium tin oxide (ITO)) and the substrate (glass) are preferably at least partially transparent. A separate sub-layer (e.g., a silver layer) of the surface layer may provide a partially reflective layer as described above, which may be configured to form a size that may be sufficiently small to allow narrower results from the light emitting device Optical cavity with visible quantum effects in the emission spectrum, or in particular, a microcavity. For a device including this (eg, Ag) reflective layer, the fabrication of the device may include: blanket Ag (alloy) deposition; blanket ITO deposition; patterning ITO to form at least one electrode; spin coating of the bank; And then the bank is patterned. Alternatively, the electrode layer of the surface layer can further function as a partially reflective layer.

可進一步提供該電子裝置,其中當用於形成安置於該表面層區域上之該可溶液處理層之溶液沈積於該第一斜面及自該第一斜面延伸至該釘紮定之第二斜面之區域中之至少一者上時,該溶液之接觸角係10°或更小。另外或另一選擇係,當用於形成安置於該表面層區域上之該可溶液處理層之溶液沈積於該堤部結構之自該釘紮點延伸遠離該第一斜面之表面區域上時,該溶液之接觸角係50°或更大。因此,此溶液可具有10°或更小及50°或更大兩者之接觸角。 The electronic device may be further provided, wherein when a solution for forming the solution-treatable layer disposed on the surface layer region is deposited on the first inclined plane and an area extending from the first inclined plane to the pinned second inclined plane When at least one of them is on, the contact angle of the solution is 10 ° or less. Additionally or alternatively, when a solution for forming the solution-treatable layer disposed on the surface layer region is deposited on a surface region of the bank structure extending from the pinning point away from the first inclined plane, The contact angle of the solution is 50 ° or more. Therefore, this solution may have a contact angle of both 10 ° or less and 50 ° or more.

可進一步提供該電子裝置,其中該堤部結構包括至少一個光阻劑層。 The electronic device may be further provided, wherein the bank structure includes at least one photoresist layer.

可進一步提供該電子裝置,其中該光阻劑層具有該第二斜面上之該點且包括含氟化合物。 The electronic device may be further provided, wherein the photoresist layer has the point on the second slope and includes a fluorine-containing compound.

可進一步提供該電子裝置,其中該堤部結構包括複數個光阻劑層,該光阻劑層具有該第一斜面。 The electronic device may be further provided, wherein the bank structure includes a plurality of photoresist layers, and the photoresist layer has the first inclined surface.

可又進一步提供該電子裝置,其中該堤部結構包括具有含氟化合物之該光阻劑層以及該第一斜面及該第二斜面。 The electronic device may be further provided, wherein the bank structure includes the photoresist layer having a fluorine-containing compound and the first inclined surface and the second inclined surface.

可進一步提供該電子裝置,其中該第一斜面具有相對於該表面層之小於或等於20度(更佳地,小於5度、10度或15度)之斜面角。此角度可係沿著第一斜面及/或具體而言在該第一斜面與該表面層相接 之情況下之平均。 The electronic device may be further provided, wherein the first inclined surface has an inclined angle of less than or equal to 20 degrees (more preferably, less than 5, 10, or 15 degrees) with respect to the surface layer. This angle may be along the first inclined plane and / or specifically the first inclined plane is in contact with the surface layer. The average of the cases.

可進一步提供該電子裝置,其中該第一斜面延伸直至在與該第二斜面之邊界處小於300nm、較佳地小於200nm之堤部結構厚度(其中厚度係相對於該表面層之高度差),較佳地其中該第一斜面及該第二斜面中之至少一者沿著100nm至150nm之堤部結構厚度延伸(因此,由該第一斜面及/或該第二斜面橫越之高度較佳地在100nm至150nm之範圍內;在多個層形成該堤部結構且具有各別斜面之情況下,至少一個(例如)該第一斜面較佳地橫越100nm至150nm之高度)。 The electronic device may be further provided, wherein the first inclined surface extends up to a thickness of the bank structure at a boundary with the second inclined surface of less than 300 nm, preferably less than 200 nm (where the thickness is a height difference from the surface layer), Preferably, at least one of the first inclined surface and the second inclined surface extends along the thickness of the bank structure from 100 nm to 150 nm (therefore, the height traversed by the first inclined surface and / or the second inclined surface is better The ground is in the range of 100 nm to 150 nm; in the case where the bank structure is formed by a plurality of layers and each has an inclined surface, at least one (for example, the first inclined surface preferably crosses a height of 100 nm to 150 nm).

可仍進一步提供該電子裝置,其中該側壁自該表面區域延伸以提供至少300nm、較佳地至少1μm之堤部結構厚度。因此,該表面層上面之該側壁之最大高度較佳地係至少300nm。在實施例中,該最大高度有利地係足夠厚的以耐受乾式蝕刻步驟,例如RIE。 The electronic device may still be further provided, wherein the sidewall extends from the surface area to provide a bank structure thickness of at least 300 nm, preferably at least 1 μm. Therefore, the maximum height of the sidewall above the surface layer is preferably at least 300 nm. In an embodiment, this maximum height is advantageously thick enough to withstand dry etching steps, such as RIE.

可又進一步提供該電子裝置,其中該第一斜面沿著該表面層延伸跨過至少1μm之長度,較佳地其中該第二斜面沿著該表面層延伸跨過至少8μm之長度,較佳地其中該側壁(至少該第一斜面及該第二斜面)沿著該表面層延伸跨過至少10μm之長度。 The electronic device may be further provided, wherein the first inclined surface extends along the surface layer over a length of at least 1 μm, preferably the second inclined surface extends along the surface layer over a length of at least 8 μm, preferably The side wall (at least the first inclined surface and the second inclined surface) extends along the surface layer to a length of at least 10 μm.

可進一步提供該電子裝置,其中該裝置係發光裝置,且其中該可溶液處理層包括用於提供電洞注入層(HIL)之有機半導電性材料,較佳地其中該發光裝置係OLED。此外,至少一個該可溶液處理層可包括安置於用於提供該HIL之該材料上方之另一有機半導電性材料,其中該另一有機半導電性材料係用於提供中間層(IL)或發光層(EL)。 The electronic device may be further provided, wherein the device is a light emitting device, and wherein the solution-processable layer includes an organic semiconductive material for providing a hole injection layer (HIL), and preferably the light emitting device is an OLED. In addition, at least one of the solution-treatable layers may include another organic semi-conductive material disposed above the material for providing the HIL, wherein the other organic semi-conductive material is used to provide an intermediate layer (IL) or Light emitting layer (EL).

在該電子裝置係諸如OLED之發光裝置時,較佳地該第一電極層及該第二電極層中之一者(其中之任一者,亦即,第一電極層或第二電極層;若係堤部發射體裝置,則較佳地係第二電極層)係光透射性的(若係堤部發射體裝置,則較佳地該基板亦係透射性的)。此裝置較佳地包括經安置(例如,在(較佳地,玻璃)基板與第一電極層之間)以 形成具有該反射性電極層之微腔之部分光反射性(較佳地完全)層(較佳地金屬的,例如銀,及/或較佳地經毯覆式沈積而非圖案化)。此腔可允許放大光及/或使該裝置更有效。 When the electronic device is a light-emitting device such as an OLED, it is preferable that one of the first electrode layer and the second electrode layer (any one, that is, the first electrode layer or the second electrode layer; If it is an embankment emitter device, it is preferably a second electrode layer) It is light-transmissive (if it is an embankment emitter device, it is preferable that the substrate is also transmissive). This device preferably includes a substrate (e.g., between a (preferably, glass) substrate and a first electrode layer) Forming a partially light-reflective (preferably complete) layer of a microcavity having the reflective electrode layer (preferably metallic, such as silver, and / or preferably blanket-deposited rather than patterned). This cavity may allow amplifying light and / or make the device more efficient.

在隨附獨立技術方案中界定較佳實施例。 Preferred embodiments are defined in the accompanying independent technical solution.

較佳實施例之以上態樣中之任一或多者及/或以上選用特徵中之任一或多者可以任何置換方式予以組合。 Any one or more of the above aspects of the preferred embodiment and / or any one or more of the above optional features may be combined in any substitution manner.

11‧‧‧表面層 11‧‧‧ surface layer

12‧‧‧堤部結構層 12‧‧‧ Embankment structure layer

13‧‧‧表面層區域 13‧‧‧ surface layer area

14‧‧‧光阻劑層 14‧‧‧Photoresist layer

15‧‧‧表面 15‧‧‧ surface

21‧‧‧表面層 21‧‧‧ surface layer

22‧‧‧堤部結構層 22‧‧‧ Embankment structure layer

23‧‧‧表面層區域 23‧‧‧ surface layer area

24‧‧‧光阻劑層 24‧‧‧Photoresist layer

25‧‧‧表面 25‧‧‧ surface

31‧‧‧表面層 31‧‧‧ surface layer

32‧‧‧第一堤部層 32‧‧‧The first bank layer

33‧‧‧表面層區域 33‧‧‧ surface layer area

34‧‧‧表面 34‧‧‧ surface

41‧‧‧表面層 41‧‧‧ surface layer

42‧‧‧堤部層 42‧‧‧bank layer

43‧‧‧表面層區域 43‧‧‧ surface layer area

44‧‧‧區域 44‧‧‧area

45‧‧‧表面 45‧‧‧ surface

51‧‧‧表面層 51‧‧‧ surface layer

52‧‧‧堤部層 52‧‧‧bank layer

53‧‧‧表面層區域 53‧‧‧ surface layer area

54‧‧‧區域 54‧‧‧area

55‧‧‧表面 55‧‧‧ surface

61‧‧‧表面層 61‧‧‧ surface layer

62‧‧‧堤部層 62‧‧‧bank layer

63‧‧‧表面層區域 63‧‧‧ surface layer area

64‧‧‧區域 64‧‧‧ area

65‧‧‧表面 65‧‧‧ surface

L1‧‧‧可溶液處理層/層 L1‧‧‧Soluble treatment layer / layer

L2‧‧‧另一可溶液處理層/層 L2‧‧‧Another solution treatment layer / layer

S1‧‧‧第一斜面/斜面 S1‧‧‧First slope / slope

S2‧‧‧第二斜面/斜面 S2‧‧‧Second bevel / bevel

為更好地理解本發明及展示可如何實施本發明,現在將以實例方式參考附圖,在附圖中:圖1a展示實例性製作方法,其中將氟化堤部材料旋塗至陽極(例如,ITO)上,並進行光圖案化以提供井;圖1b展示對遮罩中之部分透射性區域使用單個遮罩步驟以界定長陽極至陰極距離;圖1c展示具有短側壁路徑長度之經RIE圖案化堤部像素(上部至中間圖式)以及相反,根據實施例之提供較長路徑長度之像素(最下部圖式)之實施方案;圖1d展示具有自圖1a或圖1b之製程形成之堤部之裝置;圖2展示使用壽命(裝置穩定性)曲線圖;圖3a展示雙重顯影製程;圖3b展示使用單個圖案化層之雙重遮罩製程;圖3c展示使用單個圖案化層之單個遮罩部分透射性製程;圖3d展示利用反射性區及次臨限曝光劑量之使用單個圖案化層之單個遮罩製程;圖4a至圖4e展示實施例之托架堤部剖面之掃描電子顯微影像;圖5展示跨越裝置之作用區之變化HIL+IL厚度及發射CIE值;圖6圖解說明陡峭堤部結構邊界之所要消除;及 圖7展示針對標準堤部實施例及淺堤部實施例之HIL區域厚度量測之直方圖。 For a better understanding of the invention and to show how it can be implemented, reference will now be made by way of example to the accompanying drawings, in which: FIG. 1a shows an exemplary fabrication method in which a fluorinated dyke material is spin-coated to an anode (e.g. , ITO), and photo-patterned to provide a well; Figure 1b shows the use of a single masking step to define a long anode-to-cathode distance for part of the transmissive area in the mask; Figure 1c shows the RIE with a short sidewall path length Patterned bank pixel (top to middle pattern) and, conversely, an implementation that provides a longer path length pixel (bottom pattern) according to an embodiment; FIG. 1d shows a pixel having a process formed from FIG. 1a or FIG. 1b. The device of the bank; Figure 2 shows the service life (device stability) curve; Figure 3a shows the dual development process; Figure 3b shows the double mask process using a single patterned layer; Figure 3c shows a single mask using a single patterned layer Partial transmissive process of the mask; Figure 3d shows a single masking process using a single patterned layer using a reflective area and a sub-threshold exposure dose; Figures 4a to 4e show scanning electron beams in cross section Microscopic image; FIG. 5 shows the variation across the active region of the device and the thickness of the HIL + IL emission CIE values; FIG. 6 illustrates the structure of the boundary of the steep portion of the bank to be eliminated; and FIG. 7 shows a histogram of the thickness measurement of the HIL region for a standard bank example and a shallow bank example.

一般而言,實例性OLED實施例之層可係如下: In general, the layers of an exemplary OLED embodiment may be as follows:

˙基板,例如玻璃,其較佳地具有用於形成微腔之包括ITO(80nm)電極及視情況地反射性層(例如,Ag)之表面層 A substrate, such as glass, preferably has a surface layer including an ITO (80 nm) electrode and optionally a reflective layer (eg, Ag) for forming a microcavity

˙HIL(電洞注入層)=使用來自日產化工(Nissan Chemical Industries)之ND3202b之噴墨印刷 ˙HIL (hole injection layer) = inkjet printing using ND3202b from Nissan Chemical Industries

˙IL(中間層) ˙IL (middle layer)

˙EL(發光層),其包括發光聚合物LEP,例如綠色發光聚合物。 ˙EL (light emitting layer), which includes a light emitting polymer LEP, such as a green light emitting polymer.

實施例通常提供(舉例而言)具有較長路徑長度以藉此減小洩漏電流之單一堤部構造。對於OLED,此路徑長度可在陽極表面(例如,ITO)與HIL-IL-EL重合流體釘紮點之間。在高阻性HIL旁邊之此等較長路徑長度可形成針對任何潛在寄生洩漏電流及/或非發射性邊緣裝置二極體之高阻性路徑。此堤部結構已證明OLED使用壽命穩定性之改良。 Embodiments generally provide, for example, a single bank configuration with a longer path length to thereby reduce leakage current. For OLEDs, this path length can be between the anode surface (eg, ITO) and the HIL-IL-EL coincident fluid pinning point. These longer path lengths next to the high-resistance HIL can form a high-resistance path for any potential parasitic leakage currents and / or non-emissive edge device diodes. This bank structure has proven to improve the stability of OLED service life.

在以下闡述中預期用於此實施例之若干堤部製程。舉例而言:(i)經由二次層圖案化及部分反應性離子蝕刻(RIE)之經顯影疏水性堤部;(ii)由於RIE遮蔽層而具有部分曝光之像素邊緣之未經圖案化疏水性堤部;(iii)雙重顯影製程;(iv)使用單個圖案化層之雙重遮罩製程;(v)使用單個圖案化層之單個遮罩部分透射性(洩漏)製程;及(vi)利用反射性區及次臨限曝光劑量之使用單個圖案化層之單個遮罩製程。 Several bank processes are contemplated for this embodiment in the following description. For example: (i) a developed hydrophobic bank through secondary layer patterning and partially reactive ion etching (RIE); (ii) unpatterned hydrophobic edges with partially exposed pixel edges due to the RIE masking layer (Iii) dual development process; (iv) dual masking process using a single patterned layer; (v) translucent (leak) process using a single masking portion of a single patterned layer; and (vi) utilization A single masking process using a single patterned layer for reflective areas and sub-threshold exposure doses.

此等製程之實例可提供具有部分經氧氣電漿蝕刻托架之單個經顯影疏水性堤部。有利地,單個經顯影疏水性堤部及後續圖案化步驟 允許氧氣電漿清除ITO區且亦部分地蝕刻預定義量之堤部。ITO及部分經蝕刻堤部較佳地係親水性的,從而允許HIL潤濕直至疏水性堤部之未經蝕刻區。HIL之區段具有在下面直至HIL釘紮點之堤部,其將與IL及EL共用此釘紮點。作用陽極有利地與陰極分離達長的且較佳地可裝置設計之距離,因此(舉例而言)在使用高阻性HIL時造成較低電流洩漏。 Examples of these processes may provide a single developed hydrophobic bank with a partially plasma etched bracket. Advantageously, a single developed hydrophobic bank and subsequent patterning steps The oxygen plasma is allowed to clear the ITO area and also partially etch a predefined amount of the bank. The ITO and part of the etched bank are preferably hydrophilic, allowing the HIL to wet up to the unetched area of the hydrophobic bank. The HIL section has a bank below to the HIL pinning point, which will share this pinning point with IL and EL. The working anode is advantageously separated from the cathode by a long and preferably device-designable distance, thus (for example) causing lower current leakage when using a high-resistance HIL.

可因此藉由提供潤濕陽極表面(ITO)及陽極表面與HIL-IL-EL重合流體釘紮點之間之較長路徑長度來改良用於OLED之單個堤部構造。此等較長路徑長度可形成針對任何潛在寄生洩漏電流之高阻性選項。實施例允許陽極至陰極路徑以受控制方式延長且因而係可調諧的以減小寄生洩漏電流,此又可改良裝置效率。 The single bank structure for OLEDs can therefore be improved by providing a wet anode surface (ITO) and a longer path length between the anode surface and the HIL-IL-EL coincident fluid pinning point. These longer path lengths provide a high-resistance option for any potential parasitic leakage current. Embodiments allow the anode-to-cathode path to be extended in a controlled manner and thus tunable to reduce parasitic leakage currents, which in turn can improve device efficiency.

另外或另一選擇係,此等製程可減小相對於雙重堤部構造之結構複雜性。 Additionally or alternatively, these processes can reduce the complexity of the structure relative to the double bank structure.

圖1a展示實例性製作方法,其中將氟化堤部材料(堤部結構層12)旋塗至陽極(表面層11)(例如,ITO)上,且對其進行光圖案化以提供井(見表面層區域13上面之區)。然後光圖案化堤部材料上方之光阻劑層14,且進行額外處理以移除堤部之區段,由此延長絕緣堤部托架。此額外處理可包括經施用以進行蝕刻而部分地穿過堤部材料之反應性離子蝕刻。在額外處理之後移除光阻劑。因此可使堤部材料在井之邊緣處之輪廓變化,以使得該輪廓提供較長路徑長度。如由沿著圖1中之第一斜面s1及第二斜面s2之僅說明性細線所展示,該蝕刻導致至藉由移除光阻劑曝光之表面15之較長電路徑。 Figure 1a shows an exemplary fabrication method in which a fluorinated bank material (bank structure layer 12) is spin-coated onto an anode (surface layer 11) (e.g., ITO) and photo-patterned to provide a well (see The area above the surface layer area 13). The photoresist layer 14 above the material of the bank is then light-patterned and additional processing is performed to remove the section of the bank, thereby extending the insulating bank of the bank. This additional processing may include reactive ion etching applied partially to etch through the bank material. The photoresist is removed after additional processing. It is therefore possible to vary the profile of the bank material at the edges of the well so that the profile provides a longer path length. As shown by only illustrative thin lines along the first slanted surface s1 and the second slanted surface s2 in FIG. 1, this etching results in a longer electrical path to the surface 15 exposed by removing the photoresist.

在圖1b中展示之替代方法使用藉助遮罩中之部分透射性區域之單個遮罩步驟來界定針對堤部托架之長陽極至陰極距離;RIE步驟較佳地蝕刻其中存在薄正型遮蔽層之像素邊緣。RIE可蝕刻出像素,其中像素之邊緣由於薄遮蔽層而曝光於電漿。可使用此方法,藉由改變 經顯影堤部像素之相對於經RIE圖案化開孔之尺寸之經遮罩設計大小來調整陽極至陰極距離及因此調整寄生洩漏電流之量。此與簡單經光圖案化堤部像素及/或簡單經RIE圖案化堤部像素相反,其中每一者將通常給出自陽極至陰極(藍色區)之短路徑長度且其長度通常不可調整。具體而言,圖1b展示表面層21、堤部結構層22、表面層區域23、光阻劑層24、斜面s1及s2,以及表面25。 The alternative method shown in Figure 1b uses a single masking step with partial transmissive areas in the mask to define a long anode-to-cathode distance to the bank of the bank; the RIE step preferably etches the presence of a thin positive masking layer Pixel edge. RIE can etch out pixels, where the edges of the pixels are exposed to the plasma due to the thin shielding layer. You can use this method by changing The size of the masked pixels of the developed banks relative to the size of the RIE patterned openings is adjusted to adjust the anode-to-cathode distance and therefore the amount of parasitic leakage current. This is in contrast to simple light-patterned bank pixels and / or simple RIE-patterned bank pixels, each of which will typically give a short path length from the anode to the cathode (blue area) and its length is usually not adjustable. Specifically, FIG. 1 b shows the surface layer 21, the bank structure layer 22, the surface layer region 23, the photoresist layer 24, the inclined surfaces s1 and s2, and the surface 25.

(圖1c展示具有短側壁路徑長度之經RIE圖案化堤部像素(上部至中間圖式)以及相反,根據實施例之提供較長路徑長度之像素(最下部圖式)之製作)。 (Figure 1c shows the fabrication of RIE-patterned bank pixels (top-to-middle pattern) with short sidewall path lengths and conversely, pixels with longer path lengths (bottom pattern) according to an embodiment).

圖1d展示具有自如上所闡述之製程實施例形成之堤部且進一步包括呈HIL(電洞注入層)形式之可溶液處理層L1以及呈IL(中間層)及/或LEP(發光聚合物)層形式之另一可溶液處理層L2之裝置。如自圖1d所見,HIL、IL及LEP流體具有重合釘紮點。IL及/或LEP層可由EIL(電子注入層)覆蓋,該EIL又可由陰極層覆蓋。較佳地,此EIL不共用層L1及L2之釘紮點,而是覆蓋此等層並延伸跨過堤部結構之毗鄰區。陰極層可較佳地直接沈積於EIL上,其在實施例中保形地塗佈EIL以延伸跨過該等層及該等毗鄰區。 Figure 1d shows a bank portion formed with the process embodiment described above and further comprising a solution-treatable layer L1 in the form of a HIL (hole injection layer) and an IL (intermediate layer) and / or a LEP (light emitting polymer) Another device for layer L2 which can be processed in the form of a layer. As seen from Figure 1d, the HIL, IL, and LEP fluids have coincident pinning points. The IL and / or LEP layer may be covered by an EIL (electron injection layer), which in turn may be covered by a cathode layer. Preferably, the EIL does not share the pinning points of the layers L1 and L2, but instead covers these layers and extends across adjacent areas of the embankment structure. The cathode layer may preferably be deposited directly on the EIL, which in an embodiment is conformally coated with the EIL to extend across the layers and the adjacent regions.

鑑於上文,實施例提供與(距離而言)分離陽極釘紮點與陰極之雙重堤部系統相反具有長絕緣托架之單個堤部結構。可使用單個疏水性堤部且施用後續圖案化製程以拉長堤部托架。在實施例中,ITO及堤部托架可係親水性的,從而允許HIL潤濕直至經預界定點,此處,堤部變成疏水性的(油墨釘紮點)。HIL之區段將具有在下面直至HIL釘紮點之堤部,其將與IL及LEP共有此釘紮點。藉由使用高阻性HIL,作用陽極可與陰極分離達長(且可裝置設計的)距離。 In view of the above, embodiments provide a single bank structure with a long insulated bracket as opposed to a (distance) dual bank system that separates the anode pinning point from the cathode. A single hydrophobic bank can be used and a subsequent patterning process can be applied to elongate the bank of the bank. In an embodiment, the ITO and the bank of the bank can be hydrophilic, allowing HIL to wet up to a predefined point, where the bank becomes hydrophobic (ink pinning point). The HIL section will have a bank below to the HIL pinning point, which will share this pinning point with IL and LEP. By using a high-resistance HIL, the working anode can be separated from the cathode by a long (and device-designable) distance.

實施例允許陽極至陰極路徑長度以受控制方式增加且因而提供可調諧製程來減小寄生洩漏電流,此導致使用壽命測試時之較穩定 (且可重複)裝置照度。相反,藉由標準光微影製程或較複雜但標準RIE(反應性離子蝕刻)製程形成之單個堤部可提供用於像素(堤部)界定之價廉方法。然而,兩個標準技術可使短陽極至陰極路徑長度保持在像素(裝置)邊緣處。已展示陽極(ITO)表面與HIL-IL-EL-陰極重合釘紮點之間之短路徑長度(短托架)在隨時間驅動時造成不穩定裝置。 Embodiments allow the anode-to-cathode path length to be increased in a controlled manner and thus provide a tunable process to reduce parasitic leakage currents, which results in a more stable life test (And repeatable) device illumination. In contrast, a single bank formed by a standard photolithography process or a more complex but standard RIE (reactive ion etching) process can provide an inexpensive method for pixel (bank) definition. However, two standard techniques can keep short anode-to-cathode path lengths at the edge of a pixel (device). It has been shown that the short path length (short bracket) between the anode (ITO) surface and the HIL-IL-EL-cathode coincident pinning point causes an unstable device when driven over time.

圖1a可另一選擇係被認為展示用於具有長托架之單個堤部之製程流程實施例。該製程涉及雙重步驟圖案化製程以產生長堤部托架。自陽極(ITO)至油墨釘紮點之托架長度可受二次圖案化步驟控制,托架之深度亦可同樣地受控制,以提供與陽極之足夠電絕緣。可使用此實施例,藉由改變經顯影堤部像素之相對於二次部分圖案化步驟之像素尺寸之經遮罩設計大小來調整陽極至陰極距離(見僅說明性細線)及因而調整寄生洩漏電流之量。與(舉例而言)簡單經光圖案化堤部像素或簡單經RIE圖案化堤部像素(其中每一者將通常給出自陽極至陰極之短路徑長度(<1μm)且其長度通常不可調整(除了藉由堤部高度))相比,此實施例產生長托架裝置(例如,>2μm)。 FIG. 1a may alternatively be considered to show an embodiment of a process flow for a single bank with a long bracket. This process involves a two-step patterning process to create a long bank. The length of the bracket from the anode (ITO) to the ink pinning point can be controlled by the second patterning step, and the depth of the bracket can be controlled similarly to provide sufficient electrical insulation from the anode. This embodiment can be used to adjust the anode-to-cathode distance by changing the masked design size of the pixel of the developed bank relative to the pixel size of the secondary partial patterning step (see only illustrative thin lines) and thus the parasitic leakage The amount of current. And (for example) simple light-patterned dyke pixels or simple RIE patterned dyke pixels (each of which will usually give a short path length (<1 μm) from anode to cathode and its length is usually not adjustable ( Except by the height of the bank)), this embodiment results in a long carriage device (eg,> 2 μm).

較長陽極至陰極距離亦可藉由使得堤部較高而達成,然而,此通常將對像素邊緣處之HIL-IL-EL輪廓具有消極影響,使得其較厚且造成不均勻發射。 A longer anode-to-cathode distance can also be achieved by making the bank higher, however, this will usually have a negative effect on the HIL-IL-EL contour at the edge of the pixel, making it thicker and causing uneven emission.

較佳地,實施例之HIL、IL及EL全部皆具有重合釘紮點。此可造成自陽極至陰極之長洩漏路徑,其中HIL(導電性電洞注入層)與金屬陰極相接。藉由使用高阻性HIL且然後分離陽極(ITO)與陰極達長橫向HIL距離(如上所述)來使此效應最小化。 Preferably, the HIL, IL, and EL in the embodiments all have coincident pinning points. This can cause a long leakage path from the anode to the cathode, where a HIL (conductive hole injection layer) is connected to the metal cathode. This effect is minimized by using a high-resistance HIL and then separating the anode (ITO) from the cathode for a long lateral HIL distance (as described above).

考量裝置結果,在使用壽命測試期間之裝置穩定性展示了顯著改良。在實施例中,長托架藉由將阻力(路徑長度)增加至HIL-IL-EL符合之某一點來顯著地減小像素邊緣二極體效應(其係非發射性薄二極體)。 Considering the results of the device, the stability of the device during the life test showed a significant improvement. In an embodiment, the long bracket significantly reduces the pixel edge diode effect (which is a non-emissive thin diode) by increasing the resistance (path length) to a certain point of the HIL-IL-EL compliance.

圖2展示使用壽命(裝置穩定性)曲線圖。可見,用於單個堤部短托架裝置(虛曲線)之初始亮波(固定電流處之增加照度)在裝置之間有顯著不同。此可能起因於存在垂直洩漏路徑,其在測試期間「燒毀」,致使電流重新分配。在圖2中,單個堤部長托架(連續曲線)展示亮波量值之緊密得多的分配,此意味著該效應可能與洩漏電流無關。使用此堤部評估材料及製程穩定性係可能的。對於單個堤部長托架配置,使用壽命(裝置降級)係更加可預測的且對像素邊緣裝置效應之依賴性要低得多。因此,具有長托架之單個疏水性堤部已證明關於OLED使用壽命穩定性之改良。 Figure 2 shows a graph of service life (device stability). It can be seen that the initial bright wave (increased illuminance at a fixed current) for a single crater short bracket device (dotted curve) is significantly different between the devices. This may be due to the existence of a vertical leakage path, which "burned out" during the test, causing current to be redistributed. In Fig. 2, a single bank long bracket (continuous curve) shows a much tighter distribution of the magnitude of the bright wave, which means that the effect may be independent of the leakage current. It is possible to use this embankment to assess material and process stability. For a single bank configuration, the service life (device degradation) is more predictable and the dependence on the device effects at the edge of the pixel is much lower. Therefore, a single hydrophobic bank with a long bracket has proven to improve the lifetime stability of OLEDs.

考量製程複雜性,應注意經簡化製程方法可產生長托架單個疏水性堤部,及/或藉由產生具有長絕緣托架以減小洩漏之單個堤部方法來減小相對於雙重堤部構造之複雜性。有利地,此經簡化實施例允許陽極至陰極路徑以受控制方式增長,且因而可調諧地減小寄生洩漏電流,此減小裝置效率。實施例涵蓋達成單個堤部像素之替代性經簡化方法。 Considering the complexity of the process, it should be noted that the simplified process method can produce a single hydrophobic bank with a long bracket, and / or reduce the relative to the double bank with a single bank method with a long insulating bracket to reduce leakage. The complexity of construction. Advantageously, this simplified embodiment allows the anode-to-cathode path to grow in a controlled manner, and thus tunably reduces parasitic leakage currents, which reduces device efficiency. Embodiments cover an alternative simplified method of achieving a single bank pixel.

進一步關注製程複雜性,圖1a之製程方法涉及經由二次層圖案化及部分反應性離子蝕刻(RIE)之經顯影疏水性堤部。此可需要二個微影圖案化迴環(例如:清除、烘烤、塗佈、烘烤、曝光、烘烤、顯影、堤部固化、塗佈、曝光、顯影)加RIE步驟及正型抗蝕劑剝除。 Further attention is paid to the complexity of the process. The process method of FIG. 1a involves a developed hydrophobic bank through secondary layer patterning and partially reactive ion etching (RIE). This may require two lithographic patterning loops (e.g., removal, baking, coating, baking, exposure, baking, development, bank curing, coating, exposure, development) plus a RIE step and a positive resist Agent stripping.

然而,舉例而言,與使用二個光圖案化步驟加反應性離子蝕刻以產生OLED裝置穩定性所需之長托架(如在圖1a所展示)之實施例相比,圖1b實施例可提供長托架單個經顯影疏水性堤部之製程簡化。 However, for example, compared to the embodiment using two photo-patterning steps plus reactive ion etching to produce a long bracket (as shown in Figure 1a) required for OLED device stability, the embodiment of Figure 1b can The process of providing a long developed single developed hydrophobic bank is simplified.

然而,如在圖1b中展示之第一簡化展示由於RIE遮蔽層而具有部分曝光之像素邊緣之未經圖案化疏水性堤部。此製程消除對第一圖案化迴環上之遮罩及顯影步驟之需要。 However, the first simplified display as shown in Figure 1b shows an unpatterned hydrophobic bank with partially exposed pixel edges due to the RIE masking layer. This process eliminates the need for masking and development steps on the first patterned loop.

在圖3a中展示替代簡化,其被闡述為雙重顯影製程。此製程可消 除對RIE及剝除步驟之需要。較佳地,第一經圖案化堤部係薄的,具有至像素中之淺斜面。較佳地,沈積第一薄堤部層,例如旋塗並使其變硬。然後光圖案化及後續顯影該薄層以曝光陽極之區域,該薄層具有至經曝光區域之緩和斜面。然後沈積、光圖案化並顯影另一堤部層。有利地,該另一堤部層內之諸如氟物種(例如,氟部分)之物種在烘烤彼層期間遷移至該另一堤部層之頂部表面,使得該頂部表面與該另一堤部層之側壁(較佳地亦該薄層之側壁)相比較不可被將沈積於經曝光區域上之溶液潤濕。具體而言,圖3a展示表面層31、第一堤部層32、表面層區域33、具有表面34及斜面s1及s2之第二堤部層。 An alternative simplification is shown in Figure 3a, which is illustrated as a dual development process. This process can be eliminated Eliminates need for RIE and stripping steps. Preferably, the first patterned bank portion is thin and has a shallow slope to the pixel. Preferably, a first thin bank layer is deposited, such as by spin coating, and hardened. The thin layer is then light patterned and subsequently developed to expose areas of the anode, the thin layer having a gentle slope to the exposed area. Then another bank layer is deposited, light patterned and developed. Advantageously, a species such as a fluorine species (e.g., a fluorine moiety) within the other bank layer migrates to the top surface of the other bank layer during baking of the other layer, such that the top surface and the other bank layer The side walls of the layer (preferably also the side walls of the thin layer) are less wettable by the solution deposited on the exposed area. Specifically, Fig. 3a shows a surface layer 31, a first bank layer 32, a surface layer region 33, and a second bank layer having a surface 34 and slopes s1 and s2.

圖3b展示呈使用單個圖案化層之雙重遮罩製程形式之替代簡化。此係不使用正型抗蝕劑層之單個圖案化步驟製程,但其可需要二個光遮罩及雙重曝光步驟。上部遮罩(遮罩2)可係梯度遮罩以較清晰地界定斜面s1及s2。具體而言,圖3b展示表面層41、堤部層42、表面層區域43、斜面s1及s2,以及表面45,其中區域44係堤部層之相對於區域44之間或表面45下方之(若干)第一區域之第二區域。 Figure 3b shows an alternative simplification in the form of a dual masking process using a single patterned layer. This process does not use a single patterning process for a positive resist layer, but it may require two photomasks and a double exposure step. The upper mask (Mask 2) may be a gradient mask to more clearly define the slopes s1 and s2. Specifically, FIG. 3b shows the surface layer 41, the bank layer 42, the surface layer region 43, the inclined surfaces s1 and s2, and the surface 45, where the region 44 is between the bank layer layer and the region 44 or below the surface 45 ( (Several) the second area of the first area.

圖3c展示另一替代簡化:使用單個圖案化層之單個遮罩部分透射性(洩漏)製程。此係不使用正型抗蝕劑層之單個圖案化步驟製程,但其可需要較高成本之光遮罩,但使用單個曝光步驟。具體而言,圖3c展示表面層51、堤部層52、表面層區域53、斜面s1及s2,以及表面55,其中區域54係堤部層之相對於區域54之間或表面55下方之(若干)第一區域之第二區域。部分透射性(例如,亞解析度特徵化)遮罩可係梯度遮罩以較清晰地界定斜面s1及s2。 Figure 3c shows another alternative simplification: a single masked part transmissive (leak) process using a single patterned layer. This process does not use a single patterning step process of a positive resist layer, but it may require a higher-cost light mask, but uses a single exposure step. Specifically, FIG. 3c shows the surface layer 51, the bank layer 52, the surface layer region 53, the slopes s1 and s2, and the surface 55, where the region 54 is between the bank layer and the region 54 or below the surface 55 ( (Several) the second area of the first area. Partially transmissive (eg, sub-resolution characterization) masks can be gradient masks to more clearly define the bevels s1 and s2.

圖3d展示又一替代簡化:利用反射性區及次臨限曝光劑量之使用單個圖案化層之單個遮罩製程。此係不使用正型抗蝕劑層但使用單個曝光步驟之單個圖案化步驟製程。上述層之設計可併入有用於產生較高劑量區域以完全交聯堤部之反射性區。可使用此方法調整陽極至 陰極距離及因而調整寄生洩漏電流之量。具體而言,圖3d展示表面層61、堤部層62、表面層區域63、斜面s1及s2,以及表面65,其中區域64係堤部層之相對於表面65下方之(若干)第一區域之第二區域。 Figure 3d shows yet another alternative simplification: a single masking process using a single patterned layer using reflective areas and sub-threshold exposure doses. This is a single patterning step process that does not use a positive resist layer but uses a single exposure step. The design of the above layers may incorporate reflective areas for creating higher dose areas to completely crosslink the bank. You can use this method to adjust the anode to The cathode distance and thus the amount of parasitic leakage current are adjusted. Specifically, FIG. 3d shows the surface layer 61, the bank layer 62, the surface layer region 63, the slopes s1 and s2, and the surface 65, where the region 64 is the first region (several) of the bank layer relative to the surface 65 The second area.

此與經光圖案化單個堤部像素及/或經RIE圖案化堤部像素相反,其中每一者將通常給出自陽極至陰極(藍色區)之短路徑長度且其長度通常不可調整(見圖1c)。 This is in contrast to light-patterned individual bank pixels and / or RIE-patterned bank pixels, each of which will typically give a short path length from the anode to the cathode (blue area) and its length is usually not adjustable (see Figure 1c).

針對如上所述之不同方法及實施例,圖4展示多個實例性托架堤部影像。圖4a展示雙重經顯影長托架堤部,圖4b展示具有HIL之雙重經顯影長托架堤部,圖4c展示經由RIE之凹口之長托架堤部,圖4d展示單個經顯影堤部,且圖4e展示具有HIL(短(無)托架)之單個經顯影堤部。 For different methods and embodiments as described above, FIG. 4 shows a plurality of example bracket bank images. Figure 4a shows a double-developed long bracket bank, Figure 4b shows a double-developed long bracket bank with HIL, Figure 4c shows a long-bracket bank through a notch in RIE, and Figure 4d shows a single developed bank And Figure 4e shows a single developed bank with a HIL (short (no) bracket).

HIL+IL之平坦厚度量變曲線係所要的以使微腔平臺上之OLED裝置效能最大化。在噴墨印刷裝置中,厚度量變曲線取決於下伏堤部結構。此下文詳述較佳堤部輪廓以達成單個堤部噴墨印刷裝置中之適當平坦厚度量變曲線。有利地,此輪廓可提供自堤部托架至作用區之漸變過渡,從而允許印刷HIL形成適合於微腔OLED裝置之平坦型材。 The flat thickness variation curve of HIL + IL is required to maximize the efficiency of the OLED device on the microcavity platform. In the inkjet printing apparatus, the thickness curve depends on the underlying bank structure. The following is a detailed description of the preferred bank profile in order to achieve an appropriate flat thickness variation curve in a single bank inkjet printing device. Advantageously, this profile can provide a gradual transition from the embankment bracket to the active area, thereby allowing the printed HIL to form a flat profile suitable for microcavity OLED devices.

具體地考量使用漸變托架單個堤部+無水HIL之平坦覆膜型材,實施例可提供自堤部托架至作用區之漸變過渡,因此允許印刷HIL形成適合於微腔OLED裝置之平坦型材。HIL+IL之平坦厚度量變曲線係所要的以使微腔平臺上之OLED裝置效能最大化。在噴墨印刷裝置中,厚度量變曲線取決於下伏堤部結構。實施例提供用於達成單個堤部噴墨印刷裝置中之適合平坦厚度量變曲線之堤部輪廓。 Specifically considering the use of a flat film profile with a single bank of a gradation bracket + anhydrous HIL, the embodiment can provide a gradual transition from the cradle of the bank to the action zone, thus allowing the printed HIL to form a flat profile suitable for microcavity OLED devices. The flat thickness variation curve of HIL + IL is required to maximize the efficiency of the OLED device on the microcavity platform. In the inkjet printing apparatus, the thickness curve depends on the underlying bank structure. The embodiment provides a bank profile suitable for achieving a flat thickness variation curve in a single bank inkjet printing device.

達成最佳可能色彩點處之最大效能通常需要對微腔OLED裝置中之層厚度及輪廓之精確控制。此外,若存在HIL+IL層輪廓區域之顯著不均勻性,則將呈現非最佳輸出耦合且效能將受損。 Achieving maximum performance at the best possible color point often requires precise control of layer thickness and contours in microcavity OLED devices. In addition, if there is significant unevenness in the contour area of the HIL + IL layer, non-optimal output coupling will be presented and performance will be impaired.

舉例而言,在圖5中展示噴墨印刷裝置之HIL+IL厚度之寬度剖面。可見像素之邊緣區展示與中心區域相比顯著地變厚。在此等區域中依據目標色彩點轉移CIE座標。此致使折衷總體裝置效能。 For example, the width profile of the HIL + IL thickness of an inkjet printing device is shown in FIG. 5. The visible pixel edge region display is significantly thicker than the center region. In these regions, the CIE coordinates are shifted according to the target color point. This leads to a compromise in overall device performance.

已開發堤部類型使邊緣變厚之量最小化且因而改良印刷效能。自托架至ITO之急劇過渡致使邊緣由於HIL無法緊密跟隨堤部輪廓而變厚。 Bank types have been developed to minimize the amount of edge thickening and thus improve printing performance. The sharp transition from the bracket to the ITO caused the edges to thicken because the HIL could not closely follow the contour of the bank.

在圖6中展示具有漸變堤部托架之實施例,在下部圖中包含對上部環狀區域特寫表示,其中在右手側下部圖中展示與無漸變傾斜(左手側)之實施例相比之此傾斜。 An embodiment with a gradual embankment bracket is shown in FIG. 6, which includes a close-up representation of the upper annular region in the lower diagram, where the lower diagram on the right-hand side is shown in comparison with the embodiment without gradual tilt (left-hand side) This tilt.

使用此漸變托架堤部類型已展示使墨噴印刷平臺上之裝置效能最大化,使得其可與SC(經旋塗裝置)資料(展示用於發射綠色光之裝置之資料)相匹敵: The use of this gradient bracket bank type has been shown to maximize the performance of the device on the inkjet printing platform, making it comparable to SC (spin-coated device) data (showing data for devices that emit green light):

其中DE=D(u’v’),使用CIE 1976色彩空間之u’、v’定義(「CIELUV」)。該表展示諸如漸變托架堤部裝置之噴墨印刷裝置具有可與經旋塗裝置匹敵之效能。 Where DE = D (u'v '), the u', v 'definitions ("CIELUV") of the CIE 1976 color space are used. This watch shows that inkjet printing devices, such as the gradual carriage bank device, are comparable to spin-coated devices.

進一步就此而言,應注意藉由以下給出自1931 CIE XYZ色彩空間之CIExy至CIELUV之CIE u’v’之轉換(亦即,CIE1931→CIE1976): 且藉由以下給出使用CIELUV之u’、v’定義之色差度量DE: ,亦即,CIE 1976空間中之歐幾裡德距離。 Further in this regard, it should be noted that the conversion from CIExy of the 1931 CIE XYZ color space to CIE u'v 'of CIELUV is given by the following (ie, CIE1931 → CIE1976): And the color difference metric DE defined using u ', v' of CIELUV is given by: , That is, the Euclidean distance in CIE 1976 space.

對於諸如上述「漸變托架堤部」裝置之實施例,用於綠色發射之CIEx及y目標(NTSC)分別係0.213及0.724。使用美能達色度計獲得CIExy,且使用CIExy計算dE。 For embodiments such as the "gradient bracket bank" device described above, the CIEx and Y Target (NTSC) for green launches are 0.213 and 0.724, respectively. CIExy was obtained using a Minolta colorimeter, and dE was calculated using CIExy.

dE=0.02係實施例中可接受之較佳上限,然而,0.005、0.01或0.015更係所要的。 dE = 0.02 is a preferred upper limit acceptable in the examples, however, 0.005, 0.01, or 0.015 is more desirable.

圖7展示直方圖,該直方圖展示標準堤部具有比具有漸變托架堤部之實施例大之較厚區域比例。藉由量測跨越由堤部結構之側壁圍繞之表面層區域上方上作用區之規則地間隔開之點處之厚度來獲得該直方圖。具有「標準堤部」之裝置係與在圖6之上部圖中所展示類似地具有實質上恆定厚度之長托架之裝置。具有「淺堤部」之裝置具有朝該裝置之表面層逐漸變細之長托架,例如具有較佳地小於5度、10度、15度或20度之角度之第一斜面。「淺堤部」裝置具有比「標準堤部」裝置窄之厚度分配,因而允許OLED中之更受控制輸出耦合(在吸光裝置中係輸入耦合)。 FIG. 7 shows a histogram showing that the standard bank has a thicker area ratio than the embodiment with the gradient bracket bank. The histogram is obtained by measuring the thickness at regularly spaced points across the action zone above the surface layer region surrounded by the sidewalls of the bank structure. The device with a "standard bank" is a device with a long bracket of substantially constant thickness similar to that shown in the upper part of Figure 6. A device having a "shallow bank" has a long bracket that tapers toward the surface layer of the device, such as a first inclined surface that preferably has an angle of less than 5 degrees, 10 degrees, 15 degrees, or 20 degrees. The "shallow bank" device has a narrower thickness distribution than the "standard bank" device, thus allowing more controlled output coupling (input coupling in light absorbing devices) in OLEDs.

毫無疑問,熟習此項技術者將想出諸多其他有效替代方案。將理解,本發明不限於所闡述之實施例且涵蓋對熟習此項技術者顯而易見之修改,此歸屬於本文隨附申請專利範圍之範疇內。 There is no doubt that those skilled in the art will come up with many other effective alternatives. It will be understood that the present invention is not limited to the illustrated embodiments and encompasses modifications apparent to those skilled in the art, which fall within the scope of the patent application attached hereto.

Claims (22)

一種製作包括具有表面層及該表面層上之界定井之堤部結構之基板之電子裝置的方法,該堤部結構包括電絕緣材料且具有圍繞該表面層之一區域以藉此界定該井之側壁,該表面層區域包括第一電極及經配置以形成微腔之部分反射性層,且該裝置進一步包括第二電極及安置於該第一電極與該第二電極之間的半導電性材料,該方法包括:形成具有包括自該表面層區域延伸之第一斜面及自該第一斜面延伸之第二斜面之該側壁之該堤部結構,其中該第二斜面比該第一斜面陡峭,其中該側壁具有在該第二斜面上與該第一斜面間隔開之點處之表面能量不連續性;形成具有至少一個層之層結構,該層結構安置於該第一電極與該第二電極之間且具有該半導電性材料,其中該形成該層結構包括:在該表面層區域上及該側壁之該第一斜面及該第二斜面上沈積有機溶液以形成可溶液處理之該層,其中該經沈積有機溶液潤濕該第一斜面及該第二斜面直至該表面能量不連續性處之釘紮點;及乾燥該經沈積有機溶液。A method of fabricating an electronic device including a substrate having a surface layer and a bank structure defining a well on the surface layer, the bank structure including an electrically insulating material and having a region surrounding the surface layer to thereby define the well A sidewall, the surface layer region including a first electrode and a partially reflective layer configured to form a microcavity, and the device further includes a second electrode and a semi-conductive material disposed between the first electrode and the second electrode The method includes forming the bank structure having the side wall including a first inclined surface extending from the surface layer region and a second inclined surface extending from the first inclined surface, wherein the second inclined surface is steeper than the first inclined surface, The side wall has a discontinuity in surface energy at a point at which the second inclined plane is spaced from the first inclined plane; a layer structure having at least one layer is formed, and the layer structure is disposed on the first electrode and the second electrode And has the semi-conductive material therebetween, wherein the forming the layer structure includes: depositing an organic solution on the surface layer region and the first inclined surface and the second inclined surface of the side wall to This layer of solution to be treated, wherein the organic solution was deposited wets the first inclined surface and the second inclined surface until the staple of the discontinuity of the surface energy of tie points; and drying the deposited organic solution. 如請求項1之方法,其包括:在該可溶液處理層上方沈積至少另一溶液,其中該至少另一溶液潤濕直至該釘紮點;及乾燥該經沈積至少另一溶液。The method of claim 1, comprising: depositing at least another solution over the solution-treatable layer, wherein the at least another solution is wetted to the pinning point; and drying the deposited at least another solution. 如請求項1或2之方法,其中該形成該堤部結構包括:形成包括該基板之該表面層上之光阻劑之第一堤部層;光圖案化並顯影該第一堤部層以曝光該表面層之該區域;將氟化光阻劑溶液沈積至該第一堤部層及該表面層之經曝光區域上以形成第二堤部層;進行烘烤以使該第二堤部層變硬,其中該氟化光阻劑溶液之含氟化合物在該烘烤期間遷移至該第二堤部層之表面以增加該有機溶液與該表面之接觸角;及光圖案化並顯影該第二堤部層以重新曝光該表面層之該區域且曝光該第一堤部層之一區域,使得該第一堤部層區域具有該第一斜面且該第二堤部層具有該第二斜面,其中該經增加接觸角高於該有機溶液與該第一斜面及該第二斜面之接觸角,且該釘紮點係在具有該等經遷移含氟化合物之該第二堤部層表面之邊界處。The method as claimed in claim 1 or 2, wherein the forming the bank structure includes: forming a first bank layer including a photoresist on the surface layer of the substrate; photo-patterning and developing the first bank layer to Expose the area of the surface layer; deposit a fluorinated photoresist solution on the first bank portion layer and the exposed area of the surface layer to form a second bank portion layer; and bake to make the second bank portion The layer becomes hard, wherein the fluorinated compound of the fluorinated photoresist solution migrates to the surface of the second bank layer during the baking to increase the contact angle between the organic solution and the surface; and photo-patterning and developing the The second bank layer re-exposes the region of the surface layer and exposes an area of the first bank layer, so that the first bank layer region has the first slope and the second bank layer has the second A bevel, wherein the increased contact angle is higher than the contact angle of the organic solution with the first bevel and the second bevel, and the pinning point is on the surface of the second bank layer with the migrated fluorine-containing compounds At the border. 如請求項1或2之方法,其中該形成該堤部結構包括:藉由在該表面層上沈積氟化光阻劑溶液來形成堤部結構層,且乾燥該經沈積溶液以使該堤部結構層變硬,其中該氟化光阻劑溶液之含氟化合物在該烘烤期間遷移至該堤部結構層之表面以增加該有機溶液與該表面之接觸角;在該堤部結構層上沈積並乾燥光阻劑層,且光圖案化並顯影該光阻劑層;乾式蝕刻步驟,其用以蝕刻該堤部結構層穿過該經顯影光阻劑層以曝光該表面層區域,使得該經蝕刻堤部結構層具有圍繞該經曝光表面層區域之該側壁且包括該第一斜面及該第二斜面;及移除該經顯影光阻劑層以曝光該堤部結構層之表面,該經曝光表面包括該等經遷移含氟化合物,其中該表面能量不連續性係在包括該等經遷移含氟化合物之該經曝光表面與該經蝕刻側壁之間的界面處。The method of claim 1 or 2, wherein the forming the bank structure includes forming a bank structure layer by depositing a fluorinated photoresist solution on the surface layer, and drying the deposited solution to make the bank The structure layer becomes hard, wherein the fluorine-containing compound of the fluorinated photoresist solution migrates to the surface of the bank structure layer during the baking to increase the contact angle between the organic solution and the surface; on the bank structure layer Depositing and drying the photoresist layer, and photo-patterning and developing the photoresist layer; a dry etching step for etching the bank structure layer through the developed photoresist layer to expose the surface layer region so that The etched bank structure layer has the side wall surrounding the exposed surface layer region and includes the first inclined surface and the second inclined surface; and removing the developed photoresist layer to expose the surface of the bank structure layer, The exposed surface includes the migrated fluorine-containing compounds, wherein the surface energy discontinuity is at an interface between the exposed surface including the migrated fluorine-containing compounds and the etched sidewall. 如請求項4之方法,其中該形成該堤部結構包括:顯影並光圖案化該堤部結構層以曝光由該堤部結構層之側壁圍繞之該表面層區域,其中該在該堤部結構層上沈積該光阻劑層包括在該經光圖案化堤部結構層上沈積光阻劑溶液,且該顯影該光阻劑層包括重新曝光該表面層區域,且用以曝光該表面層區域之該乾式蝕刻步驟藉由薄化該堤部結構層以藉此形成該第一斜面及該第二斜面而使該經曝光區域延伸。The method of claim 4, wherein the forming the bank structure includes developing and photo-patterning the bank structure layer to expose the surface layer region surrounded by the sidewall of the bank structure layer, wherein the structure on the bank structure Depositing the photoresist layer on the layer includes depositing a photoresist solution on the photo-patterned bank structure layer, and developing the photoresist layer includes re-exposing the surface layer region and exposing the surface layer region The dry etching step extends the exposed area by thinning the bank structure layer to form the first inclined surface and the second inclined surface. 如請求項5之方法,其中該光圖案化該光阻劑層包括穿過具有非透射性區域、部分透射性區域及完全透射性區域之遮罩輻射該光阻劑層;且該顯影該光阻劑層包括完全移除光阻劑之一區域且部分地移除穿過該部分透射性區域曝光於輻射之光阻劑區域。The method of claim 5, wherein the light patterning the photoresist layer includes radiating the photoresist layer through a mask having non-transmissive regions, partially transmissive regions, and fully transmissive regions; and developing the light The resist layer includes completely removing a region of the photoresist and partially removing the photoresist region exposed to the radiation through the partially transmissive region. 如請求項6之方法,其中該乾式蝕刻步驟包括使用氧氣電漿之反應性離子蝕刻。The method of claim 6, wherein the dry etching step includes reactive ion etching using an oxygen plasma. 如請求項1之方法,其中該形成該堤部結構包括:藉由在該表面層上沈積氟化光阻劑溶液來形成堤部層;進行烘烤以使該堤部層變硬,其中該光阻劑溶液之氟化合物在該烘烤期間遷移至該堤部層之表面以藉此增加該有機溶液與該表面之接觸角;光圖案化該變硬堤部層,該光圖案化包括以第一輻射劑量輻射該堤部層之第一區域以及以第二輻射劑量輻射該堤部層之第二區域,該第二輻射劑量小於該第一輻射劑量;顯影該堤部層以曝光該表面層之該區域且部分地移除以該第二輻射劑量輻射之該堤部層之一區域,該部分移除藉此提供圍繞該經曝光區域且具有該第一斜面及該第二斜面之該側壁,其中該釘紮點係在具有該等經遷移含氟化合物之該堤部層表面與該側壁之間的邊界處。The method of claim 1, wherein the forming the bank structure comprises: forming a bank layer by depositing a fluorinated photoresist solution on the surface layer; and baking to harden the bank layer, wherein The fluorine compound of the photoresist solution migrates to the surface of the bank layer during the baking to thereby increase the contact angle between the organic solution and the surface; the light patterning of the hardened bank layer includes: A first radiation dose irradiates a first area of the bank layer and a second radiation dose irradiates a second area of the bank layer, the second radiation dose is less than the first radiation dose; developing the bank layer to expose the surface The area of the layer and partially remove an area of the bank layer irradiated with the second radiation dose, the partial removal thereby providing the surrounding the exposed area with the first slope and the second slope A side wall, wherein the pinning point is at a boundary between the surface of the bank layer having the migrated fluorine-containing compounds and the side wall. 如請求項8之方法,其中:該光圖案化包括同時穿過第一遮罩及第二遮罩輻射該堤部層,其中該以該第一劑量輻射該第一區域包括穿過該第一遮罩及該第二遮罩之完全透射性區域輻射該第一區域,且該以該第二劑量輻射該第二區域包括穿過該第一遮罩及該第二遮罩中之每一者之至少部分透射性區域輻射該第二區域;及/或該光圖案化包括穿過具有部分透射性區及更具透射性區之遮罩輻射該堤部層,其中該以該第一劑量輻射該第一區域包括穿過該更具透射性區輻射該第一區域,且該以該第二劑量輻射該第二區域包括穿過該部分透射性區輻射該第二區域;及/或該方法包括在該表面層之一區上沈積反射體層,其中:該沈積該氟化光阻劑溶液將該氟化溶液沈積於該反射體層上及該表面層上;且該光圖案化包括穿過遮罩輻射該堤部層,其中該輻射該第一區域包括該第一區域吸收直接穿過該遮罩接收之該第一劑量之一部分且吸收自該第一遮罩接收並由該反射體層反射回至該第一區域中之劑量之一部分。The method of claim 8, wherein the light patterning includes radiating the bank layer through the first mask and the second mask simultaneously, and wherein irradiating the first region with the first dose includes passing through the first A completely transmissive area of the mask and the second mask radiates the first area, and the radiating the second area with the second dose includes passing through each of the first mask and the second mask At least a partially transmissive area radiates the second area; and / or the light patterning includes radiating the bank layer through a mask having a partially transmissive area and a more transmissive area, wherein the radiation is emitted at the first dose The first region includes radiating the first region through the more transmissive region, and irradiating the second region at the second dose includes radiating the second region through the partially transmissive region; and / or the method The method includes depositing a reflector layer on an area of the surface layer, wherein: the depositing the fluorinated photoresist solution deposits the fluorinated solution on the reflector layer and the surface layer; and the photo-patterning includes passing through a mask The cover radiates the bank layer, wherein the radiation covers the first area packet The first portion of the region directly absorbed through the mask receiving the first dose of the mask and is absorbed from the first receiving reflected by the reflector layer back to a portion of the first region of the dosage. 如請求項1、2、8及9中任一項之方法,其中該電子裝置係光電子裝置。The method according to any one of claims 1, 2, 8 and 9, wherein the electronic device is an optoelectronic device. 如請求項10之方法,其中該電子裝置係發光裝置或吸光裝置。The method of claim 10, wherein the electronic device is a light emitting device or a light absorbing device. 如請求項1、2、8及9中任一項之方法,其中該電子裝置係OLED且該有機溶液用於提供電洞注入層(HIL)。The method of any one of claims 1, 2, 8 and 9, wherein the electronic device is an OLED and the organic solution is used to provide a hole injection layer (HIL). 如請求項12之方法,其進一步包括在該可溶液處理層上及在該第一電極與該第二電極之間形成至少另一可溶液處理層,該另一可溶液處理層用於提供中間層(IL)及/或發光層(EL)。The method of claim 12, further comprising forming at least another solution-treatable layer on the solution-treatable layer and between the first electrode and the second electrode, the other solution-treatable layer for providing an intermediate Layer (IL) and / or light emitting layer (EL). 如請求項1、2、8及9中任一項之方法,其中:該有機溶液在沈積於該第一斜面及自該第一斜面延伸至該釘紮點之第二斜面區域中之至少一者上時之接觸角係10°或更小;及/或其中該有機溶液在沈積於自該釘紮點延伸遠離該第一斜面的該堤部結構之一區域上時之接觸角係50°或更大。The method according to any one of claims 1, 2, 8 and 9, wherein: the organic solution is deposited on at least one of the first bevel and a second bevel region extending from the first bevel to the pinning point. The contact angle at the time is 10 ° or less; and / or the contact angle at which the organic solution is deposited on an area of the bank structure extending away from the first slope from the pinning point is 50 ° Or greater. 一種包括具有表面層及該表面層上之界定井之堤部結構之基板之電子裝置,該堤部結構包括電絕緣材料且具有圍繞該表面層之一區域以藉此界定該井之側壁,該表面層區域包括第一電極及經配置以形成微腔之部分反射性層,且該裝置進一步包括第二電極及安置於該第一電極與該第二電極之間的半導電性材料,其中:該側壁具有自該表面層區域延伸之第一斜面及自該第一斜面延伸之第二斜面,其中該第二斜面比該第一斜面陡峭;且該裝置包括具有至少一個層之層結構,至少一個該層係可溶液處理層,該層結構具有該半導電性材料且安置於該第一電極與該第二電極之間,其中:至少一個該可溶液處理層具有在該第二斜面上與該第一斜面間隔開之點處之釘紮點,該可溶液處理層安置於該表面層區域上以及該側壁之該第一斜面及該第二斜面上。An electronic device including a substrate having a surface layer and a bank structure defining a well on the surface layer, the bank structure including an electrically insulating material and having a region surrounding the surface layer to thereby define a sidewall of the well, the The surface layer region includes a first electrode and a partially reflective layer configured to form a microcavity, and the device further includes a second electrode and a semi-conductive material disposed between the first electrode and the second electrode, wherein: The side wall has a first inclined plane extending from the surface layer region and a second inclined plane extending from the first inclined plane, wherein the second inclined plane is steeper than the first inclined plane; and the device includes a layer structure having at least one layer, at least A layer is a solution-treatable layer, the layer structure has the semi-conductive material and is disposed between the first electrode and the second electrode, wherein: at least one of the solution-treatable layer has The pinning points at the points where the first inclined plane is spaced apart, the solution-treatable layer is disposed on the surface layer region and the first inclined plane and the second inclined plane of the side wall. 如請求項15之電子裝置,其中該堤部結構包括至少一個光阻劑層。The electronic device of claim 15, wherein the bank structure includes at least one photoresist layer. 如請求項16之電子裝置,其中:該光阻劑層具有在該第二斜面上之該點且包括含氟化合物;及/或該堤部結構包括複數個光阻劑層,該光阻劑層具有該第一斜面;及/或該堤部結構包括具有該等含氟化合物以及該第一斜面及該第二斜面之該光阻劑層。The electronic device of claim 16, wherein: the photoresist layer has the point on the second slope and includes a fluorine-containing compound; and / or the bank structure includes a plurality of photoresist layers, the photoresist The layer has the first inclined surface; and / or the bank structure includes the photoresist layer having the fluorine-containing compounds and the first inclined surface and the second inclined surface. 如請求項15至17中任一項之電子裝置,其中該第一斜面具有相對於該表面層之小於或等於20度。The electronic device according to any one of claims 15 to 17, wherein the first inclined surface has a degree of less than or equal to 20 degrees with respect to the surface layer. 如請求項15至17中任一項之電子裝置,其中:該第一斜面延伸直至在與該第二斜面之邊界處小於300nm;及/或該側壁自該表面區域延伸以提供至少300nm之堤部結構厚度;及/或該第一斜面沿著該表面層延伸跨過至少1μm之長度。The electronic device of any one of claims 15 to 17, wherein: the first inclined plane extends until less than 300 nm at a boundary with the second inclined plane; and / or the sidewall extends from the surface region to provide a bank of at least 300 nm Part of the structure thickness; and / or the first inclined surface extends along the surface layer over a length of at least 1 μm. 如請求項15至17中任一項之電子裝置,其中該裝置係發光裝置,且其中該可溶液處理層包括用於提供電洞注入層(HIL)之有機半導電性材料。The electronic device according to any one of claims 15 to 17, wherein the device is a light emitting device, and wherein the solution-treatable layer includes an organic semiconductive material for providing a hole injection layer (HIL). 如請求項20之電子裝置,其中該發光裝置係OLED。The electronic device as claimed in claim 20, wherein the light emitting device is an OLED. 如請求項21之電子裝置,其中至少一個該可溶液處理層包括安置於用於提供該HIL之該材料上方之另一有機半導電性材料,且該另一有機半導電性材料用於提供中間層(IL)或發光層(EL)。The electronic device of claim 21, wherein at least one of the solution-treatable layers includes another organic semi-conductive material disposed above the material for providing the HIL, and the other organic semi-conductive material is for providing an intermediate Layer (IL) or light emitting layer (EL).
TW103128177A 2013-08-16 2014-08-15 Hydrophobic bank TWI634686B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
??1314655.0 2013-08-16
GBGB1314655.0A GB201314655D0 (en) 2013-08-16 2013-08-16 Hydrophobic bank

Publications (2)

Publication Number Publication Date
TW201513427A TW201513427A (en) 2015-04-01
TWI634686B true TWI634686B (en) 2018-09-01

Family

ID=49301786

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103128177A TWI634686B (en) 2013-08-16 2014-08-15 Hydrophobic bank

Country Status (5)

Country Link
JP (1) JP2015057772A (en)
KR (1) KR20150020140A (en)
CN (1) CN104377311B (en)
GB (1) GB201314655D0 (en)
TW (1) TWI634686B (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106207012B (en) * 2016-08-15 2018-07-06 京东方科技集团股份有限公司 Pixel print structure and preparation method thereof, display device and inkjet printing methods
CN106356396B (en) * 2016-11-24 2021-03-26 深圳市Tcl高新技术开发有限公司 Pixel Bank structure suitable for preparing display by printing process and preparation method thereof
CN108346677B (en) * 2017-07-17 2019-03-12 广东聚华印刷显示技术有限公司 Dot structure and preparation method thereof
CN109713021B (en) * 2019-01-18 2020-05-12 深圳市华星光电半导体显示技术有限公司 OLED display panel and preparation method thereof
US10741798B1 (en) 2019-01-18 2020-08-11 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Organic light emitting diode display panel and method of manufacturing same
US11038150B1 (en) 2020-01-30 2021-06-15 Sharp Kabushiki Kaisha QLED/OLED pixel having reflective cavity electrode configuration
US11152538B1 (en) 2020-04-03 2021-10-19 Sharp Kabushiki Kaisha High on-axis brightness and low color shift QD-LED pixel
US11264597B2 (en) 2020-06-22 2022-03-01 Sharp Kabushiki Kaisha Multiple QD-LED sub-pixels for high on-axis brightness and low colour shift
US11456443B2 (en) 2020-12-01 2022-09-27 Sharp Kabushiki Kaisha High on-axis brightness and low colour shift QD-LED pixel with equal layer thicknesses between colour pixels
US11785819B2 (en) 2021-04-01 2023-10-10 Sharp Kabushiki Kaisha Layers for improved extraction for transparent cathode emissive displays
US11871610B2 (en) 2021-05-13 2024-01-09 Sharp Kabushiki Kaisha Dual bank structure for improved extraction from an emissive layer
US11968858B2 (en) 2021-09-02 2024-04-23 Sharp Display Technology Corporation Display subpixels having multiple emissive areas with high aspect ratios

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200517008A (en) * 2003-11-11 2005-05-16 Seiko Epson Corp Electro-optical device and electronic apparatus
US20110140596A1 (en) * 2007-05-31 2011-06-16 Panasonic Corporation Organic el element and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009087998A (en) * 2007-09-27 2009-04-23 Sanyo Electric Co Ltd Semiconductor device
KR101172794B1 (en) * 2007-12-10 2012-08-09 파나소닉 주식회사 Organic EL Device, EL Display Panel, Method for Manufacturing the Organic EL Device and Method for Manufacturing the EL Display Panel
JP2010118509A (en) * 2008-11-13 2010-05-27 Panasonic Corp Light-emitting element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200517008A (en) * 2003-11-11 2005-05-16 Seiko Epson Corp Electro-optical device and electronic apparatus
US20110140596A1 (en) * 2007-05-31 2011-06-16 Panasonic Corporation Organic el element and manufacturing method thereof

Also Published As

Publication number Publication date
JP2015057772A (en) 2015-03-26
TW201513427A (en) 2015-04-01
CN104377311B (en) 2018-10-16
CN104377311A (en) 2015-02-25
KR20150020140A (en) 2015-02-25
GB201314655D0 (en) 2013-10-02

Similar Documents

Publication Publication Date Title
TWI634686B (en) Hydrophobic bank
KR102038817B1 (en) Organic electro-luminescent device and method of fabricating the same
CN108878503B (en) OLED display substrate, manufacturing method thereof, OLED display panel and display device
US9231211B2 (en) Method for forming a multicolor OLED device
EP3699961B1 (en) Display device
CN102106186B (en) Organic EL display panel and method for manufacturing same
JP5096648B1 (en) Organic EL display panel and manufacturing method thereof
KR101322310B1 (en) Organic light emitting display device and and method for fabricating the same
JP4990425B1 (en) Organic EL display panel and manufacturing method thereof
KR20090028513A (en) Organic EL element and its manufacturing method
US20190115402A1 (en) Pixel definition layer and manufacturing method thereof, display substrate, and display panel
CN107768412A (en) Display base plate and preparation method thereof and display panel
CN107681063A (en) Array base palte and preparation method thereof, display device
JP2011509498A (en) Backplane structure for electronic devices
WO2021136446A1 (en) Driving backplate and preparation method therefor, and display panel and display device
TWI624972B (en) Optoelectronic device and method of fabricating the same
KR102015847B1 (en) Organic electro-luminescent device
WO2020238892A1 (en) Array substrate and preparation method therefor, and display apparatus
CN111276499A (en) Display substrate, method for producing the same, and display device
CN111370590A (en) Display panel, preparation method thereof and display device
CN111223875A (en) Display panel, method for producing the same, and display device
KR101264865B1 (en) Method of fabricating organic electroluminescence display device
CN104538433A (en) Active-matrix organic light emission display substrate and manufacturing method thereof
CN110993645A (en) Display panel, preparation method thereof and display device
KR100498006B1 (en) Fabricating method of organic electroluminescence device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees