CN111276499A - Display substrate, method for producing the same, and display device - Google Patents

Abstract

Embodiments of the present invention provide a substrate for display, a method for preparing the same, and a display device, which relate to the field of display technology and can solve the problem of requiring more manufacturing processes when manufacturing a substrate for display. The substrate for display includes a substrate and is disposed in the The insulating layer on the substrate is arranged on a flat layer on the side of the insulating layer away from the substrate, the flat layer includes a positive photosensitive agent; the insulating layer has a first via hole; the flat layer is A groove is provided on the surface away from the insulating layer, the portion of the flat layer located under the groove has a second via hole, and the first via hole and the second via hole communicate with each other.

Description

Display substrate, method for producing the same, and display device

technical field

The present application relates to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.

Background technique

The top-gate TFT (Thin Film Transistor, thin film transistor) has the characteristics of a short channel, so the on-state current Ion can be effectively increased, so the display effect can be significantly improved and the power consumption can be effectively reduced. In addition, the overlapping area between the gate and the source and drain of the top-gate TFT is small, so that the generated parasitic capacitance is small, and the possibility of occurrence of defects such as GDS is also reduced. Since the top-gate TFT has the above-mentioned remarkable advantages, it has attracted more and more attention.

SUMMARY OF THE INVENTION

The embodiment of the present application adopts the following technical solutions:

In a first aspect, a display substrate is provided, comprising: a substrate, an insulating layer disposed on the substrate, and a flat layer disposed on a side of the insulating layer away from the substrate; the insulating layer has a first a via hole; the flat layer is provided with a groove on its surface away from the insulating layer, the part of the flat layer located under the groove has a second via hole, the first via hole and the The second via holes communicate with each other.

In some embodiments, the display substrate further includes: a thin film transistor disposed between the substrate and the insulating layer; a first electrode plate disposed on the bottom surface of the groove, disposed on the insulating layer a second electrode plate on the side close to the substrate; the first electrode plate passes through the second via hole and the first via hole and is electrically connected to the first electrode of the thin film transistor, and the second electrode The plate is electrically connected to the gate of the thin film transistor; wherein, the first electrode plate and the second electrode plate constitute two electrode plates of the capacitor.

In some embodiments, the depth of the groove is 80% to 95% of the thickness of the flat layer.

In some embodiments, an orthographic projection of an edge of the second via close to the substrate on the substrate is an orthographic projection of an edge of the first via away from the substrate on the substrate within the projection.

In some embodiments, an orthographic projection of an edge of the second via close to the substrate on the substrate is the same as an orthographic projection of an edge of the first via away from the substrate on the substrate Projection coincides.

In some embodiments, the display substrate further includes: an electrode, and a color filter layer disposed between the insulating layer and the flat layer; the electrode is connected to the first electrode plate and is on the same layer With the same material, the color filter layer includes a filter pattern; the orthographic projection of the electrode on the substrate and the orthographic projection of one of the filter patterns on the substrate have an overlapping area.

In some embodiments, the display substrate further includes: a metal pattern disposed between the substrate and the thin film transistor; an orthographic projection of the active layer of the thin film transistor on the substrate is on the metal The pattern is in an orthographic projection on the substrate; the metal pattern is electrically connected to the first electrode of the thin film transistor, and the metal pattern and the second electrode plate have an overlapping area.

In a second aspect, a display device is provided, including the above-mentioned display substrate.

In a third aspect, a method for preparing a display substrate is provided, comprising: sequentially forming a first thin film and a second thin film on the substrate, the second thin film comprising a positive photosensitive agent; masking the second thin film exposing and developing, to form grooves on the surface of the second film away from the first film, and to form second via holes on the part under the grooves of the second film to obtain a flat layer; The portion of the first film exposed by the second via hole is etched to form an insulating layer having the first via hole.

In some embodiments, the preparation method further includes: after forming the insulating layer, performing ashing treatment on the flat layer to obtain a processed flat layer.

Embodiments of the present invention provide a display substrate, a preparation method thereof, and a display device. The display substrate includes a substrate, an insulating layer disposed on the substrate, a flat layer disposed on a side of the insulating layer away from the substrate, and the flat layer Including a positive photosensitive agent; the insulating layer has a first via hole; the flat layer is provided with a groove on its surface away from the insulating layer, and the part of the flat layer located under the groove has a second via hole, the first via hole and The second via holes communicate with each other. Since in the embodiment of the present invention, the flattening layer includes a positive photosensitive agent, the flattening layer not only has the function of flattening, but also has the function of photoresist. Therefore, when the first via hole is formed on the insulating layer, it is not necessary to use the insulating layer. A layer of photoresist is coated thereon, and the groove, the first via hole and the second via hole can be formed by one patterning process, so that one mask exposure process can be reduced, that is, the manufacturing process can be simplified.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a liquid crystal display panel according to an embodiment of the present invention;

3 is a schematic structural diagram of an electroluminescent display panel according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram 1 of a display substrate according to an embodiment of the present invention;

FIG. 5 is a second structural schematic diagram of a display substrate according to an embodiment of the present invention;

FIG. 6 is an enlarged schematic diagram of part A in FIG. 5 according to the embodiment of the present invention;

FIG. 7 is a third structural schematic diagram of a display substrate provided by an embodiment of the present invention;

FIG. 8 is an enlarged schematic diagram of part B in FIG. 7 according to the embodiment of the present invention;

FIG. 9 is a schematic flowchart of a method for preparing a display substrate according to an embodiment of the present invention;

10 is a schematic structural diagram of a mask exposure process for a second film according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of forming a flat layer according to an embodiment of the present invention;

12 is a schematic structural diagram of forming an insulating layer according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a flat layer structure after a formation process according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

An embodiment of the present invention provides a display device, and the type of the display device is not limited, which may be a liquid crystal display device (Liquid Crystal Display, LCD for short) or an electroluminescence display device. In the case where the display device is an electroluminescence display device, the electroluminescence display device may be an organic electroluminescence display device (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescence display device (Quantum DotLight Emitting Diodes, abbreviated as OLED) QLED).

In addition, the display device provided by the embodiment of the present invention may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, navigator, etc., which is not limited in the embodiment of the present invention.

As shown in FIG. 1 , the main structure of the display device includes a frame 1 , a cover plate 2 , a display panel 3 , and other accessories such as a circuit board 4 . When the display device is a liquid crystal display device, the display device further includes a backlight assembly. Here, the display panel 3 may be a flexible display panel or a rigid display panel. In the case where the display panel 3 is a flexible display panel, the display device is a flexible display device.

The longitudinal section of the frame 1 is U-shaped, the display panel 3, the circuit board 4 and other accessories are all arranged in the frame 1, and the circuit board 4 is placed under the display panel 3 (ie the back, the side facing away from the display surface of the display panel 3). one side), the cover plate 2 is disposed on the side of the display panel 3 away from the circuit board 4 . When the display device is a liquid crystal display device, and the liquid crystal display device includes a backlight assembly, the backlight assembly is disposed between the display panel 3 and the circuit board 4 .

When the display device is a liquid crystal display device, the display panel 3 is a liquid crystal display panel. In some embodiments, as shown in FIG. 2 , the display panel 3 includes a display substrate 30 and a liquid crystal layer 31 disposed on the display substrate 30 ; the display substrate 30 includes a color filter layer 301 disposed on the substrate 300 In this case, the display substrate 30 is an array substrate, which may also be called a COA (Color filter on Array) substrate.

When the display device is an electroluminescence display device, the display panel 3 is an electroluminescence display panel. As shown in FIG. 3 , the display panel 3 includes a display substrate 30 and an encapsulation layer 32 for encapsulating the display substrate 30 . Here, the encapsulation layer 32 may be an encapsulation film or an encapsulation substrate. In some embodiments, as shown in FIG. 3 , the display substrate 30 includes a color filter layer 301 disposed on the substrate 300 . In this case, the display device is a bottom-emission display device.

The embodiment of the present invention further provides a display substrate 30, which can be applied to the above-mentioned display device. As shown in FIG. 4 , the display substrate 30 includes a substrate 300 , an insulating layer 302 disposed on the substrate 300 , a flat layer 303 disposed on the side of the insulating layer 302 away from the substrate 300 , and the flat layer 303 includes a positive photosensitive agent. The insulating layer 302 has a first via hole 3021, the flat layer 303 is provided with a groove 3031 on its surface away from the insulating layer 302, and the portion of the flat layer 303 located below the groove 3031 has a second via hole 3032. The via hole 3021 and the second via hole 3032 communicate with each other.

Here, the material of the insulating layer 302 may be an organic material or an inorganic material. The organic material is not limited, for example, the organic material may be PMMA (Polymethylmethacrylate, polymethyl methacrylate). The inorganic material is not limited, for example, the inorganic material may be one or more of SiNx (silicon nitride), SiOx (silicon oxide) or SiOxNy (silicon oxynitride).

As shown in FIG. 4 , the groove 3031 is defined as a portion of the flat layer 303 having a certain depth along the thickness direction of the flat layer 303 and a certain thickness on its surface close to the insulating layer 302 .

In the embodiment of the present invention, the flat layer 303 includes resin (Resin) in addition to the positive photosensitive agent. The resin is not limited, as long as the flattening layer 303 has a flattening effect. In some embodiments, the resin may be, for example, an organosiloxane resin. Since the organosiloxane resin has better leveling properties, the planarization layer 303 can have a good planarization effect.

It should be understood that since the flat layer 303 includes a positive photosensitive agent, during mask exposure, the flat layer 303 needs to be exposed in the area where the groove 3031 needs to be formed and the area where the second via hole 3032 needs to be formed (that is, the light can be It is irradiated through the light-transmitting area on the mask), and the rest of the area is blocked (that is, blocked by the non-light-transmitting area on the mask). In addition, referring to FIG. 3, it can be seen that the depth of the groove 3031 in the flat layer 303 is formed is smaller than the depth of forming the second via hole 3032, so half exposure is used in the area where the groove 3031 needs to be formed, and full exposure is performed in the area where the second via hole 3032 needs to be formed; grooves 3031 and second vias 3032), and the unexposed areas remain. Therefore, the grooves 3031 and the second vias 3032 can be formed by one mask exposure and development, and then the insulating layer 302 can be etched to form the first vias 3021, that is, the grooves 3031 can be formed by one patterning process, and the first through hole 3021 and second via hole 3032 .

On this basis, the positive photosensitive agent is not limited. The positive photosensitizer is a photoacid generator, such as Tert-Butylphenyliodonium Perfluorooctanesulfonate (TBI-PFOS), Triphenylsulfonium Perfluorobutanesulfonate (Triphenylsulfonium Perfluorobutanesulfonate) , TPS-PFBS) and so on. For example, the resin can be polyethylene (Polyethylene, PE for short), polyvinyl chloride (PVC for short), polystyrene (PS for short), polypropylene (PP for short) and ABS resin (Acrylonitrile Butadiene Styrene, referred to as ABC). In addition, the solvent may be, for example, ethylene glycol monoacetate, ethylene glycol methyl ether acetate, N-methylpyrrole, propylene glycol, ethylene glycol alkyl ether acetate, propylene glycol monomethyl ether acetate, acetic acid A combination of any one or more of ethoxyethyl ester, dimethoxyacetaldehyde, propylene glycol methyl ether acetate, 3-ethoxy ethyl propionate, propylene glycol methyl ether (PM) and ethylene glycol ethyl ether. This embodiment of the present invention does not limit this.

Based on the above, in the embodiment of the present invention, the flattening layer 303 includes a positive photosensitive agent, that is, the flattening layer 303 not only has the function of flattening, but also has the function of photoresist, so the first via hole is formed on the insulating layer 302 3021, there is no need to coat another layer of photoresist on the insulating layer 302, and the groove 3031, the first via hole 3021 and the second via hole 3032 can be formed by one patterning process, thus reducing one mask exposure ( Mask) process, which simplifies the manufacturing process.

In some embodiments, as shown in FIG. 5 , the display substrate 30 further includes a thin film transistor 304 disposed between the substrate 300 and the insulating layer 302 , a first electrode plate 305 disposed on the bottom surface of the groove 3031 , and The second electrode plate 306 disposed on the side of the insulating layer 302 close to the substrate 300; the first electrode plate 305 is electrically connected to the first electrode 3041 of the thin film transistor 304 through the second via hole 3032 and the first via hole 3021, and the second electrode The plate 306 is electrically connected to the gate electrode 3042 of the thin film transistor 304; wherein, the first electrode plate 305 and the second electrode plate 306 constitute two electrode plates of the capacitor.

The first electrode 3041 is not limited, and the first electrode 3041 may be a source electrode or a drain electrode. It should be understood that the thin film transistor 304 further includes a second electrode 3043, and when the first electrode 3041 is a source electrode, the second electrode 3043 is a drain electrode; when the first electrode 3041 is a drain electrode, the second electrode 3043 for the source.

As shown in FIG. 5, the source and drain are insulated from each other. The materials of the source and drain electrodes are not limited. The material of the source and drain electrodes may be copper-based metals, such as copper (Cu), copper-molybdenum alloy (Cu/Mo), copper-titanium alloy (Cu/Ti), copper-molybdenum-titanium alloy (Cu/Mo/Ti), Copper-molybdenum-tungsten alloy (Cu/Mo/W), copper-molybdenum-niobium alloy (Cu/Mo/Nb), etc.; /Ti), chromium-molybdenum-titanium alloy (Cr/Mo/Ti), or other suitable materials, which are not limited in the embodiment of the present invention.

It should be noted that when the first pole plate 305 and the second pole plate 306 constitute the two pole plates of the capacitor, the larger the facing area between the two pole plates, the smaller the distance between the two pole plates, That is, the capacitance formed by the capacitor is larger.

In some embodiments, the depth of the grooves 3031 is 80%˜95% of the thickness of the flat layer 303 .

Here, the depth of the groove 3031 may be, for example, 80%, 85%, 90%, or 95% of the thickness of the flat layer 303 .

In the embodiment of the present invention, since the depth of the groove 3031 is 80% to 95% of the thickness of the flat layer 303 , that is, the thickness of the flat layer 303 inside the groove 3031 is 30% of the thickness of the flat layer 303 outside the groove 3031 5% to 20%, that is, the distance between the first electrode plate 305 and the second electrode plate 306 is smaller, so that the capacitance formed by the first electrode plate 305 and the second electrode plate 306 can be larger, and the second electrode plate 306 can form a larger capacitance. The plate 306 is electrically connected to the gate electrode 3042 of the thin film transistor 304, so the capacitance finally loaded on the thin film transistor 304 is relatively large, so that the brightness of the light emitted by the light-emitting layer can be ensured.

Considering that if the depth of the grooves 3031 is set to be deep, for example, the depth of the grooves 3031 is 95% of the thickness of the flat layer 303 , that is, the thickness of the flat layer 303 inside the grooves 3031 is the flatness outside the grooves 3031 5% of the thickness of the layer 303, so the thickness of the flat layer 303 located in the groove 3031 is too thin, which further causes the lower surface of the first electrode plate 305 to be uneven, that is, the lower surface of the first electrode plate 305 will be uneven , and when the lower surface of the first pole plate 305 is uneven, it will affect the front facing area of the first pole plate 305 and the second pole plate 306, that is, affect the distance between the first pole plate 305 and the second pole plate 306 , which further affects the capacitance of the capacitor, thereby affecting the brightness of the light emitted by the light-emitting layer. If the depth of the groove 3031 is set to be shallow, for example, the depth of the groove 3031 is 80% of the thickness of the flat layer 303 , that is, the thickness of the flat layer 303 inside the groove 3031 is the thickness of the flat layer 303 outside the groove 3031 20% of the thickness, causing the thickness of the flat layer 303 located in the groove 3031 to be too thick, that is, the facing area of the first pole plate 305 and the second pole plate 306 is reduced, and the first pole plate 305 and the second pole plate The distance between 306 increases, resulting in a decrease in the capacitance generated by the capacitor, which ultimately results in a decrease in the brightness of the light emitted by the light-emitting layer. Based on this, in some embodiments, the depth of the groove 3031 is 90% of the thickness of the flat layer 303 , that is, the thickness of the flat layer 303 inside the groove 3031 is 10% of the thickness of the flat layer 303 outside the groove 3031 %.

As shown in FIG. 5 , the thin film transistor 304 further includes an active layer 3044 and an interlayer dielectric layer 3045 disposed between the first electrode 3041 , the second electrode 3043 and the active layer 3044 . The active layer 3044 includes a first conductor region 3044a, a second conductor region 3044b, and a channel region 3044c between the first conductor region 3044a and the second conductor region 3044b. As shown in FIG. 5 , the first electrode 3041 and the first conductor region 3044a are connected through via holes in the interlayer dielectric layer 3045 , and the second electrode 3042 and the second conductor region 3044b are connected through the via holes in the interlayer dielectric layer 3045 .

In some embodiments, the first electrode 3041 is a source electrode, and the first conductor region 3044a can also be referred to as a source region; the second electrode 3042 is a drain electrode, and the second conductor region 3044b can also be referred to as a drain region. In other embodiments, the first electrode 3041 is a drain electrode, and the first conductor region 3044a may also be referred to as a drain region; the second electrode 3042 is a source electrode, and the second conductor region 3044b may also be referred to as a source region.

As shown in FIG. 5 , the thin film transistor 304 further includes a gate insulating layer 3046 disposed between the active layer 3044 and the gate electrode 3042 .

Here, the material of the gate insulating layer 3046 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al2O3), aluminum nitride (AlN) or other suitable materials. In addition, the gate insulating layer 3046 may be formed by a physical vapor deposition method, a chemical vapor deposition method (Chemical Vapor Deposition, CVD for short), or a coating method.

In some embodiments, as shown in FIG. 5 , the display substrate 30 further includes an electrode 307 and a color filter layer 301 disposed between the insulating layer 302 and the flat layer 303 , and the color filter layer 301 includes a plurality of filter patterns . The electrode 307 is connected to the first electrode plate 305 and is of the same layer and material. The orthographic projection of the electrode 307 on the substrate 300 and the orthographic projection of a filter pattern on the substrate 300 have an overlapping area.

It should be understood that when the display substrate 30 is applied to the above-mentioned liquid crystal display panel, the electrode 307 can be, for example, a pixel electrode; when the display substrate 30 is applied to the above-mentioned electroluminescent display panel, the electrode 307 can be, for example, a pixel electrode. either anode or cathode.

In the embodiment of the present invention, the electrode 307 and the first electrode plate 305 are connected to the same layer and the same material, so the electrode 307 and the first electrode plate 305 can be formed at the same time, and pass through the first via hole 3021 and the second via hole 3032 It is electrically connected to the first electrode 3041 of the thin film transistor 304 .

As shown in FIG. 4 , FIG. 5 and FIG. 6 , FIG. 6 is an enlarged schematic view of part A in FIG. 5 . The orthographic projection of the edge of the second via 3032 close to the substrate 300 on the substrate 300 is within the orthographic projection of the edge of the first via 3021 away from the substrate 300 on the substrate 300 .

4 and 6, it can be seen that the edge of the second via hole 3032 has a protruding portion relative to the edge of the first via hole 3021, that is, the diameter of the second via hole 3032 is smaller than that of the first via hole 3021. Therefore, the electrode 307 and the first electrode plate 305 can be overlapped on the flat layer 303 through the first via hole 3021 and the second via hole 3032, so as to ensure the first electrode 307 and the first electrode plate 305 and the thin film transistor 304. Pole 3041 connected smoothly.

As shown in FIG. 7 and FIG. 8 , FIG. 8 is an enlarged schematic view of part B in FIG. 7 . The orthographic projection of the edge of the second via hole 3032 close to the substrate 300 on the substrate 300 coincides with the orthographic projection of the edge of the first via hole 3021 away from the substrate 300 on the substrate 300 .

Referring to FIG. 8 , it can be seen that the edges of the first via hole 3021 and the second via hole 3032 are relatively flat, so when the electrode 307 and the first electrode plate 305 are overlapped on the flat layer 303 , the electrode 307 and the first electrode can be avoided. The plate 305 is broken at the edges of the first via hole 3021 and the second via hole 3032 , thereby further ensuring that the electrode 307 and the first electrode plate 305 are smoothly connected to the first electrode 3041 of the thin film transistor 304 .

In some embodiments, as shown in FIGS. 5 and 7 , the display substrate 30 further includes a metal pattern 308 disposed between the substrate 300 and the thin film transistor 304 , and the metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304 . connected, and the metal pattern 308 and the second electrode plate 306 have an overlapping area, the orthographic projection of the active layer 3044 of the thin film transistor 304 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300 .

Here, the overlapping area between the metal pattern 308 and the second electrode plate 306 may be that the metal pattern 308 and the second electrode plate 306 partially overlap; or the metal pattern 308 and the second electrode plate 306 may completely overlap.

In the case where the metal pattern 308 and the second electrode plate 306 all overlap, for example, the orthographic projection of the second electrode plate 306 on the substrate 300 is within the orthographic projection of the active layer 3044 on the substrate, and because the active The orthographic projection of the layer 3044 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300 , so that the orthographic projection of the second plate 306 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300 . in the orthographic projection.

The material of the metal pattern 308 is not limited. The material of the metal pattern 308 may be, for example, an opaque metal or alloy such as aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mu).

In addition, in the embodiment of the present invention, one metal pattern 308 may cover the active layer 3044 of the thin film transistor 304 in one sub-pixel, and at this time, one metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304 in one sub-pixel It can also be that a metal pattern 308 covers the active layer 3044 of the thin film transistor 304 in a pixel, at this time a metal pattern 308 is electrically connected to the first pole 3041 of the thin film transistor 304 in a pixel, that is, the The first electrodes 3041 of the thin film transistors 304 share one metal pattern 308 .

When one metal pattern 308 covers the active layer 3044 of the thin film transistors 304 in one pixel, the first electrodes 3041 of the thin film transistors 304 in one pixel share one metal pattern 308, so that the metal patterns in one pixel can be simultaneously formed 308, so that the manufacturing process can be simplified.

Since the material of the active layer 3044 of the thin film transistor 304 is a semiconductor material, the performance of the semiconductor material will be unstable when exposed to light (eg, ambient light), resulting in negative drift of the thin film transistor 304, that is, the threshold voltage of the thin film transistor 304 will change. , thereby affecting the working performance of the thin film transistor 304 . In the embodiment of the present invention, since the orthographic projection of the active layer 3044 of the thin film transistor 304 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300 , that is, the metal pattern 308 covers the thin film transistor 304 Therefore, the active layer 3044 can be prevented from being affected by light, so that the stability of the thin film transistor 304 can be improved, and the working performance of the thin film transistor 304 can be improved. And the metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304, and the metal pattern 308 and the second electrode plate 306 have an overlapping area, so a capacitance can be generated between the metal pattern 308 and the second electrode plate 306, so that the capacitor can be Having a larger capacitance further ensures the brightness of the light emitted by the light-emitting layer.

It should be noted that, in order to prevent the short circuit caused by the metal pattern 308 contacting the first conductor region 3044a and the second conductor region 3044b in the active layer 3044, based on this, in some embodiments, the display substrate 30 further A buffer layer 309 disposed on the metal pattern 308 is included. On the one hand, the buffer layer 309 can planarize the metal pattern 308 ; on the other hand, the buffer layer 309 can prevent the metal pattern 308 from coming into contact with the active layer 3044 .

The embodiment of the present invention also provides a method for preparing the display substrate 30, which can be used for preparing the above-mentioned display substrate 30. As shown in FIG. 9 , the preparation method of the display substrate 30 includes:

S100 , forming a first thin film 20 and a second thin film 21 on the substrate 300 in sequence, and the first thin film 21 includes a positive photosensitive agent.

It should be noted that, in the embodiment of the present invention, before forming the first thin film 20 and the second thin film 30, the preparation method of the display substrate 30 further includes: sequentially depositing patterning on the substrate 300 to form a metal pattern 308, depositing to form a buffer layer 309 , deposition patterning to form the pattern of the active layer 3044 and the formation of the complete thin film transistor 304 . Here, the method for forming the complete thin film transistor 304 can be based on the prior art, and details are not repeated here.

For example, it may further include: forming a color filter layer 301 , that is, forming a plurality of filter patterns of different colors.

When the material of the first thin film 20 is an organic material, the first thin film 20 and the second thin film 21 can be formed by using an ink jet printing process (Ink JetPrinter, IJP for short). When the material of the first thin film 20 is an inorganic material, the first thin film 20 can be formed by chemical vapor deposition, and the second thin film 21 can be formed by an inkjet printing process. Alternatively, the first thin film 20 and the second thin film 21 may also be formed by a coating method.

S101 , performing mask exposure and development on the second film 21 to form a groove 3031 on the surface of the second film 21 away from the first film 20 , and to form a second through-hole on the part under the groove 3031 of the second film 21 . Hole 3032, resulting in flat layer 303.

As shown in FIG. 10 , since the flat layer 303 includes a positive photosensitive agent, when performing mask exposure on the second film 21 , half-exposure is used in the area where the groove 3031 needs to be formed, and half exposure is used in the area where the second via hole 3032 needs to be formed. The area is fully exposed. After mask exposure, a developing process is performed on the second film 21. As shown in FIG. 11, all the fully exposed areas in the second film 21 are removed by development, and about 90% of the upper part of the half exposed area is removed by development, thereby forming grooves 3031 and the second via 3032.

It should be noted that half-exposure is used in the area where the groove 3031 needs to be formed, and during the half-exposure, the transmittance of the mask is inversely proportional to the thickness of the bottom of the groove 3031, that is, when the thickness of the bottom of the groove 3031 is the flat layer 303 When the thickness is 5% to 20%, the transmittance of the mask plate at this time is 80% to 95%.

S102 , etching the portion of the first film 20 exposed by the second via hole 3032 to form the insulating layer 302 having the first via hole 3021 .

As shown in FIG. 12 , first via holes 3021 are formed after an etching process (HF wet etching) is performed on the first thin film 20 . Here, the edge of the second via hole 3032 is convex relative to the edge of the first via hole 3021 .

In some embodiments, as shown in FIG. 9 , the preparation method of the display substrate 30 further includes;

S103 , after the insulating layer 302 is formed, ashing is performed on the flat layer 303 to obtain the processed flat layer 303 .

As shown in FIG. 13 , performing a slight ashing process on the flat layer 303 can make the surface of the groove 3031 more flat, and can eliminate the protruding edge ( That is, the tip angle of the second via hole 3032 ), in this way, the problem that the electrode 307 and the first electrode plate 305 are broken at the edges of the first via hole 3021 and the second via hole 3032 can be avoided, thereby further ensuring that The electrode 307 and the first electrode plate 305 are smoothly connected to the first electrode 3041 of the thin film transistor 304 .

In the embodiment of the present invention, since the flat layer 303 includes a positive photosensitive agent, the halftone mask combined with the HF wet etching process can reduce one mask exposure process, so that the above-mentioned grooves 3031, 3031, The first via hole 3021 and the second via hole 3032 simplify the fabrication process.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (10)

1. A substrate for display, comprising:

a substrate;

an insulating layer disposed on the substrate, the insulating layer having a first via;

the flat layer is arranged on one side, far away from the substrate, of the insulating layer and comprises a positive photosensitive agent, a groove is formed in the surface, far away from the insulating layer, of the flat layer, a second through hole is formed in the portion, located below the groove, of the flat layer, and the first through hole is communicated with the second through hole.

2. The substrate for display use according to claim 1, further comprising:

a thin film transistor disposed between the substrate and the insulating layer;

the first polar plate is arranged on the bottom surface of the groove, penetrates through the second through hole and the first through hole and is electrically connected with the first pole of the thin film transistor;

the second polar plate is arranged on one side, close to the substrate, of the insulating layer and is electrically connected with the grid electrode of the thin film transistor;

wherein the first plate and the second plate form two plates of a capacitor.

3. The substrate according to any one of claims 1 and 2, wherein the depth of the groove is 80 to 95% of the thickness of the planarization layer.

4. The substrate for display use according to claim 1,

an orthographic projection of the edge of the second via hole close to the substrate on the substrate is within an orthographic projection of the edge of the first via hole far away from the substrate on the substrate.

5. The substrate for display use according to claim 4,

the orthographic projection of the edge of the second through hole close to the substrate on the substrate is coincident with the orthographic projection of the edge of the first through hole far away from the substrate on the substrate.

6. The substrate for display according to claim 2, further comprising:

an electrode; the electrode is connected with the first polar plate and is made of the same material on the same layer;

and a color filter layer disposed between the insulating layer and the planarization layer; the color filter layer includes a plurality of filter patterns;

the orthographic projection of the electrode on the substrate and the orthographic projection of one of the filter patterns on the substrate have an overlapping region.

7. The substrate for display according to claim 2, further comprising:

a metal pattern disposed between the substrate and the thin film transistor;

an orthographic projection of an active layer of the thin film transistor on the substrate is within an orthographic projection of the metal pattern on the substrate;

the metal pattern is electrically connected to a first electrode of the thin film transistor, and the metal pattern and the second electrode have an overlapping area.

8. A display device comprising the substrate for display according to any one of claims 1 to 7.

9. A method for manufacturing a substrate for display, comprising:

sequentially forming a first film and a second film on a substrate, the second film including a positive type photosensitizer;

carrying out mask exposure and development on the second film to form a groove on the surface of the second film far away from the first film, and forming a second through hole at the part under the groove of the second film to obtain a flat layer;

and etching the part of the first film exposed by the second via hole to form an insulating layer with a first via hole.

10. The method of manufacturing according to claim 9, further comprising:

after the insulating layer is formed, ashing treatment is performed on the flat layer to obtain a treated flat layer.

Images