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TWI624004B - 包含超晶格空乏層堆疊之半導體元件及其相關方法 - Google Patents

包含超晶格空乏層堆疊之半導體元件及其相關方法 Download PDF

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TWI624004B
TWI624004B TW103140684A TW103140684A TWI624004B TW I624004 B TWI624004 B TW I624004B TW 103140684 A TW103140684 A TW 103140684A TW 103140684 A TW103140684 A TW 103140684A TW I624004 B TWI624004 B TW I624004B
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superlattice
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羅勃Ｊ 米爾斯
竹內秀樹
歐文 特勞特曼
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米爾斯科技有限公司
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Abstract

一半導體元件可包含在一底材上面之超晶格層與主體半導體層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，且該超晶格層之每一層群組包括複數個堆疊之基底半導體單層，其界定出一基底半導體部份與受限在相鄰之基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含超晶格層與主體半導體層之該交替堆疊之一上部主體半導體層中之分隔之源極區與汲極區，以及該上部主體半導體層上面位於該些分隔之源極區與汲極區間之一閘極。

Description

包含超晶格空乏層堆疊之半導體元件及其相關方法
本申請案主張2013年11月22日申請之美國臨時專利申請案第61/907,626號之優先權，該臨時申請案之完整內容茲以此述及方式納入本說明書。
本發明與半導體領域有關，更詳細而言，與包含超晶格之半導體元件及相關方法有關。
利用諸如增強電荷載子之遷移率(mobility)增進半導體元件性能之相關結構及技術，已多有人提出。例如，Currie等人之美國專利申請案第2003/0057416號揭示了矽、矽-鍺及鬆弛矽之應變材料層，其亦包含原本會在其他方面導致性能劣退的無雜質區(impurity-free zones)。此等應變材料層在上部矽層中所造成的雙軸向應變(biaxial strain)會改變載子的遷移率，從而得以製作較高速與/或較低功率的元件。Fitzgerald等人的美國專利申請公告案第2003/0034529號則揭示了同樣以類似的應變矽技術為基礎的CMOS反向器。
Takagi的美國專利第6,472,685 B2號揭示了一半導體元件，其包含夾在矽層間的一層矽與碳層，以使其第二矽層的導帶及價帶承受伸張應變(tensile strain)。這樣，具有較小有效質量(effective mass)且已由施加於閘電極上的電場所誘發的電子，便會被限制在其第二矽層內，因此，即可認定其n通道MOSFET具有較高的遷移率。
Ishibashi等人的美國專利第4,937,204號揭示了一超晶格，其中包含一複數層，該複數層少於八個單層(monolayer)且含有一部分(fractional)或雙元(binary)半導體層或一雙元化合物半導體層，該複數層係交替地以磊晶成長方式生長而成。其中的主電流方向係垂直於該超晶格之各層。
Wang等人的美國專利第5,357,119號揭示了一矽-鍺短週期超晶格，其經由減少超晶格中的合金散射(alloy scattering)而達成較高遷移率。依據類似的原理，Candelaria的美國專利第5,683,943號揭示了具較佳遷移率之MOSFET，其包含一通道層，該通道層包括矽與一第二材料之一合金，該第二材料以使該通道層處於伸張應力下的百分比替代性地存在於矽晶格中。
Tsu的美國專利第5,216,262號揭示了一量子井結構，其包括兩個能障區(barrier region)及夾於其間的一磊晶生長半導體薄層。每一能障區各係由厚度範圍大致在二至六個交疊之SiO2/Si單層所構成。能障區間則另夾有厚得多之一矽區段。
在2000年9月6日線上發行的應用物理及材料科學及製程(Applied Physics and Materials Science & Processing)pp.391-402中，Tsu 於一篇題為「矽質奈米結構元件中之現象」(Phenomena in silicon nanostructure devices)的文章中揭示了矽及氧之半導體-原子超晶格(semiconductor-atomic superlattice,SAS)。此矽/氧超晶格結構被揭露為對矽量子及發光元件有用。其中特別揭示如何製作並測試一綠色電輝光二極體(electroluminescence diode)結構。該二極體結構中的電流流動方向是垂直的，亦即，垂直於SAS之層。該文所揭示的SAS可包含由諸如氧原子等被吸附物種(adsorbed species)及CO分子所分開的半導體層。在被吸附之氧單層以外所生長的矽，被描述為具有相當低缺陷密度之磊晶層。其中的一種SAS結構包含1.1nm厚之一矽質部份，其約為八個原子層的矽，而另一結構的矽質部份厚度則有此厚度的兩倍。在物理評論通訊(Physics Review Letters)，Vol.89,No.7(2002年8月12日)中，Luo等人所發表的一篇題為「直接間隙發光矽之化學設計」(Chemical Design of Direct-Gap Light-Emitting Silicon)的文章，更進一步地討論了Tsu的發光SAS結構。
已公告之Wang,Tsu及Lofgren等人的國際申請案WO 02/103,767 A1號揭示了薄的矽與氧、碳、氮、磷、銻、砷或氫的一能障建構區塊，其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度(four orders of magnitude)。其絕緣層/能障層容許低缺陷磊晶矽挨著絕緣層而沉積。
已公告之Mears等人的英國專利申請案第2,347,520號揭示，非週期性光子能帶間隙(aperiodic photonic band-gap,APBG)結構可應用於電子能帶間隙工程(electronic bandgap engineering)中。詳細而言，該申請案揭示，材料參數(material parameters)，例如能帶最小值的位置、有 效質量等等，皆可加以調節，以獲致具有所要能帶結構特性之新非週期性材料。其他參數，諸如導電性、熱傳導性及介電係數(dielectric permittivity)或導磁係數(magnetic permeability)，則被揭露亦有可能被設計於材料之中。
雖有此等結構所提供之優點，但對於將先進半導體材料與各種半導體元件結合而言，進一步發展是可能需要的。
一種製作半導體元件之方法可包含在一底材上面形成超晶格層與主體半導體層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，該超晶格層之每一層群組包括複數個堆疊之基底半導體單層，其界定出一基底半導體部份與受限在相鄰之基底半導體部份之一晶格內之至少一非半導體單層。該方法亦可包含在超晶格層與主體半導體層之該交替堆疊之一上部主體半導體層中形成分隔之源極區與汲極區，以及在該上部主體半導體層上面於該些分隔之源極區與汲極區間形成一閘極。
更詳細而言，該方法可更包括形成至少一淺溝槽隔絕(STI)區使之延伸穿過超晶格層與主體半導體層之該交替堆疊並進入該底材。此外，該方法亦可包含以交替之摻雜物導電性類型摻雜各別超晶格之間之主體層。
作為示例，每一基底半導體部分可包括矽、鍺等等。同樣作為示例，該至少一非半導體單層可包括由氧、氮、氟及碳-氧所組成群組中選定之一非半導體。形成該閘極可包括在該上部主體半導體層上面於該些分隔之源極區與汲極區之間形成一氧化物層，以及形成覆於該氧化物 層上方之一閘電極。此外，來自每一超晶格層之相對基底半導體部分之至少一些半導體原子，係透過該些相對基底半導體部分間之非半導體層，以化學方式鍵結在一起。
相關之一半導體元件可包含一底材上面之超晶格層與主體半導體層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，該超晶格層之每一層群組包括複數個堆疊之基底半導體單層，其界定出一基底半導體部份與受限在相鄰之基底半導體部份之一晶格內之至少一非半導體單層。該半導體元件可更包含超晶格層與主體半導體層之該交替堆疊之一上部主體半導體層中之分隔之源極區與汲極區，以及該上部主體半導體層上面位於該些分隔之源極區與汲極區間之一閘極。
25、25’‧‧‧超晶格
45a~45n、45a’~45n’‧‧‧層群組
46、46’‧‧‧基底半導體單層
46a~46n、46a’~46n’‧‧‧基底半導體部份
50、50’‧‧‧能帶修改層
52、52’‧‧‧頂蓋層
100‧‧‧半導體元件
105‧‧‧矽底材
106、109‧‧‧源極
107、110‧‧‧汲極
108、111‧‧‧通道區
112、115‧‧‧P型矽層
113、114‧‧‧N型矽層
116‧‧‧上部半導體層
117‧‧‧磊晶矽層
120‧‧‧STI區
121‧‧‧氧化物層
122‧‧‧閘電極
125‧‧‧超晶格層
圖1為依照本發明之一半導體元件所用一超晶格之放大示意剖視圖。
圖2為圖1所示超晶格之一部分之透視示意原子圖。
圖3為依照本發明之一超晶格之另一實施方式之放大示意剖視圖。
圖4A為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從迦碼點(G)計算所得能帶結構之圖。
圖4B為習知技術之主體矽及圖1~2所示之4/1矽/氧超晶格兩者從Z點計算所得能帶結構之圖。
圖4C為習知技術之主體矽及圖3所示之5/1/3/1矽/氧超 晶格兩者從迦碼點與Z點計算所得能帶結構之圖。
圖5為包含依照一示例性實施例之一超晶格空乏層堆疊之一平面式CMOS元件之剖視圖。
圖6~8為描繪一種製作圖5之平面式CMOS元件之一系列剖視圖。
圖9為對應於圖5~8所繪處理步驟之流程圖。
茲參考本發明說明書所附圖式詳細說明本發明，圖式中所示者為本發明之較佳實施方式。不過，本發明仍可以許多不同形式實施，因此本發明之範疇不應解釋為僅限於本說明書所述實施方式。相反的，這些實施方式之提供，僅是為了使本發明所揭示之發明內容更為完整詳盡，並使熟習本發明所屬技術領域者能夠完全瞭解本發明之範疇。在本說明書及圖式各處，相同圖式符號係指相同元件，而撇號(’)則係用以標示不同實施方式中之類似元件。。
本發明與在原子或分子等級上控制半導體材料之特性有關。進一步而言，本發明與用於半導體元件之改進材料之識別、形成及使用有關。
申請人之理論認為(但申請人並不欲受此理論所拘束)，本說明書所說明之超晶格結構可減少電荷載子之有效質量，並由此而帶來較高之電荷載子遷移率。有效質量之各種定義在本發明所屬技術領域之文獻中已有說明。為衡量有效質量之改善程度，申請人分別為電子及電 洞使用了「導電性反有效質量張量」(conductivity reciprocal effective mass tensor)及： 為電子之定義，且： 為電洞之定義，其中f為費米-狄拉克分佈(Fermi-Dirac distribution)，EF為費米能量(Fermi energy)，T為溫度，E(k,n)為電子在對應於波向量k及第n個能帶狀態中的能量，下標i及j係指直交座標x，y及z，積分係在布里羅因區(Brillouin zone，B.Z.)內進行，而加總則是在電子及電洞的能帶分別高於及低於費米能量之能帶中進行。
申請人對導電性反有效質量張量之定義為，一材料之導電性反有效質量張量之對應分量之值較大者，其導電性之張量分量(tensorial component)亦較大。申請人再度提出理論(但並不欲受此理論所拘束)認為，本說明書所述之超晶格可設定導電性反有效質量張量之值，以增進材料之導電性，例如電荷載子傳輸之典型較佳方向。適當張量項數之倒數，在此稱為導電性有效質量。換句話說，若要描述半導體材料結構的特性，如上文所述，在載子預定傳輸方向上計算出電子/電洞之導電性有效質量，便可用於分辨出較佳之材料。
申請人已辨識出可用於半導體元件之改進材料或結 構。更具體而言，申請人所辨識出之材料或結構所具有之能帶結構，其電子及/或電洞之適當導電性有效質量之值，實質上小於對應於矽之值。這些結構除了有較佳遷移率之特點外，其形成或使用之方式，亦使其得以提供有利於各種不同元件類型應用之壓電、焦電及/或鐵電特性，下文將進一步討論之。
參考圖1及圖2，該些材料或結構之形式為一超晶格25，該超晶格25之結構在原子或分子等級上受到控制，且可應用原子或分子層沉積之已知技術加以形成。該超晶格25包含複數個堆疊排列之層群組45a~45n，如圖1之示意剖視圖所示。
如圖所示，超晶格25之每一層群組45a~45n包含複數個堆疊之基底半導體單層46，其界定出各別之基底半導體部份46a~46n與其上之一能帶修改層50。為清楚呈現起見，該能帶修改層50於圖1中以雜點表示。
如圖所示，該能帶修改層50包含一非半導體單層，其係受限在相鄰之基底半導體部份之一晶格內。「受限在相鄰之基底半導體部份之一晶格內」一語，係指來自相對之基底半導體部分46a~46n之至少一些半導體原子，透過該些相對基底半導體部分間之非半導體單層50，以化學方式鍵結在一起，如圖2所示。一般而言，此一組構可經由控制以原子層沉積技術沉積在半導體部分46a~46n上面之非半導體材料之量而成為可能，這樣，可用之半導體鍵結位置便不會全部(亦即非完全或低於100%之涵蓋範圍)被連結至非半導體原子之鍵結佔滿，下文將進一步討論之。因此，當更多半導體材料單層46被沉積在一非半導體單層50上面或上方時， 新沉積之半導體原子便可填入該非半導體單層下方其餘未被佔用之半導體原子鍵結位置。
在其他實施方式中，使用超過一個非半導體單層是可能的。應注意的是，本說明書提及非半導體單層或半導體單層時，係指該單層所用材料若形成於主體，會是非半導體或半導體。亦即，一種材料(例如矽)之單一單層所顯現之特性，並不必然與形成於主體或相對較厚層時所顯現之特性相同，熟習本發明所屬技術領域者當可理解。
申請人之理論認為(但申請人並不欲受此理論所拘束)，能帶修改層50與相鄰之基底半導體部份46a~46n，可使該超晶格25在平行層之方向上，具有較原本為低之電荷載子適當導電性有效質量。換一種方向思考，此平行方向即正交於堆疊方向。該能帶修改層50亦可使該超晶格25具有一般之能帶結構，同時有利地發揮作為該超晶格垂直上下方之多個層或區域間之絕緣體之作用。
再者，此超晶格結構亦可有利地作為該超晶格25垂直上下方多個層之間之摻雜物及/或材料擴散之阻擋。因此，這些特性可有利地允許該超晶格25為高K值介電質提供一界面，其不僅可減少高K值材料擴散進入通道區，還可有利地減少不需要之散射效應，並改進裝置行動性，熟習本發明所屬技術領域者當可理解。
本發明之理論亦認為，包含該超晶格25之半導體元件可因為較原本為低之導電性有效質量，而享有較高之電荷載子遷移率。在某些實施方式中，因為本發明而實現之能帶工程，該超晶格25可進一步具有對諸如光電元件等尤其有利之實質上之直接能帶間隙。
如圖所示，該超晶格25亦包含一上部層群組45n上面之一頂蓋層52。該頂蓋層52可包含複數個基底半導體單層46。該頂蓋層52可具有介於2至100個基底半導體單層，較佳者為介於10至50個單層。
每一基底半導體部分46a~46n可包含由IV族半導體、III-V族半導體及II-VI族半導體所組成之群組中選定之一基底半導體。當然，IV族半導體亦包含IV-IV族半導體，熟習本發明所屬技術領域者當可理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
每一能帶修改層50可包含由，舉例而言，氧、氮、氟、碳及碳-氧所組成之群組中選定之一非半導體。該非半導體亦最好具有在沈積下一層期間保持熱穩定之特性，以從而有利於製作。在其他實施方式中，該非半導體可為相容於給定半導體製程之另一種無機或有機元素或化合物，熟習本發明所屬技術領域者當能理解。更詳細而言，該基底半導體可包含，舉例而言，矽及鍺當中至少一者。
應注意的是，「單層」一詞在此係指包含一單一原子層，亦指包含一單一分子層。亦應注意的是，經由單一單層所提供之能帶修改層50，亦應包含層中所有可能位置未完全被佔據(亦即非完全或低於100%之涵蓋範圍)之單層。舉例來說，參照圖2之原子圖，其呈現以矽作為基底半導體材料並以氧作為能帶修改材料之一4/1重複結構。在圖示之實施例中，氧原子之可能位置僅有一半被佔據。
在其他實施方式及/或使用不同材料的情況中，則不必然是二分之一的佔據情形，熟習本發明所屬技術領域者當能理解。事實上， 熟習原子沈積技術領域者當能理解，即便在此示意圖中亦可看出，在一給定單層中，個別的氧原子並非精確地沿著一平坦平面排列。舉例來說，較佳之佔據範圍是氧的可能位置有八分之一至二分之一被填滿，但在特定實施方式中其他佔據範圍亦可使用。
由於矽及氧目前廣泛應用於一般半導體製程中，故製造商將能夠立即應用本說明書所述之材質。原子沉積或單層沉積亦是目前廣泛使用之技術。因此，結合有本發明之超晶格25之半導體元件，可立即加以採用並實施，熟習本發明所屬技術領域者當能理解。
申請人之理論認為(但申請人並不欲受此理論所拘束)，就一超晶格而言，例如矽/氧超晶格，矽單層之數目最好為七層或更少，以使該超晶格之能帶在各處皆為共同或相對均勻，以實現所欲之優點。。圖1及圖2所示之矽/氧4/1重複結構，已經過模型化以表示電子及電洞在X方向上之較佳遷移率。舉例而言，電子(就主體矽而言具等向性)之計算後導電性有效質量為0.26，而X方向上的4/1矽/氧超晶格之計算後導電性有效質量則為0.12，兩者之比為0.46。同樣的，在電洞之計算結果方面，主體矽之值為0.36，該4/1矽/氧超晶格之值則為0.16，兩者之比為0.44。
雖然此種方向上優先(directionally preferential)之特點可有利於某些半導體元件，其他半導體元件亦可得益於遷移率在平行於層群組之任何方向上更均勻之增加。電子及電洞兩者之遷移率同時增加，或僅其中一種電荷載子遷移率之增加，亦皆可有其好處，熟習本發明所屬技術領域者當可理解。
該超晶格25之4/1矽/氧實施方式之較低導電性有效質 量，可不到非超晶格25者之導電性有效質量之三分之二，且此情形就電子及電洞而言皆然。當然，該超晶格25可更包括至少一種類型之導電性摻雜物在其中，熟習本發明所屬技術領域者當能理解。
茲另參考圖3說明依照本發明之具有不同特性之超晶格25’之另一實施方式。在此實施方式中，其重複模式為3/1/5/1。更詳細而言，最底下的基底半導體部份46a’有三個單層，第二底下的基底半導體部份46b’則有五個單層。此模式在整個超晶格25’重複。每一能帶修改層50’可包含一單一單層。就包含矽/氧之此種超晶格25’而言，其電荷載子遷移率之增進，係獨立於該些層之平面之定向。圖3中其他元件在此未提及者，係與前文參考圖1所討論者類似，故不再重複討論。
在某些元件實施方式中，其超晶格之每一基底半導體部份可為相同數目之單層之厚度。在其他實施方式中，其超晶格之至少某些基底半導體部份可為相異數目之單層之厚度。在另外的實施方式中，其超晶格之每一基底半導體部份可為相異數目之單層之厚度。
圖4A~4C呈現應用密度功能理論(Density Functional Theory,DFT)計算出之能帶結構。在本發明所屬技術領域中廣為習知的是，DFT通常會低估能帶間隙之絕對值。因此，間隙以上的所有能帶可利用適當之「剪刀形更正」(scissors correction)加以偏移。不過，能帶的形狀則是公認遠較為可靠。縱軸之能量應從此一角度解釋之。
圖4A呈現主體矽(以實線表示)及圖1之4/1矽/氧超晶格25(以虛線表示)兩者由迦碼點(G)計算出之能帶結構。圖中該些方向係指該4/1矽/氧結構之單位晶格(unit cell)而非指矽之一般單位晶格，雖然圖 中之方向(001)確實對應於一般矽單位晶格之方向(001)，並因此而顯示出矽導帶最小值之預期位置。圖中方向(100)及方向(010)係對應於一般矽單位晶格之方向(110)及方向(-110)。熟習本發明所屬技術領域者當可理解，圖中之矽能帶係被摺疊收攏，以便在該4/1矽/氧結構之適當反晶格方向(reciprocal lattice directions)上表示。
由圖中可見，與主體矽相較，該4/1矽/氧結構之導帶最小值係位於迦碼點(G)，而其價帶最小值則出現在方向(001)上布里羅因區之邊緣，吾人稱為Z點之處。吾人亦可注意到，與矽之導帶最小值曲率比較下，該4/1矽/氧結構之導帶最小值之曲率較大，此係因額外氧層引入之微擾(perturbation)造成能帶分裂(band splitting)之故。
圖4B呈現主體矽(實線)及該4/1矽/氧超晶格25(虛線)兩者由Z點計算出之能帶結構。此圖描繪出價帶在方向(100)上之增加曲率。
圖4C呈現主體矽(實線)及圖3之5/1/3/1矽/氧超晶格25’(虛線)兩者由迦碼點及Z點計算出之能帶結構之曲線圖。由於該5/1/3/1矽/氧結構之對稱性，在方向(100)及方向(010)上計算出之能帶結構是相當的。因此，在平行於各層之平面中，亦即垂直於堆疊方向(001)上，導電性有效質量及遷移率可預期為等向性。請注意，在該5/1/3/1矽/氧之實施例中，導帶最小值及價帶最大值兩者皆位於或接近Z點。
雖然曲率增加是有效質量減少的一個指標，但適當的比較及判別可經由導電性反有效質量張量之計算而進行。此使得本案申請人進一步推論，該5/1/3/1超晶格25’實質上應為直接能帶間隙。熟習本發明所屬技術領域者當可理解，光躍遷(optical transition)之適當矩陣元素(matrix element)是區別直接及間接能帶間隙行為之另一指標。
吾人可使用前述方式為特定目的選出具有改進能帶結構之材料。參考圖5，圖中所繪之半導體元件100實施例係一CMOS元件(其左邊設有一PMOS電晶體，右邊設有一NMOS電晶體)，在該半導體元件100中可使用複數個超晶格材料層125，以在矽底材105上面形成一各別「類埋置氧化物(quasi-BOX)」結構，使之位於該PMOS電晶體之源極106、汲極107及通道區108與該NMOS電晶體之源極109、汲極110及通道區111之下方。更詳細而言，每一類埋置氧化物包括垂直方向上分隔之一系列超晶格層125，該些超晶格層之間堆疊有若干區或層112~115，該些區或層為一種主體半導體材料(例如矽)並包含交替之摻雜物類型。在圖所示之實施例中，該NMOS堆疊包含該底材105上面之一底部超晶格層125、該底部超晶格層上面之一N型矽層114、該N型矽層上面之一中間超晶格層、該中間超晶格層上面之一P型矽層115，以及該P型矽層上面之一上部超晶格層。就該PMOS堆疊而言，如圖所示，其P型矽層112位於底部，其N型矽層113則位於頂部。
就該些通道區108，111及源極區106，109與汲極區107，110被界定在其中之上部半導體層116(圖6)而言，其如前文所述，可有利地以磊晶方式生長在上部超晶格層125之頂部上面。然而，在某些實施方式中，如有需要，通道可部分或全部位於該上部超晶格層中。此一類埋置氧化物結構在概念上可被認為發揮類似於一埋置氧化物層之功能，但該類埋置氧化物堆疊在這裡還提供一嵌入式P-N接面之額外益處，以為該些通道區108，111之進一步電性隔絕提供一空乏層，熟習本發明所屬技術領域者當 可理解。因此，類埋置氧化物空乏層堆疊可在不同應用中使用，例如，在諸如部分空乏(PD)或完全空乏(FD)之SOI元件中作為一SOI層或埋置氧化物層之替代。
茲參考圖6~9說明一種製作該半導體元件100之示例性方法。從方框201開始，在該矽底材105上面可形成複數個全覆式(blanket)超晶格層125，並在該些超晶格層之間形成插入之磊晶矽層117。接著可進行方框202之STI模組，以在NMOS與PMOS電晶體之間形成該些STI區120。該STI處理可包含，舉例而言，在所欲位置蝕刻出一溝槽使之穿過該三個超晶格層125、墊氧化(pad oxidation)、襯墊層氧化(liner oxidation)、一緻密化回火及一犧牲氧化(sacrificial oxidation)，熟習本發明所屬技術領域者當可理解。接著可進行方框203之井植入(well implantation)模組，以在位於該些超晶格層125間之半導體層112~115中植入各別之P型或N型摻雜物，並視需要接著進行一回火(例如快速熱回火(RTA))。該方法可更包括方框204~205之閘極形成，及源極106，109與汲極107，110植入，熟習本發明所屬技術領域者當可理解。如圖所示，每一閘極包含覆於該些源極區與汲極區106，107與109，110間之各別通道區108，111上方之一氧化物層121，以及每一氧化物層上面之一閘電極122。
應注意的是，本說明書之實施例雖提供了具體之參數(例如尺寸等等)及材料，但不同之實施方式亦可使用其他合適參數及材料，熟習本發明所屬技術領域者當可理解。舉例而言，NMOS及PMOS元件不需兩者同時使用空乏層堆疊或類埋置氧化物，而可擇其中一者使用之。此外，一堆疊中可包含超過一個之P-N接面。亦即，如有需要，該堆疊中可 包含額外之超晶格層125及摻雜半導體層。
在得益於前述說明及相關圖式之教示下，熟習本發明所屬技術領域者將可想到許多變化及其他實施方式。因此，應理解的是，本發明並不限於所揭露之特定實施方式，且所有變化及其實施方式皆旨在落入後附之申請專利範圍之範疇內。

Claims (18)

  1. 一種製作一半導體元件之方法，其包括：在一底材上面形成超晶格層與主體半導體層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，該超晶格層之每一層群組包括複數個堆疊之基底半導體單層，其界定出一基底半導體部份與受限在相鄰之基底半導體部份之一晶格內之至少一非半導體單層；以交替之摻雜物導電性類型摻雜各別超晶格層之間之主體半導體層以界定一p-n接面；在超晶格層與主體半導體層之該交替堆疊之一上部主體半導體層中形成分隔之源極區與汲極區；以及在該上部主體半導體層上面於該些分隔之源極區與汲極區之間形成一閘極並於源極與汲極區之間且在p-n接面之上界定一空乏通道；其中該半導體元件在其通道與底材之間實質上沒有氧化物層存在。
  2. 如申請專利範圍第1項之方法，其更包括形成至少一淺溝槽隔絕(STI)區使之延伸穿過超晶格層與主體半導體層之該交替堆疊並進入該底材。
  3. 如申請專利範圍第1項之方法，其中每一基底半導體部分包括矽。
  4. 如申請專利範圍第1項之方法，其中每一基底半導體部分包括鍺。
  5. 如申請專利範圍第1項之方法，其中該至少一非半導體單層包括氧。
  6. 如申請專利範圍第1項之方法，其中該至少一非半導體單層包括由氧、氮、氟及碳-氧所組成群組中選定之一非半導體。
  7. 如申請專利範圍第1項之方法，其中形成該閘極包括在該上部主體半導體層上面位於該些分隔之源極區與汲極區之間形成一氧化物層，以及形成覆於氧化物層上方之一閘電極。
  8. 如申請專利範圍第1項之方法，其中來自每一超晶格層之相對基底半導體部分之至少一些半導體原子，係透過相對基底半導體部分間之該非半導體單層以化學方式鍵結在一起。
  9. 一半導體元件，其包括：一底材上面之超晶格層與主體半導體層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，該超晶格層之每一層群組包括複數個堆疊之基底半導體單層，其界定出一基底半導體部份與受限在相鄰之基底半導體部份之一晶格內之至少一非半導體單層，各別超晶格層之間之主體半導體層以交替之摻雜物導電性類型摻雜以界定一p-n接面；超晶格層與主體半導體層之該交替堆疊之一上部主體半導體層中之分隔之源極區與汲極區；以及該上部主體半導體層上面位於該些分隔之源極區與汲極區間之一閘極，其於源極與汲極區之間且在p-n接面之上界定一空乏通道；其中該半導體元件在其通道與底材之間實質上沒有氧化物層存在。
  10. 如申請專利範圍第9項之半導體元件，其更包括延伸穿過超晶格層與主體半導體層之該交替堆疊並進入該底材之至少一淺溝槽隔絕(STI)區。
  11. 如申請專利範圍第9項之半導體元件，其中每一基底半導體部分包括矽。
  12. 如申請專利範圍第9項之半導體元件，其中每一基底半導體部分包括鍺。
  13. 如申請專利範圍第9項之半導體元件，其中該至少一非半導體單層包括氧。
  14. 如申請專利範圍第9項之半導體元件，其中該至少一非半導體單層包括由氧、氮、氟及碳-氧所組成群組中選定之一非半導體。
  15. 如申請專利範圍第9項之半導體元件，其中該閘極包括該上部主體半導體層上面位於該些分隔之源極區與汲極區之間之一氧化物層，以及覆於氧化物層上方之一閘電極。
  16. 如申請專利範圍第9項之半導體元件，其中來自相對之基底半導體部分之至少一些半導體原子，係透過相對基底半導體部分間之該非半導體單層，以化學方式鍵結在一起。
  17. 一半導體元件，其包括： 一底材上面之超晶格層與主體矽層之一交替堆疊，每一超晶格層包含複數個堆疊之層群組，該超晶格層之每一層群組包括複數個堆疊之基底矽單層，其界定出一基底矽部份與受限在相鄰之基底矽部份之一晶格內之至少一氧單層，各別超晶格層之間之主體矽層以交替之摻雜物導電性類型摻雜以界定一p-n接面；超晶格層與主體矽層之該交替堆疊之一上部主體矽層中之分隔之源極區與汲極區；以及該上部主體矽層上面位於該些分隔之源極區與汲極區間之一閘極，其於源極與汲極區之間且在p-n接面之上界定一空乏通道；其中該半導體元件在其通道與底材之間實質上沒有氧化物層存在。
  18. 如申請專利範圍第17項之半導體元件，其更包括延伸穿過超晶格層與主體矽層之該交替堆疊並進入該底材之至少一淺溝槽隔絕(STI)區。
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