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DE69631098D1 - Halbleiterstrukturen - Google Patents

Halbleiterstrukturen

Info

Publication number
DE69631098D1
DE69631098D1 DE69631098T DE69631098T DE69631098D1 DE 69631098 D1 DE69631098 D1 DE 69631098D1 DE 69631098 T DE69631098 T DE 69631098T DE 69631098 T DE69631098 T DE 69631098T DE 69631098 D1 DE69631098 D1 DE 69631098D1
Authority
DE
Germany
Prior art keywords
semiconductor structures
semiconductor
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69631098T
Other languages
English (en)
Inventor
Jeremy Allam
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Europe Ltd
Original Assignee
Hitachi Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Europe Ltd filed Critical Hitachi Europe Ltd
Application granted granted Critical
Publication of DE69631098D1 publication Critical patent/DE69631098D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/40—Transit-time diodes, e.g. IMPATT or TRAPATT diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/80—Heterojunction BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H10D62/8162—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation
    • H10D62/8164—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices having quantum effects only in the vertical direction, i.e. layered structures having quantum effects solely resulting from vertical potential variation comprising only semiconductor materials 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
DE69631098T 1995-08-03 1996-07-30 Halbleiterstrukturen Expired - Lifetime DE69631098D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95305436 1995-08-03

Publications (1)

Publication Number Publication Date
DE69631098D1 true DE69631098D1 (de) 2004-01-29

Family

ID=8221280

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631098T Expired - Lifetime DE69631098D1 (de) 1995-08-03 1996-07-30 Halbleiterstrukturen

Country Status (3)

Country Link
US (2) US6326650B1 (de)
JP (1) JPH09121061A (de)
DE (1) DE69631098D1 (de)

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JP3159198B2 (ja) * 1999-02-19 2001-04-23 住友電気工業株式会社 電界効果トランジスタ
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US6563145B1 (en) * 1999-04-19 2003-05-13 Chang Charles E Methods and apparatus for a composite collector double heterojunction bipolar transistor
FR2795871B1 (fr) * 1999-07-01 2001-09-14 Picogiga Sa Transistor iii-v a heterojonction, notamment transistor a effet de champ hemt ou transistor bipolaire a heterojonction
CA2307745A1 (en) 1999-07-15 2001-01-15 Sumitomo Electric Industries, Ltd. Photodiode
AU2002216611A1 (en) * 2000-09-29 2002-04-08 Board Of Regents, The University Of Texas System A theory of the charge multiplication process in avalanche photodiodes
US6455377B1 (en) * 2001-01-19 2002-09-24 Chartered Semiconductor Manufacturing Ltd. Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)
WO2003009396A2 (en) * 2001-07-20 2003-01-30 Microlink Devices, Inc. Algaas or ingap low turn-on voltage gaas-based heterojunction bipolar transistor
US6934031B2 (en) * 2001-09-27 2005-08-23 Rudolph Technologies, Inc. Methods and apparatus for determining optical constants of semiconductors and dielectrics with interband states
ES2616248T3 (es) * 2002-02-01 2017-06-12 Picometrix, Llc Fotodiodo PIN de alta velocidad con respuesta incrementada
AU2003207814A1 (en) * 2002-02-01 2003-09-02 Picometrix, Inc. Charge controlled avalanche photodiode and method of making the same
WO2003065418A2 (en) * 2002-02-01 2003-08-07 Picometrix, Inc. Planar avalanche photodiode
KR100463416B1 (ko) * 2002-09-05 2004-12-23 한국전자통신연구원 아발란치 포토트랜지스터
US6703639B1 (en) 2002-12-17 2004-03-09 The United States Of America As Represented By The Secretary Of The Navy Nanofabrication for InAs/AlSb heterostructures
US20070020833A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
US20060273299A1 (en) * 2003-06-26 2006-12-07 Rj Mears, Llc Method for making a semiconductor device including a dopant blocking superlattice
US7531850B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7227174B2 (en) * 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045377B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US20060243964A1 (en) * 2003-06-26 2006-11-02 Rj Mears, Llc Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7514328B2 (en) * 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US20060292765A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Method for Making a FINFET Including a Superlattice
US20070020860A1 (en) * 2003-06-26 2007-01-25 Rj Mears, Llc Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods
US7153763B2 (en) 2003-06-26 2006-12-26 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
US7586116B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US20050282330A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
US20060289049A1 (en) * 2003-06-26 2006-12-28 Rj Mears, Llc Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
US20070010040A1 (en) * 2003-06-26 2007-01-11 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress Layer
US7586165B2 (en) * 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US20070063185A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Semiconductor device including a front side strained superlattice layer and a back side stress layer
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7531828B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
US20060231857A1 (en) * 2003-06-26 2006-10-19 Rj Mears, Llc Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) device
US20050279991A1 (en) * 2003-06-26 2005-12-22 Rj Mears, Llc Semiconductor device including a superlattice having at least one group of substantially undoped layers
US7491587B2 (en) * 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US20060267130A1 (en) * 2003-06-26 2006-11-30 Rj Mears, Llc Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween
US20070015344A1 (en) * 2003-06-26 2007-01-18 Rj Mears, Llc Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
US7535041B2 (en) * 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US20070063186A1 (en) * 2003-06-26 2007-03-22 Rj Mears, Llc Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layer
US7612366B2 (en) * 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7598515B2 (en) * 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7202494B2 (en) * 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US20060011905A1 (en) * 2003-06-26 2006-01-19 Rj Mears, Llc Semiconductor device comprising a superlattice dielectric interface layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US20060220118A1 (en) * 2003-06-26 2006-10-05 Rj Mears, Llc Semiconductor device including a dopant blocking superlattice
US20040266116A1 (en) * 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US7446002B2 (en) * 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US6958486B2 (en) * 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7045813B2 (en) * 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7229902B2 (en) * 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7531829B2 (en) * 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
JP2005259755A (ja) * 2004-03-09 2005-09-22 Matsushita Electric Ind Co Ltd ヘテロ接合バイポーラトランジスタおよびその製造方法
US7180103B2 (en) * 2004-09-24 2007-02-20 Agere Systems Inc. III-V power field effect transistors
US20060175631A1 (en) * 2005-02-04 2006-08-10 Raytheon Company Monolithic integrated circuit having enhanced breakdown voltage
US7902046B2 (en) * 2005-09-19 2011-03-08 The Board Of Trustees Of The Leland Stanford Junior University Thin buffer layers for SiGe growth on mismatched substrates
US7517702B2 (en) * 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US20070187667A1 (en) * 2005-12-22 2007-08-16 Rj Mears, Llc Electronic device including a selectively polable superlattice
WO2007098138A2 (en) * 2006-02-21 2007-08-30 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer and associated methods
KR20070117238A (ko) * 2006-06-08 2007-12-12 삼성전기주식회사 반도체 발광 트랜지스터
KR100850950B1 (ko) * 2006-07-26 2008-08-08 엘지전자 주식회사 질화물계 발광 소자
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) * 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7863066B2 (en) * 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) * 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
JP5498662B2 (ja) * 2008-03-26 2014-05-21 国立大学法人 東京大学 半導体装置および半導体装置の製造方法
WO2010023273A1 (de) * 2008-08-28 2010-03-04 Forschungsverbund Berlin E.V. Schottky-drain transistor
TW201115735A (en) * 2009-10-21 2011-05-01 Univ Nat Chiao Tung Ohmic contact of III-V semiconductor device and manufacturing method
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CN105900241B (zh) 2013-11-22 2020-07-24 阿托梅拉公司 包括超晶格耗尽层堆叠的半导体装置和相关方法
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EP3284106B1 (de) 2015-05-15 2021-12-22 Atomera Incorporated Verfahren zur herstellung von halbleiterbauelementen mit superlattice-schichten zur eingrenzung von spitzen einer halo-implantation
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US9748430B2 (en) 2015-06-18 2017-08-29 Board Of Regents, The University Of Texas System Staircase avalanche photodiode with a staircase multiplication region composed of an AIInAsSb alloy
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
FR3053837B1 (fr) * 2016-07-08 2018-08-24 Commissariat A L'energie Atomique Et Aux Energies Alternatives Structure du type photodiode a avalanche et procede de fabrication d'une telle structure
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Also Published As

Publication number Publication date
US6436784B1 (en) 2002-08-20
JPH09121061A (ja) 1997-05-06
US6326650B1 (en) 2001-12-04

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8332 No legal effect for de