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DE69631940D1 - Halbleitervorrichtung - Google Patents

Halbleitervorrichtung

Info

Publication number
DE69631940D1
DE69631940D1 DE69631940T DE69631940T DE69631940D1 DE 69631940 D1 DE69631940 D1 DE 69631940D1 DE 69631940 T DE69631940 T DE 69631940T DE 69631940 T DE69631940 T DE 69631940T DE 69631940 D1 DE69631940 D1 DE 69631940D1
Authority
DE
Germany
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69631940T
Other languages
English (en)
Other versions
DE69631940T2 (de
Inventor
Katsuhiro Kato
Yasuhiro Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of DE69631940D1 publication Critical patent/DE69631940D1/de
Application granted granted Critical
Publication of DE69631940T2 publication Critical patent/DE69631940T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08142—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electronic Switches (AREA)
DE69631940T 1995-11-21 1996-11-21 Halbleitervorrichtung Expired - Lifetime DE69631940T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP30270695A JP3400215B2 (ja) 1995-11-21 1995-11-21 半導体装置
JP30270695 1995-11-21

Publications (2)

Publication Number Publication Date
DE69631940D1 true DE69631940D1 (de) 2004-04-29
DE69631940T2 DE69631940T2 (de) 2005-03-10

Family

ID=17912215

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631940T Expired - Lifetime DE69631940T2 (de) 1995-11-21 1996-11-21 Halbleitervorrichtung

Country Status (6)

Country Link
US (1) US5850094A (de)
EP (1) EP0776092B1 (de)
JP (1) JP3400215B2 (de)
KR (1) KR100417093B1 (de)
DE (1) DE69631940T2 (de)
TW (1) TW312848B (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000002089A (ko) * 1998-06-17 2000-01-15 김영환 정전기 방전 보호 회로
IT1302208B1 (it) * 1998-09-14 2000-09-05 St Microelectronics Srl Dispositivo circuitale di protezione contro scariche elettrostatichee immune dal fenomeno di latch-up.
US6600356B1 (en) * 1999-04-30 2003-07-29 Analog Devices, Inc. ESD protection circuit with controlled breakdown voltage
TW445627B (en) * 1999-10-04 2001-07-11 Winbond Electronics Corp Electrostatic discharge buffer apparatus
KR100333337B1 (ko) * 1999-10-11 2002-04-18 윤종용 이동통신 시스템에서 디지털 필터 장치 및 필터링 방법
DE10205711A1 (de) * 2002-02-12 2003-08-21 Infineon Technologies Ag Verfahren und Vorrichtung zum Erfassen eines Durchbruchs eines Bipolartransistors
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
KR100713935B1 (ko) * 2006-04-14 2007-05-07 주식회사 하이닉스반도체 반도체 메모리 장치의 정전기 방전 보호 회로 및 정전기방전 보호 방법
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
EP2321748B1 (de) 2008-07-16 2017-10-04 Tela Innovations, Inc. Zellsynchronisierungs- und positionierungsverfahren in einer dynamischen feldarchitektur und umsetzung des verfahrens
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
JP5576674B2 (ja) * 2010-02-23 2014-08-20 ルネサスエレクトロニクス株式会社 半導体装置
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
JP2013172085A (ja) * 2012-02-22 2013-09-02 Asahi Kasei Electronics Co Ltd 半導体装置の製造方法及び半導体装置
TWI870135B (zh) * 2023-12-01 2025-01-11 立積電子股份有限公司 半導體裝置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6268319A (ja) * 1985-09-20 1987-03-28 Matsushita Electric Ind Co Ltd 誘導性負荷駆動回路
JPS62165969A (ja) * 1986-01-17 1987-07-22 Sanyo Electric Co Ltd Ｃｍｏｓ半導体装置
US4819047A (en) * 1987-05-15 1989-04-04 Advanced Micro Devices, Inc. Protection system for CMOS integrated circuits
US4855620A (en) * 1987-11-18 1989-08-08 Texas Instruments Incorporated Output buffer with improved ESD protection
US4990802A (en) * 1988-11-22 1991-02-05 At&T Bell Laboratories ESD protection for output buffers
US5075691A (en) * 1989-07-24 1991-12-24 Motorola, Inc. Multi-resonant laminar antenna
US5021853A (en) * 1990-04-27 1991-06-04 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
KR920009015A (ko) * 1990-10-29 1992-05-28 김광호 반도체 칩의 보호회로
US5272586A (en) * 1991-01-29 1993-12-21 National Semiconductor Corporation Technique for improving ESD immunity
JP2878587B2 (ja) * 1993-10-20 1999-04-05 株式会社日立製作所 半導体装置

Also Published As

Publication number Publication date
EP0776092A2 (de) 1997-05-28
TW312848B (de) 1997-08-11
US5850094A (en) 1998-12-15
KR970031339A (ko) 1997-06-26
JPH09148903A (ja) 1997-06-06
KR100417093B1 (ko) 2004-05-06
DE69631940T2 (de) 2005-03-10
EP0776092A3 (de) 1999-11-10
JP3400215B2 (ja) 2003-04-28
EP0776092B1 (de) 2004-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP