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TWI251911B - Test vehicle ball grid array package - Google Patents

Test vehicle ball grid array package Download PDF

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Publication number
TWI251911B
TWI251911B TW092118813A TW92118813A TWI251911B TW I251911 B TWI251911 B TW I251911B TW 092118813 A TW092118813 A TW 092118813A TW 92118813 A TW92118813 A TW 92118813A TW I251911 B TWI251911 B TW I251911B
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Taiwan
Prior art keywords
pcb
adhered
package
sealing
test
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Application number
TW092118813A
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English (en)
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TW200418154A (en
Inventor
Chae-Kyu Jang
Sang-Kwon Lee
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Hynix Semiconductor Inc
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Publication of TW200418154A publication Critical patent/TW200418154A/zh
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Publication of TWI251911B publication Critical patent/TWI251911B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

1251911 五、發明說明（1) 【本=:所屬之技術領域』 m n fn m F# '，] ^ J ^ ^ f 【先前技術】且日日0可移動測試用球栅型陣列封裝。、 眾所皆知，丰宴壯 t胃 量產型封裝是斜封裝可分成量產型封裝和測試封获。 娜曰片 ^產口口製造。測試封裝則製造用炎、、目丨」、1 脰日日。可移動測試用封裝常用陶瓷$# “彳試半導 封裝。 用陶是或邊接型封裝作為測試 。1下’參考第1圖來說明傳統的陶究可移動測試用封裝 晶片it =二日日片1 〇位於基板溝槽中2。並以上蓋5覆芸半I， 曰片10所在的溝槽2。半導體晶片10 : - +導體 的接腳3之間藉由金屬導線4彼此㈣。由二圖：)：基板i 接腳部分被成形彎向基板1的下方。 土 。外的 ，種可移動測試用陶变封裝適合用來測試低密戶一 +。半導體晶片1的測試是在基板丨的接觸又间速兀 電極接觸的狀態下進行。 觸接腳3與測試p c B的 傳、统可移動測試用陶£封裝適合用來測試 件，但卻不適合用來測試高密度高速元件。理由又呵速凡 可移動測試用陶謂、，由於金屬接腳 ：：二傳統 測試用陶瓷封裝的寄生電容太大。因$ #、、先可移動 疋圪緣體，因此傳統可移動測試用陶瓷封六^材枓 此’在測試高密度高速元件時，會產誤：：：。因 地測試。 9 W紅作而热法正確
1251911 五、發明說明
是曾經發展可 几件例如隨機 凸塊型陣列封 雖然未圖 型陣列封裝來 (Rambus)元件 寸和和腳塾值 示也未提及，但 測試高密度高速 。可移動測試用 置。 移動測試用凸塊 存取記憶體排 裝受限於晶片尺 甲 竟封裝具有高寄生電感 封裝不適合用來測試高 兩六 由於傳統可移動測試用陶 兒:’因此傳統可移動測試用陶究 度高速元件 而且’由於 裝的二至三倍， 造0 傳統可移動測試用陶竟封 因此傳統可移動測試用陶 裝的尺寸是一般封 瓷封裝並不容易製 而且傳統可移動測試用陶瓷封裝需要一個測試PCb。 因此’會造成製造的問題並增加生產成本。 為了解決上述問題，傳統上測試是利用一般封裝以去除 封裝的製程進打而不另外製造測試封裝。在去除封裝的製程 中，將S產封策去除露出半導體晶片，並施加電訊號給曝露 半導體晶片的每個腳墊來測試半導體晶片。由於去除封裝製 程比傳統複雜，因此並不適合製程。由於去除封裝會降低分 析區域的可靠性並造成不正確的取樣，因此傳統去除封裝製 程有其困難性。 、 【本發明之内容】 本發明的目的、特徵和優點藉由圖示和後面的敘述將更 明白清楚。 因此為了解決上述習知技術所發生的問題，本發明的目 的是提供一種適合用來測試高密度高速元件的可移動測試用
$ 8頁 1251911 五、發明說明（3) 球柵型陣列封裝。 為了達到上述目的，本發明的可移動測試用球柵型陣列 封裝具有·一個具有接腳的PCB ;塗佈在pCB邊緣的黏著材 料；一個黏著在黏著劑材料上的封牆；一個黏在pCB上具有 多個腳墊的半導體測試晶片；多個金屬導線分別連接㈣的 腳墊和PCB的接月卻；一個封蓋黏在封牆以密封導體晶片；和 多個黏在PCB下面的錫球。 【本發明之實施方式】
接下來將參考圖示說明本發明最佳實施例。纟以下的說 明和圖示中，相同的零件以相同的標示數字表示並省略 零件的重複說明部分。 第2圖疋根據本發明實施例的可移動測試用球柵型 封裝橫截面圖。 j 可移動測試用球栅陣列（以下稱為"TVT —BGA，，封裝）包括 一個PCB 20 ’黏著材料27，封牆24，半導體測試晶片 個金屬導線2 8，和多個錫球3 2。 PCB 20具有接腳22。黏著劑材料27塗佈在ρ(：Β 2〇的邊 。封牆24黏著在黏著劑材料27上。半導體測試晶片27具有多 個黏在PCB 20上的腳墊（未圖示）σρ(：Β 2〇的腳墊和？(^ 的接腳分別由多條金屬導線28連接。封蓋25黏在封牆以 封半導體測試晶片30。黏著在PCB 2〇下面的多個錫球32盥電 路連接（未圖示）。錫球32用來固定pCB和外部元件。、 、，接腳22藉由金線28或類似材料與半導體晶片3〇的腳墊連 接亚作為PCB 20的電極。接腳22只要能夠打線可以是任何形
1251911
五、發明說明（4) 狀如，方形、三角形、圓形等。 每個封牆24和封蓋25是由非導電材料或類似材料 成。封牆24藉由類似膠帶的材料黏在pCB 2〇上。 ί起24a讓封蓋25可以輕易地藉由凸起24a黏著在封；:、有 利用膠帶26、低溫熱塑性膠帶或類似低溫 *的 材料黏在封牆24的凸起24a。 土〖生知▼的 錫球32藉由流銲和固定球的製程附著在PCB 20的下表面 ί ?膠帶在PCB 2°各個部分並使用封牆24和封 成25在封+年.肢日日片3〇製造本發明的TV_BGA封裴。 以輕易達^可移動測試用的高密度高速幻牛。在進行多= 測試用局=和高速元件的測試時，產生的寄生電感和電容 I小。由於根據本發明的TV-BGA封裝沒有金屬接腳 此寄生％感彳艮小而且在接腳間沒有寄 可移動測試用的高密度高速元件。今生“所以可以得到 而且在分析半導體晶片時，tv_bga封裝不需 的程序。因此可以改善分析的正確性。 ’、、裝 根據本發明的T V - B G A封裝可以靡H *、息立 是中心腳墊型w。 τ以應用在邊緣腳墊型晶片或 第2圖是根據本發明實施例應用在邊緣腳μ “ TV-BGA封装的橫截面圖。第3圖是根摅太 … 3圖，TV-BGA封I晶片腳墊位置p、2面圖丄如弟2圖和第 中心腳勢型半導體晶片。由於根V本，^ r 很據本發明的TV-BGA封裝沒有
第10胃 1251911
限制晶片腳墊的位置，TV-BGA封裝可以進行傳統很難 面下型BGA型封裝的分析。 、 二。根據本發明的TV_BGA封裝可以與球栅型陣列測試板的預 二區域共用。因此，TV —BGA封裝不需要額外的pCB， 、 本較低。 、A成 裝是以傳統設備和製程 ’所以具有技術和成本上 此外，根據本發明的TV-BGA封 ^因此不需要發展新設備和新製程 的優勢。 根據 圖說明如 流程圖。 截面圖。 狀而非片 類似 第5 A圖）· 腳2 2所環 個金屬導 為了密封 電材料所 封蓋2 5是 或類似低 熱塑性膠 (第4圖和 本發明實施例的TV-BGA封裝製程參考第4圖到第5d 下。第4圖是根據本發明實施例的TV_BGA封裝製 第5A圖到第5D圖分別是每個製程步驟的上視圖和橫 20具有電路圖形21和一個接腳22。pCB 為長條 狀。塗佈在PCB 20上的膠帶23環繞每個接腳'、22。^、 膠帶23的材料取代膠帶23塗佈在pcb 20上（第4圖和 °半導體晶片3 0黏在黏晶製程時由黏著材料2 7和接 繞的封閉區域。利用打線，PCB2〇的腳墊分別以多 線28與PCB20的接腳電性連接（第4圖和第⑽圖） 半導體晶片30，封牆24黏在膠帶23上。封牆是非導 ，成。封蓋25使用膠帶26黏在封牆24的凸回起2^。 是由非導電材料所構成。膠帶2 6為低溫熱塑性膠帶 :熱塑性膠帶的材料，低溫熱塑性膠帶或類似低溫 :的材料輕易地將封蓋25與封牆24黏著— 第5C圖）。 ~ %
1251911 五、發明說明（6) 將錫球3 2附著到P C B 2 0的下表面之後，利用流鮮製程讓 錫球32 I、黏在PCB 20的下表面。之後多個TV-BGA封裝以長 條狀的方式製造。藉著進行TV_BGA封裝的某一特殊製程之 後’再將TV-BGA封裝分開成片狀，完成TV —BGA封裝（第4圖和 第5D圖）。 根據本發明的TV-BGA封裝製造方法，如上述，除了塗佈 膠帶環繞每個PCB20接腳22的步驟和固定封牆24和封蓋25的 步驟之外。與傳統可移動測試用製造方法相比，本發明的 TV-BGA封裝製造方法不需要額外的製程和相關設備除了上述 的兩個步驟。 為可移動測試用封裝和實 兩者具有相同的電性所以 在本發明的T V - B G A封襄中，因 際封裝具有相同的原材料和結構， 可以增加缺陷封裝分析的可靠性。 備 此 可 而且由方；本發明的TV-BGA封裝採用傳統技術和擎造設 ’ ^不需要額外的投資和研發所以具有成本優勢 項技U ΐ =佳實施例僅作為解釋目的，對於任何熟悉 能不偏離太直y & Ί 修變更、取代或附加都有 月匕不侷磷本專利申請範圍。
第12頁 1251911 _ 圖式簡單說明 第1圖是傳統可移動測試用陶瓷陣列封裝的橫截面圖； 第2圖是根據本發明實施例可移動測試用球栅型陣列封 裝的橫截面圖； 第3圖是本發明另一可移動測試用球栅型陣列封裝實施 例的橫截面圖； 第4圖是根據本發明可移動測試用球柵型陣列封裝實施 例的製程流程圖；和 第5A圖到第5D圖分別是每個製程步驟的上視圖和橫截面 圖。 【圖中元件編號與名稱對照表】 1 ： 基板 10 半導體晶片 2 ： 基板溝槽中 20 PCB 21 : :電路圖形 22 接腳 23 ： :膠帶 24 封牆 24a :凸起 25 封蓋 26 膠帶 27 黏著材料 28 金屬導線 3 ： 接腳 30 半導體測試晶片 32 : I锡球 3 0a :中心腳墊型半導體晶片 4 ： 金屬導線 5 二 上蓋
第13頁

Claims (1)

  1. 案號92】1SS13 1251911
    六、申請專利範圍 1· 一種可移動測試用球柵型陣列封裝， 一個具有接腳的PCB ; 、有： 塗佈在PCB邊緣的黏著材料； 黏在黏著劑材料上的封牆，封牆上端 黏在PCB上具有多個腳墊的半導體測試/曰凸起； 分別連接PCB腳墊與PCB接腳的多個金3曰片；. 黏在封牆上的封蓋以密封半導體晶片；、線； 黏在PCB下邊的多個錫球。 、及 m 2 ·如申請專利範圍第1項的可移動測 封裝，其中每個封牆和封蓋是由非導電材料戶球柵型陣列 3.如申請專利範圍第1項的可移動試斤/冓成。 封裝，其中封蓋是黏在封牆的凸起用球麵型陣列 4·如申請專利範圍第3項的可移動測試用球柵型陣 封裝，其中封蓋是以低溫熱塑性膠帶或類似低溫熱塑性膠 ▼的材料黏在封牆的凸起。 5 ·如申請專利範圍第丨項的可移動測試用球栅型陣列 封裝’其中半導體晶片是中心腳塾型晶片。
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