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TW533482B - Method of manufacturing a semiconductor device - Google Patents

Method of manufacturing a semiconductor device Download PDF

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Publication number
TW533482B
TW533482B TW090109425A TW90109425A TW533482B TW 533482 B TW533482 B TW 533482B TW 090109425 A TW090109425 A TW 090109425A TW 90109425 A TW90109425 A TW 90109425A TW 533482 B TW533482 B TW 533482B
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TW090109425A
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Peter A Stolk
Pierre H Woerlee
Mathijs J Knitel
Brandenburg Anja C M C Van
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Koninkl Philips Electronics Nv
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

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  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Description

533482 修正 案號 90109425 五、發明說明（1) 技術領域 本發明係關於半導體裝置之製造，特別是關於提供工具俾 減少積體電路（I C s )内金屬氧化物半導體場效電晶體 (MOSFETs)最小特徵之大小。尤其是，本發明係關於一項 科技使源極/汲極（S/D)接合與M0S電晶體内袖珍反滲吸收 劑區之單獨形成致能而不需額外施加隱蔽罩之步驟。 先前技術 半導體工業不斷努力以減少積體電路内M0SFET最小特徵大 小。驅使此等企圖主要是由於需要產生較低成本之I C s， 同時保持或改良電路功能性與速率。例如藉減少在此等 I C s上現用電晶體之特性大小，特別是閘極長度，閘極氧 化厚度和接合深度，且藉增加通道摻吸收劑準位即可達成 此項向下調整。 短Μ 0 S電晶體一般遭受到所謂短通道效應（S C Ε ):當減少閘 極長度時源極與汲極會相互接近。此在某種意義上對電晶 體之切換多少有點相反效果，即由閘極較少可控制切換， 此可導致不需要之減少截限電壓。此相反效應可由一使在 源極和汲極周圍之空虛區佔用縫道區之漸增大分數，如此 即需要閘極上有較低電位以達成縫道内之逆增。 按習用M0SFET調整想定，藉減少接合深度與增加縫道滲雜 劑濃度即可保持S C Ε在可接受限度以内。但此等想定不再 可以工作在次級-0.18微米裝置，因為在此等裝置内SCE之 抑制在通道内需要太高之摻吸收劑準位，此可引起接合上 之破壞。 建議此問題之解決辦法係使用腔洞或光環反滲吸收劑植入
70739-920312.ptc 第5頁 533482 案號 90109425 年/月6 曰 修正 五、發明說明（2) 物。在PMOS電晶體内之腔洞可使用燐光質，砷或銻離子， 在N Μ 0 S電晶體内之腔洞可使用硼或銦離子。腔洞移植物可 有助於提高在直接靠近S/D區之通道滲吸收劑準位。當減 少閘極長度時此可導致淨增加通道滲吸收劑區，因而抑制 短通道裝置之S/D空虛區之影響。 , 按標準Μ 0 S處理，特別是按習用互補Μ 0 S處理，腔洞移植步 驟，亦稱為光環移植步驟，係與S / D (延伸）移植步驟聯 合。在此聯合移植步驟中，矽晶圓某些面積係涵蓋一定型 之抵抗層以便避免此等面積内不需要之移植。例如，在 NM0S電晶體形成中即涵盖PMOS電晶體’反之亦然。在拆除 該抵抗層以後在一單獨韌煉步驟内可致動此等腔洞移植物 和S / D移植物。在此韌煉步驟中摻雜劑擴散可決定腔洞摻 雜劑和S / D摻雜劑兩者之分配。 在U S - A - 5，2 2 7，3 2 1專利内可提供一製程之範例其中由韌煉 作用可調整一主要摻雜劑第一擴散區與一光環擴散區之大 小 。 本方法之一缺點，其中可使用一種韌煉步驟以擴散摻雜 劑，係不能單獨地調整腔洞和S / D區之摻吸收劑側面以便 改進裝置性能。 因之應產生可能性以分開而單獨地移植和韌煉腔洞區和 S / D區。此可提供可能性以便摻雜劑分配且因而使短通道 性能達最佳情況。 但問題存在於此事實：在移植中可涵蓋部分晶圓之抵抗層 係不能受2 5 0 °C以上之溫度。此即表示完全分開之腔洞和 S/D形成即需要使用額外抵抗加蔽罩步驟。對於CMOS製
70739-920312.ptc 第6頁 533482 案號 90109425 年之月 曰 修正 五、發明說明（3) 程，此可表示需要兩種額外平板印刷步驟。本發明之方法 不需額外加蔽罩或平板印刷步驟，因此種步驟可延長及使 製程複·雜且因而顯著提高製造成本。 發明内容 本發明意欲克服為習用Μ 0 S電晶體技術所域之問題。 藉使用硬蔽罩使腔洞和S / D區單獨形成致能即可達成此目 的〇 更詳言之，本發明係關於製造包括一 PMOS電晶體和一 NMOS 電晶體之半導體裝置之方法包括以下步驟：
(a) 提供一半導體基材具有係被供有NMOS電晶體之Ρ-井 區，和係被供有PM 0 S電晶體之N -井區； (b) 在P -井區和N -井區上形成閘極； (c) 施加一硬蔽罩，可涵蓋P -井區或者N -井區； (d )在未被硬蔽罩所涵蓋之該區内移植一源極及一汲 極，隨後即為熱作用； (e )在未被硬蔽罩所涵蓋之該區内移植腔洞移植物，隨 後即為熱作用； (ί )拆除硬蔽罩。
較佳地，藉加一硬蔽罩即可實行步驟（c )，以一防止層涵 蓋該硬蔽罩，使此防止層定型，且使用該定型之防止層為 使硬蔽罩層定型之一蔽罩以形成硬蔽罩。 硬蔽罩應有足夠厚度以避免移植之摻雜劑滲透，且因此有 利地有一至少0 . 0 5微米之厚度。該硬蔽罩厚度之上限緊要 性不大。有時厚度係由經濟考量決定之，由於硬蔽罩並非 很厚。一般言，硬蔽罩所需之厚度視用以形成硬蔽罩之該
70739-920312.ptc 第7頁 533482 修正 案號 90109425 五、發明說明（4) 層之化學成分而定。使用並不太厚之硬蔽罩，例如SiGe -硬蔽罩有厚度在0.25微米以下，較佳在0.20微米以下，有 額外優·點是可減少在傾斜腔洞移植物中會發生之離子遮蔽 之效果。藉使用如有厚度約0 . 1 5微米之S i G e硬蔽罩即可獲 得甚良好結果。 / 雖然硬蔽罩可使用幾種材料，特別是幾種氧化物，氮化物 及氧氮化物，但硬蔽罩有益地包括G e _摻雜劑碎，特別是 G e _摻雜劑多結晶矽（多-S i h G ex在溫度約4 5 0 °C時對X > 0 . 3 可沉澱其材料，且可承受迅速熱韌煉情況）。藉化學蒸氣 沉澱可施加此等材料且由原形質侵蝕可使其定型。藉習用 溫侵蝕自氧化物及矽很選擇性地消除此等材料。 實施方式 參考圖1至5更詳細說明本發明，圖内可闡述本發明之適用 方法。 按圖1顯示一矽基材1 ，提供有一 N -井區2和P-井區3，由一 場隔離區4予以分開。P -井區3係被供有N Μ 0 S電晶體5，而 Ν-井區2係被供有PMOS電晶體6 -井區3和Ν-井區2兩者均 備有一閘極氧化物7在其上即形成多矽閘極8。在多矽閘極 8形成以後，即可有利地實行相等於少數毫微米氧化成長 之一短氧化步驟以一氧化層9來涵蓋矽基材與多晶矽閘極
然後，在4 5 0 °C時藉由化學蒸汽沈澱即可施加G e -摻雜劑多 結晶（多S i 〇 65 G eG 35)之硬面罩層1 0 (圖2 )。施加此層厚度約 0 · 1 5微米。施加一習用光阻層1 1 (厚度約0 · 5微米）在硬面 罩層1 0頂部且使用習用平板印刷術予以定型。使用定型之
70739-920312.ptc 第8頁 533482 _案號 90109425 夕么年么月么 曰 修正 五、發明說明（5) 光阻層1 1為一隱蔽罩藉原形質侵蝕俾使硬面罩層1 〇定型， 圖3顯示其最後結果。 圖4顯示一步驟，其中砷離子被移植入p —井區3内在能量範 圍自5至15 KeV和用量範圍在1E15與5E15 cnr2之間，較佳 在3E1 4與1E1 5 cm—2之間，此移植步驟之後為習用韌煉，因 而形成一源極與一汲極1 2。圖5顯示腔洞移植法在傾斜角 20-40° 處使用硼離子（15一30 KeV ;1E13一 1E14 cur2)，其 後為款煉步驟。圖4及5所示步驟可任選地反向，如此首先 實行一腔洞移植/韌煉後跟一源極/汲極移植/韌煉。
隨後’自晶圓（未圖示）可選擇性拆除硬面罩層1 〇，若需 要’與圖2至5所示之相同步驟係可對N -井區2實行，使用B 或BF2離子供源極/汲極移植與使用a s或p離子供腔洞移 植。 在上述步驟之後為本發明之一部分，選擇性移植結構係遭 受習用進一步處理以完成包括PMOS電晶體和NMOS電晶體之 半^體裝置。尤其是，在閘極如側上形成側壁隔板，一般 為氧化物或氮化物。隨後，一般用砷可選擇性摻雜劑在 N Μ 0 S面積上’同時使用習用隱蔽技術，且一般用硼可選擇 性地摻雜劑在PM〇s面積上。按任一次序可實行NMOS及PMOS 推雜劑步驟。後然後，可實行一韌煉步驟以致動摻雜劑 區。最後’可實行習用矽化和金屬化步驟，其最後可提供 所需之半導體裝置。 圖1 - 5係顯示使用依據本發明之方法製造一半導體裝置之 連續階段之示意剖面圖。
70739-920312.pt 第9頁 533482 _•案號 90109425 么月έ?日_修正 五、發明說明（6) 1
70739-920312.ptc 第10頁 533482
70739-920312.ptc 第11頁

Claims (1)

  1. 533482 _案號 90109425 ^么年2月日_魅_ 六、申請專利範圍 / 1. 一種製造包括PMOS電晶體和NMOS電晶體之半導體裝置 之方法，包括以下步驟： (a) 提供一半導體基材具有係備有NMOS電晶體之Ρ-穴 區，與應備有PMOS電晶體之N-井區； (b) 在P -井區上和N -井區上形成閘極； · (c) 施加可涵蓋P -井區或者N -井區之一硬隱蔽罩； (d )移植一源極及汲極在未受硬隱蔽罩所涵蓋之該區 内，後跟熱作用； (e )移植腔洞移植物在未受硬隱蔽罩所涵蓋之該區内， 後跟熱作用； (ί )拆除隱蔽罩。 0 2 .如申請專利範圍第1項之方法，其中在加上硬隱蔽罩 之前，施加一介質層以涵蓋半導體基材與閘極。 3 .如申請專利範圍第1或2項之方法，其中步驟（c )係藉 施加一硬面罩層，用一抗層涵蓋該硬面罩層，使此抗層定 型，且使用定型之抗層為一使硬面罩層定型之隱蔽以形成 硬面罩層。 4 .如申請專利範圍第1或2項之方法，其中施加硬面罩 層，其厚度至少0.05微米。 5 .如申請專利範圍第4項之方法，其中施加硬面罩層， 其厚度在0.25微米以下。 6 .如申請專利範圍第1或2項之方法，其中施加之硬面罩 _ 層包括G e -掺雜劑石夕，S i - r i c h S i Ν或多結晶G e。
    70739-920312.ptc 第12頁
TW090109425A 2000-04-12 2001-04-19 Method of manufacturing a semiconductor device TW533482B (en)

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US (1) US6461908B2 (zh)
EP (1) EP1275147B1 (zh)
JP (1) JP4846167B2 (zh)
KR (1) KR100796825B1 (zh)
AT (1) ATE434831T1 (zh)
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784062B2 (en) * 2002-06-03 2004-08-31 Micron Technology, Inc. Transistor formation for semiconductor devices
JP3730947B2 (ja) * 2002-10-08 2006-01-05 松下電器産業株式会社 半導体装置の製造方法
JP5106099B2 (ja) * 2004-03-30 2012-12-26 カール・ツァイス・エスエムティー・ゲーエムベーハー 投影対物レンズ、マイクロリソグラフィのための投影露光装置及び反射レチクル
US8212988B2 (en) 2004-08-06 2012-07-03 Carl Zeiss GmbH Projection objective for microlithography
US7511890B2 (en) * 2005-02-04 2009-03-31 Carl Zeiss Smt Ag Refractive optical imaging system, in particular projection objective for microlithography
US7704865B2 (en) * 2005-08-23 2010-04-27 Macronix International Co., Ltd. Methods of forming charge-trapping dielectric layers for semiconductor memory devices
US9679602B2 (en) 2006-06-14 2017-06-13 Seagate Technology Llc Disc drive circuitry swap
KR100779395B1 (ko) * 2006-08-31 2007-11-23 동부일렉트로닉스 주식회사 반도체소자 및 그 제조방법
US9305590B2 (en) 2007-10-16 2016-04-05 Seagate Technology Llc Prevent data storage device circuitry swap
US20100330756A1 (en) * 2009-06-25 2010-12-30 International Business Machines Corporation Integrated circuit structure manufacturing methods using hard mask and photoresist combination
US8877596B2 (en) 2010-06-24 2014-11-04 International Business Machines Corporation Semiconductor devices with asymmetric halo implantation and method of manufacture
DE102010063782B4 (de) * 2010-12-21 2016-12-15 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Transistoren mit Metallgatestapeln mit großem ε und einem eingebetteten Verspannungsmaterial

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513953A (en) * 1978-07-18 1980-01-31 Fujitsu Ltd Complementary integrated circuit
JPS5651872A (en) * 1979-10-05 1981-05-09 Oki Electric Ind Co Ltd Manufacture of complementary type mos transistor
JPH01145849A (ja) * 1987-12-01 1989-06-07 Fujitsu Ltd 半導体装置の製造方法
JPH029164A (ja) * 1988-06-28 1990-01-12 Matsushita Electric Ind Co Ltd パターン形成方法および半導体装置の製造方法
JPH02162739A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置の製造方法
US5227321A (en) * 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
JP2917696B2 (ja) * 1992-08-22 1999-07-12 日本電気株式会社 Ｃｍｏｓ半導体装置の製造方法
JP3062398B2 (ja) * 1993-06-25 2000-07-10 松下電器産業株式会社 Ｃｍｏｓ半導体装置の製造方法
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
US5489546A (en) * 1995-05-24 1996-02-06 Micron Technology, Inc. Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process
US6004854A (en) * 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5736440A (en) * 1995-11-27 1998-04-07 Micron Technology, Inc. Semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate
JPH09205151A (ja) * 1996-01-26 1997-08-05 Sony Corp 相補型半導体装置の製造方法
JP2980057B2 (ja) * 1997-04-30 1999-11-22 日本電気株式会社 半導体装置の製造方法
US5904520A (en) * 1998-01-05 1999-05-18 Utek Semiconductor Corp. Method of fabricating a CMOS transistor
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6187619B1 (en) * 1998-02-17 2001-02-13 Shye-Lin Wu Method to fabricate short-channel MOSFETs with an improvement in ESD resistance

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EP1275147A1 (en) 2003-01-15
JP2003531494A (ja) 2003-10-21
KR100796825B1 (ko) 2008-01-22
EP1275147B1 (en) 2009-06-24
US6461908B2 (en) 2002-10-08
WO2001080310A1 (en) 2001-10-25
ATE434831T1 (de) 2009-07-15
DE60139068D1 (de) 2009-08-06
US20010031522A1 (en) 2001-10-18
JP4846167B2 (ja) 2011-12-28

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