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JPS5651872A - Manufacture of complementary type mos transistor - Google Patents

Manufacture of complementary type mos transistor

Info

Publication number
JPS5651872A
JPS5651872A JP12803279A JP12803279A JPS5651872A JP S5651872 A JPS5651872 A JP S5651872A JP 12803279 A JP12803279 A JP 12803279A JP 12803279 A JP12803279 A JP 12803279A JP S5651872 A JPS5651872 A JP S5651872A
Authority
JP
Japan
Prior art keywords
substrate
region
type
film
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12803279A
Other languages
Japanese (ja)
Other versions
JPS6152576B2 (en
Inventor
Yasushi Ueno
Takao Hashimoto
Hironori Kitabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP12803279A priority Critical patent/JPS5651872A/en
Publication of JPS5651872A publication Critical patent/JPS5651872A/en
Publication of JPS6152576B2 publication Critical patent/JPS6152576B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Weting (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a high-concentration diffusion region without causing any influence on the others by providing a PSG film prescribing for mole ratio on the surface of a substrate when forming the source and the drain regions of a transistor by diffusion wherein a selective etching is applied to the PSG film by using a hydrofluoric aqueous solution prescribing for composition. CONSTITUTION:A P<-> type region is formed by diffusion on the predetermined region of an N type substrate 7. Thick field oxide films 8 are formed by locating around the circumference of the substrate 7 and on borders between the P<-> type region and the substrate. A gate oxide films 11 with predetermined shape are provided on the surface of the substrate 7 surrounded by the films 8 and poly- crystalline layers 10 are formed on the films 11. Next, a low temperature PSG film 9 having 0.1-0.3 (PH3/SiH4) by mole ratio is formed on the whole surface and the removal of etching is applied to an NMOS transistor formation section by a hydrofluoric aqueous solution of 0.1-0.5%. Then, the remaining film 9 is used as a mask and an N<+> type source region and drain region 13 are formed in the P<-> type region by ion implantation. P<+> type region 14 is formed in the substrate 7 by renewing the film 9.
JP12803279A 1979-10-05 1979-10-05 Manufacture of complementary type mos transistor Granted JPS5651872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12803279A JPS5651872A (en) 1979-10-05 1979-10-05 Manufacture of complementary type mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12803279A JPS5651872A (en) 1979-10-05 1979-10-05 Manufacture of complementary type mos transistor

Publications (2)

Publication Number Publication Date
JPS5651872A true JPS5651872A (en) 1981-05-09
JPS6152576B2 JPS6152576B2 (en) 1986-11-13

Family

ID=14974816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12803279A Granted JPS5651872A (en) 1979-10-05 1979-10-05 Manufacture of complementary type mos transistor

Country Status (1)

Country Link
JP (1) JPS5651872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003531494A (en) * 2000-04-12 2003-10-21 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003531494A (en) * 2000-04-12 2003-10-21 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method for manufacturing semiconductor device
JP4846167B2 (en) * 2000-04-12 2011-12-28 エヌエックスピー ビー ヴィ Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPS6152576B2 (en) 1986-11-13

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