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DE60139068D1 - Herstellungsverfahren für halbleiterbauelement - Google Patents

Herstellungsverfahren für halbleiterbauelement

Info

Publication number
DE60139068D1
DE60139068D1 DE60139068T DE60139068T DE60139068D1 DE 60139068 D1 DE60139068 D1 DE 60139068D1 DE 60139068 T DE60139068 T DE 60139068T DE 60139068 T DE60139068 T DE 60139068T DE 60139068 D1 DE60139068 D1 DE 60139068D1
Authority
DE
Germany
Prior art keywords
well region
hard mask
manufacturing
region
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60139068T
Other languages
English (en)
Inventor
Peter A Stolk
Pierre H Woerlee
Mathijs J Knitel
Brandenburg Anja C Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60139068D1 publication Critical patent/DE60139068D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Toxicology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE60139068T 2000-04-12 2001-04-03 Herstellungsverfahren für halbleiterbauelement Expired - Lifetime DE60139068D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00201317 2000-04-12
PCT/EP2001/003749 WO2001080310A1 (en) 2000-04-12 2001-04-03 Method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
DE60139068D1 true DE60139068D1 (de) 2009-08-06

Family

ID=8171339

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60139068T Expired - Lifetime DE60139068D1 (de) 2000-04-12 2001-04-03 Herstellungsverfahren für halbleiterbauelement

Country Status (8)

Country Link
US (1) US6461908B2 (de)
EP (1) EP1275147B1 (de)
JP (1) JP4846167B2 (de)
KR (1) KR100796825B1 (de)
AT (1) ATE434831T1 (de)
DE (1) DE60139068D1 (de)
TW (1) TW533482B (de)
WO (1) WO2001080310A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6784062B2 (en) * 2002-06-03 2004-08-31 Micron Technology, Inc. Transistor formation for semiconductor devices
JP3730947B2 (ja) * 2002-10-08 2006-01-05 松下電器産業株式会社 半導体装置の製造方法
EP1730596B1 (de) * 2004-03-30 2011-02-16 Carl Zeiss SMT AG Projektionsobjektiv und projektionsbelichtungsvorrichtung
JP4833211B2 (ja) 2004-08-06 2011-12-07 カール・ツァイス・エスエムティー・ゲーエムベーハー マイクロリソグラフィ用の投影対物レンズ
US7511890B2 (en) * 2005-02-04 2009-03-31 Carl Zeiss Smt Ag Refractive optical imaging system, in particular projection objective for microlithography
US7704865B2 (en) * 2005-08-23 2010-04-27 Macronix International Co., Ltd. Methods of forming charge-trapping dielectric layers for semiconductor memory devices
US9679602B2 (en) 2006-06-14 2017-06-13 Seagate Technology Llc Disc drive circuitry swap
KR100779395B1 (ko) * 2006-08-31 2007-11-23 동부일렉트로닉스 주식회사 반도체소자 및 그 제조방법
US9305590B2 (en) 2007-10-16 2016-04-05 Seagate Technology Llc Prevent data storage device circuitry swap
US20100330756A1 (en) * 2009-06-25 2010-12-30 International Business Machines Corporation Integrated circuit structure manufacturing methods using hard mask and photoresist combination
US8877596B2 (en) 2010-06-24 2014-11-04 International Business Machines Corporation Semiconductor devices with asymmetric halo implantation and method of manufacture
DE102010063782B4 (de) * 2010-12-21 2016-12-15 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Transistoren mit Metallgatestapeln mit großem ε und einem eingebetteten Verspannungsmaterial

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5513953A (en) * 1978-07-18 1980-01-31 Fujitsu Ltd Complementary integrated circuit
JPS5651872A (en) * 1979-10-05 1981-05-09 Oki Electric Ind Co Ltd Manufacture of complementary type mos transistor
JPH01145849A (ja) * 1987-12-01 1989-06-07 Fujitsu Ltd 半導体装置の製造方法
JPH029164A (ja) * 1988-06-28 1990-01-12 Matsushita Electric Ind Co Ltd パターン形成方法および半導体装置の製造方法
JPH02162739A (ja) * 1988-12-15 1990-06-22 Fujitsu Ltd 半導体装置の製造方法
US5227321A (en) * 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
JP2917696B2 (ja) * 1992-08-22 1999-07-12 日本電気株式会社 Cmos半導体装置の製造方法
JP3062398B2 (ja) * 1993-06-25 2000-07-10 松下電器産業株式会社 Cmos半導体装置の製造方法
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
US5489546A (en) * 1995-05-24 1996-02-06 Micron Technology, Inc. Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process
US6004854A (en) * 1995-07-17 1999-12-21 Micron Technology, Inc. Method of forming CMOS integrated circuitry
US5736440A (en) * 1995-11-27 1998-04-07 Micron Technology, Inc. Semiconductor processing method of forming complementary NMOS and PMOS field effect transistors on a substrate
JPH09205151A (ja) * 1996-01-26 1997-08-05 Sony Corp 相補型半導体装置の製造方法
JP2980057B2 (ja) * 1997-04-30 1999-11-22 日本電気株式会社 半導体装置の製造方法
US5904520A (en) * 1998-01-05 1999-05-18 Utek Semiconductor Corp. Method of fabricating a CMOS transistor
US6187619B1 (en) * 1998-02-17 2001-02-13 Shye-Lin Wu Method to fabricate short-channel MOSFETs with an improvement in ESD resistance
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance

Also Published As

Publication number Publication date
ATE434831T1 (de) 2009-07-15
JP2003531494A (ja) 2003-10-21
WO2001080310A1 (en) 2001-10-25
US6461908B2 (en) 2002-10-08
KR20020025892A (ko) 2002-04-04
JP4846167B2 (ja) 2011-12-28
EP1275147B1 (de) 2009-06-24
EP1275147A1 (de) 2003-01-15
TW533482B (en) 2003-05-21
KR100796825B1 (ko) 2008-01-22
US20010031522A1 (en) 2001-10-18

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