[go: up one dir, main page]

TW471149B - Semiconductor device, process for producing same, carrier substrate and process for producing same - Google Patents

Semiconductor device, process for producing same, carrier substrate and process for producing same Download PDF

Info

Publication number
TW471149B
TW471149B TW089120114A TW89120114A TW471149B TW 471149 B TW471149 B TW 471149B TW 089120114 A TW089120114 A TW 089120114A TW 89120114 A TW89120114 A TW 89120114A TW 471149 B TW471149 B TW 471149B
Authority
TW
Taiwan
Prior art keywords
block
metal film
metal
recessed
stepped
Prior art date
Application number
TW089120114A
Other languages
English (en)
Inventor
Yoshio Furuhata
Tsuyoshi Kobayashi
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Application granted granted Critical
Publication of TW471149B publication Critical patent/TW471149B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48478—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball
    • H01L2224/4848—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a wedge bond, i.e. wedge on pre-ball outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/85005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

471149 經濟部智慧財產局員工消費合作社印製 A7 -一--------五、發明說明（1 )發明背景 1 _發明領域 本發明關於一種半導體元件、用於製造該半導體元件 之方法、載體基材及其製造方法。 2.相關技藝說明 隨著諸如行動電話或其他之小型電子設備已經進入廣 泛的用途，已對於將尺寸減至最小並縮減欲被裝設在此類 電子設備中之半導體元件的製造成本有需求。其中一被安 装至引線框上之半導體晶片被樹脂遮蔽之傳統半導體元件 具有在内部與外部引線之間延伸的區域或安裝區域為相對 大之問題。此外，在BGA(球格栅陣列）型半導體元件中， 因為該半導體元件需要一用以安裝半導體晶片之基材，而 有另一個高製造成本之問題。 為了將半導體元件的尺寸絲最小並縮小其安裝面積 以及縮減製造成本，一種半導體元件已經被提出，例如， 在曰本未審查專利公告案（K〇kai)第9-162348號中。被揭 露在Kokai第9-162348號中之半導體元件包括一被安裝至 晶片黏接樹脂之半導體晶片、其中半導體晶片被以環氧樹 脂遮蔽之樹脂封裝體、以及覆蓋被形成在樹脂封裝體之安 裝表面上的樹脂突出部之金屬膜，該金屬膜藉由線接合之 方式被電氣地連接至半導體晶片的電極部段上。該半導體 元件有助於不需要内部與外部引線，與使用引線框的情況 相反，如在BGA型封裝體中般，安裝半導體晶片不需要 基材，並且金屬膜便於分散熱且因為金屬膜具有與接體端 {請先閱讀背面之注意事項再填寫本頁) i裝 -n —m —Λ l·---訂· -·線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 經濟部智慧財產局員工消費合作社印製 471149 A7 —----------B7___ 五、發明說明（2 ) " " 子相同的功能因此易於將晶片安裝至基材上之操作。 在上述形式為安袭高頻半導體晶片之半導體元件中， 其上安裝有半導體晶片之安裝部分金屬膜較佳被作為用以 避免噪音進入使得電性穩定之接地端子。因此，必須將接 地端子電氣地連接至安裝部分金屬膜上。 例如，在第6圖所示之半導體元件5丨中，一其上被安 裝有半導體晶片52之安裝部分金屬膜53與一電氣地連接至 半導體晶片52上之接體部分金屬膜54於安裝表面處被部分 地延伸。一接地接體部分55從安裝部分金屬膜”之周邊邊 緣被向外地延伸。半導體晶片52之一接地電極與接地接體 部分55被以一導線56相互地電氣連接，並且一信號電極與 接體部分金屬膜54被以一導線58相互地電氣連接。為了儘 可能密實地設計安裝部分金屬膜53並使導線56之長度儘可 能地短，接地接體部分55較佳儘可能地接近半導體晶=52 來被設置。藉此，對於被形成為階式組構狀態之安裝部分 金屬膜53已有需求。為了以階式組構狀態形成安裝部分金 屬膜53，一用以製造供半導體元件5丨製造用之載體基材方 法將會參考第7(a)至7(h)、8(a)與8(b)圖作說明。在此方面， 在避免第7(a)至7(h)圖中之導體部分金屬膜54之例示的同 日守’ 一用以形成安裝部分金屬膜53之程序將會被主要地說 明。在第7(a)圖中，一蝕刻光阻（感光光阻）61被塗覆在諸 如銅板之金屬基材60的個別表面上。接著，如第7(b)圖所 示，於钕刻光阻上疊對光罩的同時進行曝光與顯影程序， 以使一圖案62具有所需尺寸的中心空位空間（參見第8(a)) 圖。其後，如第7(c)圖所示，第一半蝕刻被進行（以移除 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 裝-----„----訂--------...線 (請先閱讀背面之注意事項再填寫本頁) 471149 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 大約四分之一的金屬板60厚度）使得接體凹入處〇被形 成。在此方面，當金屬板60為一銅板時，氯化鐵較佳被作 為蝕刻液。接著，在第7(d)圖中，蝕刻光阻61被去除，而 導致接體凹入處在金屬基材60中形成。 在第7(e)圖中，一蝕刻光阻（感光光阻）61再次被塗覆 在其上已被形成有接體凹入處63之金屬基材6〇上，並且在 蝕刻光阻上疊對光罩的同時進行曝光與顯影程序，使得圖 案64具有所需尺寸的中心空位空間（參見第8(b)圖）。接著， 在第7(f)圖中，一第二半蝕刻被進行（以移除大約四分之一 的金屬基材60厚度），使得一安裝凹入處65被形成。接下 來，在第7(g)圖中，蝕刻光阻61被去除以在階式組構狀態 中形成彼此具有不同厚度之接體凹入處63與安裝凹入處 65。在此方面，半蝕刻的面積與厚度可藉由改變在光罩中 之中心空位空間圖案的設計而自由地調整。 接著’在第7(h)圖中，在藉由電解液電鍍、真空沉積 或濺鍍之方式，以未顯示之光阻塗覆除了接體凹入處63與 女裝凹入處65之外的金屬基材60之剩餘部的同時，一多層 金屬膜被形成。因此，一在其上有安裝部分金屬膜53以階 式組構狀態被形成之載體基材66被形成。 將钱刻光阻61塗覆在金屬基材60上並在曝光與顯影之 後半蝕刻該金屬基材步驟的重複會使製造程序複雜而增加 製造成本。為了在一個相互對準之位置處形成具有不同尺 寸的第一中心空位圖案62與第二中心空位圖案64，要求一 兩度精確的對準，其係會造成許多報廢產品的產生而降低 產率。 中國國家標準ϋΑ4規格⑵〇 X 297公釐） ------------- ^-----„----t---------線' (請先閱讀背面之注意事項再填寫本頁) 6 W1149
五、發明說明（4 經濟部智慧財產局員工消費合作社印製 發明概要說明 =本發明之目的為提供一種能夠以低成本量產之 種用於製造該半導體μ之方法，使用該 件之載體基材，以及藉由解決上述在習知技" 之問題而簡化製造程序來製造該半導體元件之方法。 ,、根據本發明，有提供一種半導體元件’其係包含··一 半導體構件’係具有至少—個信號電極與至少—個接地電 極；一安裝部分金屬獏，係具有其上被安裝有該半導體構 件之底部區塊與位在該底部區塊周邊並在水平面上較該底 部區塊高之階形區塊；—接體部分金屬膜，係與該安裝部 分金屬膜關並於其周邊區域處被配置；電氣連接構件， 其係用以將半導體構件之信號電極與接體部分金屬膜連 接，並將半導體構件之接地電極與安裝部分金屬膜之階形 區塊連接；以及-心賴何體構件、電氣連接構件、 及安裝部分金屬膜與接體部分金屬膜之至少一個安裝/連 接側邊之樹脂。 安裝部分金屬膜與接體部分金屬膜的至少一者包含由 從底部續貫成層之一金層、一鈀層'_鎳層及一鈀層構成 之四層成膜。 根據本發明之另-層面，提供有_適於供製造半導體 元件用之載體基材，該基材係'包含：_金屬基底’其係具 有至少-個基準表面、一中心凹入區塊與位在該中心凹入 區塊周邊處之階形凹入區塊、一狁其 •1文&旱表面中心凹入區塊 之深度比該階形凹人區塊更大的深度；亦階形 本紙張尺度適用中國國家標準（CNS)A4規格（210 請 先 閱 讀 背 面 之 注 意 事 項 再 填 寫 頁 裝 訂 線 7 471149 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 A7 ________B7 _五、發明說明（5 ) 區塊分隔並於其周邊區域處被配置之周邊凹入區塊之金屬 基底；被形成在中心凹入區塊與階形凹入區塊上之安裝部 分金屬膜；以及被形成在該周邊凹入區塊上之接體部分金 屬膜。 與上述相同的方法，安裝部分金屬膜與接體部分金屬 膜之至少一者包含由從金屬基底貫續成層之一金層、一鈀 層、一鎳層、及一鈀層所構成之四成層膜。 根據本發明又一層面，提供有一用以製造載體基材之 方法’其係包含下列步驟：以蝕刻光阻塗覆包括基準表面 之金屬基材的個別表面；部分地移除在金屬基底之基準表 面上的蝕刻光阻，以便形成一中心空位圖案，於該中心空 位圖案周邊處形成環狀空位圖案，並形成與該環狀空位圖 案隔開之連接空位圖案；藉由使用蝕刻光阻作為一罩幕來 半蝕刻金屬基底，並且側蝕刻一部分在中心空位圖案與環 狀空位圖案之間的金屬基底，以形成一包括一中心凹入 塊與一位在中心凹入區塊周邊處之階形凹入區塊，一從 準表面之中心凹入區塊的深度比從基準表面之階形凹入 塊更大的深度之安裝凹人區塊，並且亦形成_與該階形 入區塊隔開並於其周邊區域處被配置之周邊凹入區塊；" 別在安裝凹入區塊與周邊凹入區塊上形成一安装部分金屬 膜與-接體部分金屬膜；以及從金屬基底上移除蝕刻光 阻。 根據本發明再一層面，提供有一用以製造半導體元件 之方法，其係包含下列步驟： (a)形成一載體基材； 基 區 凹 分 -I I ^ -----r---^ --------—線、 (請先閱讀背面之注意事項再填寫本頁) 本紙張&度1时闕家標準（CNS)A4規格（210 X ;公复「 471149 A：
五、發明說明（6 ) :b)在安裝部分金屬膜之底部區塊上安裝具有”、— 個信號電極與至少―個㈣電極之何體構件T (C)將半導體構件之信带 、， 乜琥兒極電乳地連接至接體部分上，亚將半導體構件之接地電極與安裝部膜之階形區塊連接； ，m ⑷以用以遮蔽半導體構件之光阻遮蔽電氣連接構件 並至少遮蔽連接安裝部分金屬膜與接體部分金 媒之安裝/連接側邊，以便形成_經遮蔽部分；及 ⑷從載體基材上移除遮蔽部分並連同安裝部分金膜與接體部分金屬膜一起移除。 -方法進-步包含-用以在半導體構件被安裝在安穿 部分金屬膜之底部區塊上之後，在安裝部分金屬膜盘接體 部分金屬膜之至少一者上形成一柱检隆起部之步驟。 遮蔽部分藉由蝕刻金屬基底而從載體基材上被移除。 另外，遮蔽部分藉由剝除載體基材之遮蔽部分而被從載體 基材上移除。 屬 以 屬 (請先閱讀背面之注意事項再填寫本頁) 裝 訂： 線- 經濟部智慧財產局員工消費合作社印製 附呈囷式之簡短說明第1(a)至l(j)圖例示一用以製造半導體元件之方法 第2圖為金屬膜之一例示之截面圖；第3圖如在第1(b)圖中之箭頭方向c_c所見之圖；第4(a)至4(c)圖例示蝕刻光阻圖案之某種變化；第5圖顯示在本發明之一實施例中之蝕刻條件 第6圖為習知技藝半導體元件之截面圖； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 9 經濟部智慧財產局員工消費合作社印制衣 4^1149 A： ^------B7 五、發明說明（7 ) 第7(a)至7(h)圖例示傳統用以製造載體基材之方法； 以及 第8(a)至8(b)圖分別例示習知技藝蝕刻光阻。 較佳實施例之詳細說明 本發明將會參考例示在附呈圖式中之較佳實施例而在 下文中作詳細地說明。 在此實施例中’將會說明其上帶有一供諸如行動電話 用之高頻類比1C的半導體元件以及一用以製造該半導體元 件之方法。第1 (a)至i (j)圖例示一用以製造該半導體元件 之方法，第2圖為金屬膜之一例示之戴面圖；以及第3圖為 如在第1(b)圖中箭頭方向c-c中所見之圖。 最初，將會說明半導體元件之結構。參考第】⑴圖， 標號1表至一具有下列結構之半導體元件。一半導體晶片2 經由一黏著層3而被安裝至以階式組構狀態被形成之安裝 部分金屬膜4之底部上。-優於散熱能力與導電性之材料， 諸如包含銀顆粒之導電環氧樹脂，較佳被使用於形成黏著 層3。在半導體晶片2之電極部段2神之接地電極被以金導 線6或相似者電氣地連接至一肩狀部如上，該肩狀部係以 比底部高的水平在安裝部分金屬膜4之底部周圍被形成。 此外，在半導體晶片2之電極部段^中之信號電極被以金 導線6或相似者於電氣地連接至_接體部分金屬心上，該 接體部分金屬膜係於兩者之間的空間處在安裝部分金屬膜 4周圍被形成。半導體晶片2、支撐半導體晶片2之安裝部 分金屬膜4、及接體部分金屬膜5被埋入由環氧樹脂形成之 本紙張尺度適用中國國豕標準（CNS〉A4規格（2】〇 X 297公爱）
------------- 裝! (請先閱讀背面之注意事項再填寫本頁) i線· 10 A：
樹脂遮蔽部分7。安裝部分金屬膜4與接體部分金屬獏5在 樹脂遮蔽部分7之-安裝表面上被暴露。根據此實施例土 安裝部分金屬膜4亦被作為晶粒塾、一散熱片、及一接地 471149 五、發明說明（8 ) 端子，而接體部分金屬膜5會有作為信號線之接體端子^ 作用。 安裝部分金屬膜4與接體部分金屬膜5由多層金屬膜形 成。在此實施例中’如第2圖所示，多層金屬膜被由在界 定安裝表面之外部層上貫續地覆蓋之一金層9、一鈀層1〇、 一鎳層11、及一鈀層12的四層膜構成。在考慮外層與基材 端子以及内層與導線6的焊料黏著性的同時’各種金屬層 之結合可被採用。 接下來，參考第1(a)至l(j)圖與第3圖，一用以製造半 導體元件1之方法將會說明於下·· 在第1(a)圖中，一蝕刻光阻14被塗覆在諸如銅板之金 屬基材13的個別上部與下部表面上。金屬基材的厚度⑴ 較佳為約0.125mm。例如，一感光光阻較佳被作為一蝕刻 光阻14。在將光罩（未顯示）覆蓋在姓刻光阻μ上之後，與 其中金屬薄膜欲藉由曝光並顯影钱刻光阻而被形成之區 塊一致之部分的蝕刻光阻;u被移除，而形成第1(b)圖所示 的光阻圖案15。更具體地，如第3圖所示，一方形中心空 位圖案20與一圍繞中心空位圖案2〇之方形環狀空位圖案 分別對應於金屬基材13之安裝凹入處16欲在其中被形成之 區塊而被形成。此外，一連接空位圖案22(未顯示於第3圖 中）對應於一金屬基材13之連接凹入處17欲被形成於其中 之區塊而被形成，如第1(b)圖所示。如第3圖所示，環狀 ί紙張尺ϋ用fiiii"準（CNS)A4_規格（210 x 297公复） ---裝-----Γ---訂------—-線 (請先閱讀背面之注意事項再填寫本頁} 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 11 471149 A7 五、發明說明（9 ) 工位圖案21的見度較佳為〇(}3麵至^加麵，並且在中〜 與環狀空位圖案20、21之間的敍刻光阻14之寬度較㈣ 0.04至 〇.〇6mm。 、糟下來’在第1刚中，金屬基材13在使祕刻光阻 作為-罩幕的同時被半姓刻，以形成安裝凹入處Μ與連接 凹入處17。更具體地，部分的金屬基材邮環狀空位圖案 21與中心空位圖案2〇之間藉由側蝕刻而被移除，以形成具 有比中〜部分更南的肩狀部或階形區塊之安裝凹入處1 6， 與其同時地，連接凹入處17在與安裝凹入處16相距一段距 離處在安裝凹入處16周圍被形成。 訂 如此，安裝凹入處16以及在相距安裝凹入處16一段距 離處圍繞安裝凹入處之連接凹入處17藉由包括半钱刻與側 蝕刻之單一曝光蝕刻程序而被形成。在此方面，半蝕刻之 線 面積與/或深度可藉由改變供環狀空位圖案2丨與中心空位 圖案20用之罩幕設計而作調整，諸如其尺寸或形狀。當鋼 板被作為金屬基材時，氣化鐵或相似者較佳被作為蝕刻 液。安裝凹入處16的深度（其中心部分）以及連接凹入處之 深度大致相同，且較佳為約1/2t#〇〇6mm至〇〇8mm。 接著，在第i(d)圖中，多層金屬膜在安裝凹入處16與 連接凹入處1 7中藉由使用蝕刻光阻14作為一罩幕來進行電 鍍而被形成，以分別產生安裝部分金屬膜4與連接部分金 屬膜5。如上所述，多層金屬膜為一層由在界定安裝表面 之外層上貫續地覆蓋之一金層9、一把層1Q、一鎳層η、 及一鈀層12所構成的四層膜。在此方面，安裝凹入處16與 連接凹入處17在蝕刻光阻14已被移除後被電解液電鍍，代 本紙張尺度適用中國國家標準（CNS)A4規格（2〗0 X 297公釐） 12 471149 五、發明說明（10 ) 之以一供電鍍用之分離光阻圖案已被f +、 可以名h壯 口系匕被形战，電解液電鍍 文裝凹入處16與連接凹入處17中被進行。 〜金屬膜不僅可以藉由電解液電鍍被形成，還可以藉由 洛乳，積或濺鑛被形成。為增進金屬膜與金屬基材13之分 離，安裝凹入處16與連接凹入處17能夠被以供增進分離用 之材料塗覆’諸如導電糊劑。 接下來，在第1(e)圖中，載體基材18藉由移除塗覆金 屬基材13的個別表面之餘刻光阻而被得㈣。安裝部分金屬 膜4在载體基材18之中心部分中被形成為階式、组構狀態（如 在此實施例中之兩階肩狀部），並且接體部分金屬膜5在安 裝部分金屬膜周圍於多個位置處被形成。 接著，在第1(f)圖中，半導體晶片2經由黏著層3而被 安裝至在載體基材18中被形成之安裝部分金屬膜4上。 經濟部智慧財產局員工消費合作社印製 接下來’在第1 (g)圖中，諸如金隆起部之柱栓隆起部 19在安裝部分金屬膜4與接體部分金屬膜5之肩狀部如上被 形成。柱栓隆起部1 9可以如揭露般地被形成，例如，在曰 本未審查專利公告案（Kokai)第10-79448號中，藉由將金 球球接合至鈀層12上，在使用毛細現象的同時使用超音波 知·接’旦藉由毛細現象的向下移動而破壞金球’藉由毛 細現象向上的移動剪裁金導線。藉由以此方式破壞金球， 可能將金球堅固地接合至纪層12上。此外，因為柱栓隆起 部19與導線6被由相同的材料形成，因此在柱栓隆起處與 導線之間的黏著性被增加。關於此點，柱栓隆起部19可以 被省略’若導線6可以被直接地附著至接體部分金屬膜5與 肩狀部4a上。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 13 471149 發明說明（11 接著’在第1(h)圖中，半導體晶片2之電極部段23藉 由V線6被電氣地連接至在安裝部分金屬膜4與接體部分金 屬膜5中被形成之柱栓隆起部19上。在此程序中，導線接 合以此類導線6之一端最初被接合至電極部段2&上，接著 另一端被接合至柱栓隆起部19上之方式被進行。或是，導 線16之一端最初可以被接合至柱栓隆起部丨9上，接著，另 ‘被接合至電極部段2a上。在後者的情況中，可能減少 導線環路的高度。關於此點，金導線6可以是一被以絕緣 材料覆蓋之經覆蓋導線。 其後’在第l(i)圖中，載體基材18被插入欲被以環氧 樹脂遮蔽之樹脂遮蔽元件（未顯示）中。半導體晶片2與半 導體晶片欲被安裝於其上之安裝部分金屬膜4與接體部分 金屬膜5之表面被以樹脂遮蔽部分7覆蓋。 接下來’在第1 (j)圖中，樹脂遮蔽部分7與安裝部分 金屬膜4與接體部分金屬膜5一起被與載體基材18分離。分 離程序可以藉由以蝕刻方式來移除除了對應於安裝部分金 屬膜4與接體部分金屬膜5之區域外的金屬基材13，或是藉 由機械地剝除載體基材1 8之樹脂遮蔽部分7而被進行。 經 濟 部 智 慧 財 產 工 消 費 合 社 印 製 . 1、！ — 裝--- (請先閱讀背面之注意事項再填寫本頁) "線· /因為半導體元件1之安裝部分金屬膜4藉由半蝕刻而被 、成為卩自式組構狀悲，可能以最少長度的導線6而將在半 導體晶片2正向附近處被形成之肩狀部如與半導體晶片2之 =地電極連接。藉此，可能在接地端子部段中形成安裝部 分金屬膜4，其係避免噪音進入半導體晶片2中以增進遮蔽 的效果。 此外’因為安裝部分金屬膜4可以透過單一的曝光餘 ^張尺度x 297 姻 14 471149 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 本紙張尺度ϋ財目隊鮮（cNS)A4規格（2ig χ撕公髮-- A： 五、發明說明（12 ) 刻程序而被形成為階式組構狀態，因此可能將半導體元件 1之.製造程序大程度地簡化，藉此半導體元件能夠以 本量產。 根據使用在半導體元件i中之載體基材18以及用以製 造該半導體元件之方法，因為安裝部分金屬膜4可以藉: 單-的曝絲刻程序而被形成為階式組構狀態，因此不需 要進行第二次或進-步的曝光姓刻程序，其係如習知技: 般對於透過第-次曝光姓刻程序而被形成之姓刻光阻需^ 光罩的高精確對準，使得廢棄產品降低而改善產率。 第4(a)至4⑷圖例示姓刻光阻圖_的某些變化，諸 如第3圖所示者。在第4⑷时，有-與第3圖相似之方形 中心空位圖案20’並且有三個方形狀空位圖案21，亦即内 部、中間及外部空位圖案21。因此，有三個方形環狀姓刻 光阻圖案14，亦即，内部、中間及外部姓刻光阻圖案Μ。 該等方形環狀空位圖案21的寬度A較佳為〇〇44職。切 狀空位圖案2H的外部與中間_光阻圖案14較佳為 〇.〇36麵。在内部環狀空位圖案21與方形中心空位圖案 之間的内部姓刻光阻圖案14的寬度c較佳為〇 〇4〇咖。 第4⑻圖所示之钱刻光阻圖案】4與第4(a)圖相似，除 了外部與中間光阻圖案為規律中斷。空位圖案21的寬" 車父佳為〇.〇3〇mm。中間敍刻光阻圖案2ι的寬度G較佳為 0.050mm。内部、連續的银刻 …、 。糊_。 ，、的㈣先阻圖案之寬度Η較佳為 第4⑷圖所示之姓刻光阻圖案14亦與第4⑷圖相似， 除了内部、中間與外部方形環狀空位圖案Μ為規律中斷。 ^ ii — l·---^---------Μ (請先閱讀背面之注意事項再填寫本頁) 15 471149 經濟部智慧財產局員工消費合作社印製 五、發明說明（I3 中間空位圖案21的寬度佳為0 030匪。* 刻光阻圖案14之宫#^ f Rik 二 見又F較佳為0.050mm。内部蝕刻光阻圖 案14之見度Η較佳為〇.〇4〇mm。 弟5®為沿著第4⑷圖之χ_χ，截取之示意橫戴面圖， 亦員不在使用如第4(幻圖所示之蝕刻光阻圖案的情況 的姓刻條件。D表示從金屬基材13之上部表面至安裝凹入 處1J之肩狀區塊頂部之維度，而£表示從肩狀區塊的底部 安凌凹入處1 6之中心部分的維度。若蝕刻時間太長， 空位圖案21中之蝕刻將會不完全的方式下，維度D(D 0.010mm)將會為不可接受者。另—方面，若似彳時間八 長以對應於中心空位圖案2〇之安裝凹入處i 6的區塊將會 被過度地蝕刻的方式下，維度E(E-〇〇i5mm)將會為不可 一者這疋由於钱刻速度差所造成的。所以，將必須調 節姓刻時間，以便滿足維度D與E。 當根據本發明之半導體元件及其製造方法被使用時， 可能將在半導體晶片之正向附近處被形成之肩狀部以最小 長度的導線連接至半導體晶片之接地電極上，因為安裝部 分金屬膜藉由半姓刻而被形成為階式組構狀態。藉此，安 裝部分金屬膜可以在接地端子部段中被形成，以避免噪音 進入半導體晶片中並增進遮蔽效果。 因為安裝部分金屬膜可以透過單一曝光蝕刻程序被形 成為階式組構狀態，因此可能將用以製造半導體元件之方 法大幅度地簡化，藉此能夠以低成本來量產半導體元件。 根據使用在半導體元件中之載體基材及其製造方法， 因為女裝部分金屬膜可以藉由單一曝光蝕刻程序而被形成 以 太 (請先閱讀背面之注意事項再填寫本頁} ---------• — 訂---------線 本紙張尺度翻+關家鮮（CNS)A4^(21Gx297公髮 16 471149 A7 __B7 五、發明說明（Μ 為階式組構狀態，因此不需要進行第二次H 钱刻程序，其係如f知技藝般對於透過二/的曝光 序:被形成之钱刻光阻需要光罩的高精確對； 產品降低而改善產率。 彳于廢棄 雖然已對於如上所述之較佳實施例進行說明，但 明不應被限制在上述之實施财，當 x 各心 …'應包括其各種的變 “正’而不會背離本發明之精神。例如，多層金屬膜 之結構與/或材料可以被適當地變化，或是安裝部' 膜4之肩狀部4a的數目可以被任意地選擇。 ---裝——— l·---訂· f靖先閱讀背面之注意事項再填寫本頁) •線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 17 471149 A7 B7_ 五、發明說明（15 ) 元件標號對照表 經濟部智慧財產局員工消費合作社印製 1 半導體元件 2 半導體晶片 2a 電極部段 3 黏著層 4 安裝部分金屬膜 4a 肩狀部 5 接體部分金屬膜 6 金導線 7 樹脂遮蔽部分 9 金層 10 飽層 11 鎳層 12 纪層 13 金屬基材 14 蝕刻光阻 15 光阻圖案 16 安裝凹入處 17 連接凹入處 18 載體基材 19 柱栓隆起部 20 中心空位圖案 21 環狀空位圖案 22 連接空位圖案 51 半導體元件 52 半導體晶片 53 安裝部分金屬膜 54 接體部分金屬膜 55 接地接體部分 56 導線 58 導線 60 金屬基材 61 蝕刻光阻 62 圖案 63 接體凹入處 64 圖案 65 安裝凹入處 66 載體基材 (請先閱讀背面之注意事項再填寫本頁) 裝-----：----訂---------線， 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 18

Claims (1)

  1. 471149 2. 經濟部智慧財產局員工消費合作社印f 3. 申請專利範圍 • 一種半導體元件，其係包含： —半導體構件，係、具有至少一個信號電極與至小 一個接地電極； ' ^ _ 一安裝部分金屬膜，係具有其上被安装有該半導 體構件之底部區塊與位在該底部區塊周邊處並在水平 面上較該底部區塊高之階形區塊； ,一接體部分金屬膜，係與該安裝部分金屬膜隔開 並於其周邊區域處被配置； 電氣連接構件，其係用以將該半導體構件之該信 號電極與該接體部分金屬膜連接，並將該半導體構件 之該接地電極與該安裝部分金屬膜之該階形區塊連 接；以及 二一用以遮蔽該半導體構件、該電氣連接構件'及 該安裝部分金屬膜與該接體部分金屬膜之至少一個安 褒/連接側邊之樹腊。 如申請專利範圍第！項之半導體元件，其中該安裝部 分金屬膜與該接體部分金屬膜之至少一者包含由從底 部續貫成層之-金層、―把層、一鎳層及一把層構成 之四層膜。 一種適於供製造半導體元件用之載體基材，該基材係 包含： 中 入 一金屬基底，其係具有至少一個基準表面、一 心凹入區塊與位在該中心凹入區塊周邊處之階形凹 區塊、一從該基準表面該中心凹入區塊之深度比該
    -19- W1149
    經濟部智慧財產局員工消費合作社印制衣 形凹入區塊更大的深度； 該金屬基底係亦具有一與該階形凹入區塊分隔I 於其周邊區域處被配置之周邊凹入區塊； 被形成在該中心凹入區塊與該階形凹入區塊上 之安裝部分金屬膜；以及 一被形成在該該周邊凹入區塊上之接體部分金屬 膜。 4.如申睛專利範圍第3項之載體基材，其中該安裝部分 金屬膜與該接體部分金屬膜之至少一者包含由從該金 屬基底貫續地成層之一金層、一纪層、一鎳層、及一 銳層所構成之四成層膜。 5 ’ 種用以製造載體基材之方法’係包含下列步驟： 以姓刻光阻塗覆包括基準表面之一金屬基材的個 別表面； 部分地移除在該金屬基底之該基準表面上的該蝕 刻光阻，以便形成一中心空位圖案，於該中心空位圖 案周邊處形成一環狀空位圖案，並形成一與該環狀空 位圖案隔開之連接空位圖案； 藉由使用該蝕刻光阻作為一罩幕來半蝕刻該金屬 基底’並侧蝕刻一部分在該中心空位圖案與該環狀空 位圖案之間的該金屬基底，以形成一包括一中心凹入 區塊與一位在該中心凹入區塊周邊處之階形凹入區 塊、一從該基準表面之該中心凹入區塊的深度比從該 基準表面之該階形凹入區塊更大的深度之安裝凹入區 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -------------裝--------訂-------—線 (請先閱讀背面之注意事項再填寫本頁) 20 471149
    塊’並且亦形成一與該階形凹入區塊隔開並於其周线 區域處被配置之周邊凹入區塊； 一〜分別在駐裝以區塊與該周相人區塊上形成 一安裝部分金屬膜與一接體部分金屬膜；以及 從該金屬基底上移除該蝕刻光阻。 6·如申請專利範圍第5項之方法，其令該中心空位圖案 與該環狀空位圖案具有正方形或長方形的形狀。 7· -種用以製造半導體元件之方法，其係包含下列步 驟： 經濟部智慧財產局員工消費合作社印製
    (a)形成一載體基材包含： 以蝕刻光阻塗覆包括一基準表面之一金屬基 材的個別表面； 部分地移除在該金屬基底之該基準表面上的 5亥蝕刻光阻，以便形成一中心空位圖案，於該中心空 位圖案周邊處形成一環狀空位圖案，並形成一與該環 狀空位圖案隔開之連接空位圖案； 藉由使用該蝕刻光阻作為一罩幕來半蝕刻該 金屬基底，並側I虫刻一部分在該中心空位圖案與該環 狀空位圖案之間的該金屬基底，以形成一包括一中心 凹入區塊與一位在該中心凹入區塊周邊處之階形凹入 區塊、一從該基準表面之該中心凹入區塊的深度比從 該基準表面之該階形凹入區塊更大的深度之安裝凹入 區塊’並且亦形成一與該階形凹入區塊隔開並於其周 邊區域處被配置之周邊凹入區塊；
    本紙張尺度適用中關家標準（CNS)A4規格（21G x 297公爱
    . 裝 訂· (請先閱讀背面之注意事項再填寫本頁) 丨線. 21 經濟部智慧財產局員工消費合作社印製 471149 六、申請專利範圍 分別在該安裝凹入區塊與該周邊凹入區塊上 形成一包括一底部區塊及一位在該底部區塊周邊處之 階形區塊的安裝部分金屬膜與一接體部分金屬獏；以 及 、 k 5亥金屬基底上移除該餘刻光阻； (b)在該安裝部分金屬膜之該底部區塊上安裝一 具有至少一個信號電極與至少一個接地電極之半導體 構件； (〇將該半導體構件之該信號電極電氣地連接至 該接體部分上，並將該半導體構件之該接地電極與該 安裝部分金屬膜之該階形區塊電氣連接； (d)以用以遮蔽該半導體構件之光阻遮蔽該電氣 連接構件並至少遮蔽該連接安裝部分金屬膜與該接體 部分金屬膜之安裝/連接側邊，以便形成一經遮蔽部 分；以及 (e)從該載體基材上移除該遮蔽部分並連同該安 裝部分金屬膜與該接體部分金屬膜一起移除。 8·如申請專利範圍第7項之方法，其係進一步包含一用 以在該半導體構件被安裝在該安裝部分金屬膜之該底 部區塊上之後，在該安裝部分金屬膜與該接體部分金 屬膜之至；一者上形成一柱栓隆起部之步驟。 9. 如申請專利範圍第7項之方法，其中該遮蔽部分藉由 蝕刻該金屬基底而從該載體基材上被移除。 10. 如申請專利範圍第7項之方法，其中該遮蔽部分藉由
    本紙張尺度剌巾關家標準(CNSM4規格（210 X 297公爱） Μ-----------------線 (請先閱讀背面之注意事項再填寫本頁) 22 47Π49 AS BS cs DS 申請專利範圍 剝除該載體基材之該遮蔽部分被從該載體基材上移 除 --------------------訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 23
TW089120114A 1999-10-01 2000-09-28 Semiconductor device, process for producing same, carrier substrate and process for producing same TW471149B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28095099A JP3691993B2 (ja) 1999-10-01 1999-10-01 半導体装置及びその製造方法並びにキャリア基板及びその製造方法

Publications (1)

Publication Number Publication Date
TW471149B true TW471149B (en) 2002-01-01

Family

ID=17632174

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089120114A TW471149B (en) 1999-10-01 2000-09-28 Semiconductor device, process for producing same, carrier substrate and process for producing same

Country Status (6)

Country Link
US (1) US6423643B1 (zh)
EP (1) EP1091401B1 (zh)
JP (1) JP3691993B2 (zh)
KR (1) KR100721839B1 (zh)
DE (1) DE60033901T2 (zh)
TW (1) TW471149B (zh)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143981A (en) 1998-06-24 2000-11-07 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
KR100369393B1 (ko) 2001-03-27 2003-02-05 앰코 테크놀로지 코리아 주식회사 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법
JP4054188B2 (ja) * 2001-11-30 2008-02-27 富士通株式会社 半導体装置
JP3783648B2 (ja) * 2002-04-10 2006-06-07 日立電線株式会社 配線板及びそれを用いた半導体装置の製造方法
US7368391B2 (en) * 2002-04-10 2008-05-06 Micron Technology, Inc. Methods for designing carrier substrates with raised terminals
JP2004103860A (ja) 2002-09-10 2004-04-02 Fujitsu Ltd 半導体装置、カメラモジュール及びその製造方法
TW586677U (en) * 2003-01-22 2004-05-01 Via Tech Inc Stack structure of chip package
US6894382B1 (en) * 2004-01-08 2005-05-17 International Business Machines Corporation Optimized electronic package
US7009286B1 (en) * 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
KR101091889B1 (ko) * 2004-01-17 2011-12-08 삼성테크윈 주식회사 연성회로기판
US20060087010A1 (en) * 2004-10-26 2006-04-27 Shinn-Gwo Hong IC substrate and manufacturing method thereof and semiconductor element package thereby
US8163604B2 (en) * 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
JP5051421B2 (ja) * 2006-06-30 2012-10-17 日立化成工業株式会社 実装基板
US8014154B2 (en) * 2006-09-27 2011-09-06 Samsung Electronics Co., Ltd. Circuit substrate for preventing warpage and package using the same
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
JP2009141054A (ja) * 2007-12-05 2009-06-25 Furukawa Electric Co Ltd:The 半導体装置
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8176628B1 (en) 2008-12-23 2012-05-15 Amkor Technology, Inc. Protruding post substrate package structure and method
US20170117214A1 (en) 2009-01-05 2017-04-27 Amkor Technology, Inc. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
TWI557183B (zh) 2015-12-16 2016-11-11 財團法人工業技術研究院 矽氧烷組成物、以及包含其之光電裝置
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
KR101486790B1 (ko) 2013-05-02 2015-01-28 앰코 테크놀로지 코리아 주식회사 강성보강부를 갖는 마이크로 리드프레임
CN103346140A (zh) * 2013-06-10 2013-10-09 孙青秀 一种基于框架采用镀银技术的封装件及其制作工艺
KR101563911B1 (ko) 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
JP6149072B2 (ja) 2015-07-07 2017-06-14 アオイ電子株式会社 半導体装置およびその製造方法
JP6863846B2 (ja) * 2017-07-19 2021-04-21 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法
JP6927634B2 (ja) * 2017-09-20 2021-09-01 大口マテリアル株式会社 半導体素子搭載用基板及びその製造方法
JP7134137B2 (ja) * 2019-05-31 2022-09-09 三菱電機株式会社 半導体装置
JP7271337B2 (ja) 2019-06-27 2023-05-11 新光電気工業株式会社 電子部品装置及び電子部品装置の製造方法
CN113791030B (zh) * 2021-09-13 2024-05-31 国网山东省电力公司电力科学研究院 一种埋地金属构件土壤腐蚀原位检测传感器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
US6072239A (en) 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
JP3181229B2 (ja) * 1996-07-12 2001-07-03 富士通株式会社 半導体装置及びその製造方法及びその実装方法及びリードフレーム及びその製造方法
JPH1167838A (ja) * 1997-08-22 1999-03-09 Matsushita Electric Ind Co Ltd バンプ付電子部品の製造方法
JP3031323B2 (ja) * 1997-12-26 2000-04-10 日本電気株式会社 半導体装置とその製造方法
JP2000195984A (ja) * 1998-12-24 2000-07-14 Shinko Electric Ind Co Ltd 半導体装置用キャリア基板及びその製造方法及び半導体装置及びその製造方法
JP4362163B2 (ja) * 1999-04-06 2009-11-11 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
DE60033901D1 (de) 2007-04-26
EP1091401B1 (en) 2007-03-14
KR20010070117A (ko) 2001-07-25
KR100721839B1 (ko) 2007-05-28
JP2001102484A (ja) 2001-04-13
JP3691993B2 (ja) 2005-09-07
EP1091401A2 (en) 2001-04-11
DE60033901T2 (de) 2007-07-12
EP1091401A3 (en) 2003-07-02
US6423643B1 (en) 2002-07-23

Similar Documents

Publication Publication Date Title
TW471149B (en) Semiconductor device, process for producing same, carrier substrate and process for producing same
TW418514B (en) Semiconductor device and method of producing the same
TW560234B (en) Wiring substrate for small electronic component and manufacturing method
TW535462B (en) Electric circuit device and method for making the same
TW501382B (en) Semiconductor device and process therefor
TW498508B (en) Semiconductor package and method of fabricating the same
TW456013B (en) Heat spreader substrate structure and the process thereof
JPH11233683A (ja) 樹脂封止型半導体装置とそれに用いられる回路部材および樹脂封止型半導体装置の製造方法
CN101246893A (zh) 具有高传导面积的集成电路封装体及其制作方法
USRE49286E1 (en) Method of making flip chip
US20130130493A1 (en) Connecting pad producing method
TW201813034A (zh) 導線架及電子組件裝置
TWI309962B (en) Circuit device and menufacturing method thereof
CN103489802A (zh) 芯片封装结构及形成方法
TW441062B (en) Carrier substrate for producing semiconductor device
JP3097653B2 (ja) 半導体装置用パッケージおよびその製造方法
TW200832573A (en) Fabrication method of semiconductor package
TW200532811A (en) Method for fabricating a packaging substrate
JP2000332145A (ja) 樹脂封止型半導体装置用の回路部材とそれを用いた樹脂封止型半導体装置および回路部材の製造方法
CN111146091B (zh) 一种散热封装结构的制造方法及散热结构
TWI455216B (zh) 四邊扁平無接腳封裝方法及其製成之結構
TW200826206A (en) Semiconductor fabrication method and structure thereof
CN102945840B (zh) 半导体芯片封装结构及封装方法
US6627993B1 (en) Semiconductor device having an electrical contact and a dielectric lining in a contact region
TW201015674A (en) Package and fabricating method thereof

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees