4231〇9 A7 B7 經濟邹智慧財產局員工消費合作杜印®ί 五、發明說明（）5-1發明領域 本發明係有關於一種製造半導體元件的方法，特別 是有關於一種製造具有自對準接觸窗（self a|ign contact : SAC)技術之半導體元件的方法-5-2發明背景 隨著超大型積體電路半導體元件的進步，半導體元 件之大小變得越來越小’使得單一半導體元件的寬度變 得越來越小，而半導體元件的製造通常是包含了電晶 體、位元線以及字元線的製造’更包含了接觸窗的製造。 所以對設計者而言’以自對準（self-align)技術製造的半 導體元件中的小面積之元件是非常重要的。 用以製造具有複晶矽化金屬（polycide)閘極，而具 有自對準接觸窗之半導體元件，通常會遭遇一些問題， 諸如在輕摻雜汲極（Lightly Doped Drain : LDD)氧化製程 之後，主要因為滲透出氡化層側壁之複晶矽化金屬所導 致的粗糙之側壁。上述的此種現象經常會導致粗糙的側 壁’其會使得在複晶硬化金屬閘極（ρ ο I y c i d e g a t e)和接觸 窗（contact)之間的絕緣劣化（degrade)。 以製造一半導體元件’如字元線、位元線' 或是電 晶體，的方法為例’用一個電晶體製造方法作為習知技 術之說明。當提供底材1 0作為上述製程之用時，閘極氧 化層1彳、複晶矽層1 2、矽化鎢層彳3陸續被沉積在底材 ---.1,---,--- !t--------訂_ {請^^讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2i0 X 297^7 A7 B7 4 2310 9 五、發明說明（） 1 0上。然後視需要而選擇要或是不要沉積一層以正矽酸 乙酯（Tetra-Ethy卜Ortho-Silicate : TEOS)為原料，以化 學氣相沉積（Chemical Vapor Deposit 丨 on: CVD)方法沉 積之氧化層14，此處以沉積上一層TEOS氧化層14於 矽化鎢層1 3上為例》氬化矽層1 5形成於TEOS氧化層 14上，然後接著旋塗、曝光並顯影而產生的一光阻層 1 6，以在非等向性（a n i s 〇 t「〇 p丨c a 11 y)地蝕刻氮化矽層15 和TE0S氧化矽層14時，作為蝕刻罩幕（mask)之用。然 後參考圖一 B，剝除光阻層1 6並接著非等向性的蝕刻複 晶矽層1 2和矽化鎢層1 3，以形成複層結構。上述的複 層結構包含了經過蝕刻的複晶矽層1 2、經過蝕刻的矽化 鎢層1 3、經過蝕刻的T E 0 S氧化層1 4以及經過蝕刻的 氮化矽層1 5 » 參考圖一 C，形成間隙壁2 0於前述的複層結構的 侧壁上，以完成半導體元件之製造。然而經過其後續步 驟，會使用氧化製程以及自對準技術（self-align contact : SAC)來處理半導體元件。所以形成於半導體元 件上的介電層2 5，例如氧化矽層，參考圖一 D，會被蝕 刻出一接觸窗，所以一部份的底材1 0被裸露。然後，形 成導電層30並將其圖樣化（pattern)於裸露的部分間隙壁4231〇9 A7 B7 Economics Zou Intellectual Property Bureau Consumer Consumption Cooperation Du Yin®ί 5. Description of the Invention (5) Field of the Invention The present invention relates to a method for manufacturing semiconductor components, and more particularly to a method for manufacturing semiconductor devices with self-alignment. Method for semiconductor element of self- | ign contact (SAC) technology-5-2 Background of the Invention With the advancement of semiconductor elements of very large integrated circuits, the size of semiconductor elements has become smaller and smaller, making a single semiconductor element As the width of semiconductor devices becomes smaller and smaller, the manufacturing of semiconductor devices usually includes the manufacture of transistors, bit lines, and word lines, and it also includes the manufacturing of contact windows. Therefore, it is very important for designers to use small-area components of semiconductor components manufactured by self-align technology. Semiconductor devices with polycide gates and self-aligned contact windows often encounter problems, such as after the lightly doped drain (LDD) oxidation process. Rough sidewalls caused by polycrystalline silicide metal that permeates the side walls of the halide layer. Such a phenomenon as described above often results in a rough side wall, which degrades the insulation between the polycrystalline hardened metal gate (ρ ο y c i d e g a t e) and the contact. Taking a method of manufacturing a semiconductor element 'such as a word line, a bit line' or a transistor as an example ', a method of manufacturing a transistor is used as an explanation of the conventional technique. When the substrate 10 is provided for the above process, the gate oxide layer 1 彳, the polycrystalline silicon layer 1 2 and the tungsten silicide layer 彳 3 are successively deposited on the substrate ---. 1, ---, --- -! t -------- Order_ {Please ^^ Read the notes on the back and fill in this page) This paper size applies to China National Standard (CNS) A4 (2i0 X 297 ^ 7 A7 B7 4 2310 9 V. Description of the invention (1) 10. Then, if necessary, choose whether or not to deposit a layer of Tetra-Ethy Ortho-Silicate (TEOS) as a raw material, and use chemical vapor deposition (Chemical Vapor Deposit)丨 on: CVD) oxide layer 14 is deposited. Here, a TEOS oxide layer 14 is deposited on the tungsten silicide layer 13 as an example. A silicon argon layer 15 is formed on the TEOS oxide layer 14, and then spin-coated, A photoresist layer 16 produced by exposure and development is used as an etching mask when the silicon nitride layer 15 and the TEOS silicon oxide layer 14 are anisotropically etched (anis 〇t "〇p 丨 ca 11 y"). (Mask). Then referring to FIG. 1B, the photoresist layer 16 is stripped, and then the polycrystalline silicon layer 12 and the tungsten silicide layer 13 are anisotropically etched to form a multilayer structure. The layer structure includes an etched polycrystalline silicon layer 1 2. An etched tungsten silicide layer 1 3. An etched TE 0 S oxide layer 1 4 and an etched silicon nitride layer 1 5 »Referring to FIG. 1C, forming The spacer wall 20 is on the side wall of the aforementioned multi-layer structure to complete the manufacturing of the semiconductor device. However, after the subsequent steps, the semiconductor device is processed using an oxidation process and a self-align contact (SAC) technology. Therefore, a dielectric layer 25 formed on a semiconductor element, such as a silicon oxide layer, will be etched out of a contact window with reference to FIG. 1D, so a part of the substrate 10 is exposed. Then, a conductive layer 30 is formed and Pattern it on the exposed part of the gap wall
2 0以及裸露的部分閘極氧化層1 1上。然後移徐介電層 2 5，並且進行其後續步驟以形成半導體元件Q 當把氧化製程施於上述的半導體元件上時，由矽化 鎢層1 3的側壁上所產生的複晶矽，會導致粗糙並且有突 本紙張尺度適用令國國家標準（CNS)A4規格（21〇 X 297公釐） -----T---τι— 11 --------訂---- (諳先閱讀背面之江意事項再填寫本頁) 經濟部智慧財產局員工消費合作钍印製 經濟部智慧財產局員工消費合作社印製 4 23 1 Ο 9 _Β7_ 五、發明說明（） 出物的侧壁，此會導致複晶矽化金屬閘極和自對準接觸 窗之間的絕緣之退化（degrade)，而上述的現象則是因為 、厚度減少的間隙壁20之一部分間隙壁35所導致的。 5-3發明目的及概述 如上述之發明背景中，傳統方法之缺點，在後續的 氧化（快速熱處理）製程中，防止複層結構的側壁上產生複 晶矽化金屬突出物所導致的絕緣邊限（isolation margin) 降低是很重要的課題。本發明提供一種簡單並且極為可 行的方法，以製造使用自對準技術的半導體元件，其可 以增加複晶矽化金屬閘極與自對準接觸窗之間的絕緣邊 限，此處即將揭露上述製造半導體元件的方法。 根據以上所述之目的，本發明提供了一種一種製造 半導體元件的方法，此方法包含下列步驟：首先依序形 成第一氧化層、複晶矽層及複晶矽化金屬層於底材上， 其中複晶矽化金屬層為導電結構。形成氮化矽層於導電 結構上，並形成光阻圖案於氮化矽層上，然後蝕刻部份 氮化矽層以裸露出部份複晶矽化金屬層，以經蝕刻氮化 矽層為遮罩，並撥除光阻圖案。然後等向性蝕刻複晶矽 化金屬層，以於氮化矽層下方之複晶矽化金屬層中形成 底切。 此時複晶矽化金屬層之頂寬度小於氮化矽層寬 度，然後非等向性蝕刻複晶矽化金屬層，並蝕刻複晶矽 層直到裸露出部分第一氧化層，以形成複層結構。最後 本紙張尺度適用中國國家標準（CNS)A4規樁（210x 297公釐） / ϋ tsi u I t n d n t— n n-^nJ* n t n I n n I » (請^閱讀背面之沒意事項再填寫本頁> 4 23 1 Ο 9 Α7 經濟部智慧財產局員工消費合作社印製 B7五、發明說明（） 形成間隙壁（spacer)於複層結構側壁上，以形成半導體元 件，此退縮之複晶矽化金屬層的惻壁在一氧化步驟之 後，被阻止以致不能突出間隙壁。 5-4圈示簡單說明 本發明的特徵可以經由下列的圖式及其伴隨的說 明而得到更加清楚的了解，其中： 圖一 A顯示的是在導電結構（碎化鎮層）被触刻之 前，半導體元件之習知結構的剖面圖； 圖一 B顯示的是在形成複層結構之後，半導體元件 之習知結構的剖面圖； 圖一 C顯示的是在複層結構的側壁上形成間隙壁 之後，半導體元件之習知結構的剖面圖； 圖一 D顯示的是使用自對準技術，並且於接觸窗中 形成導電圖案後，半導體元件之習知結構的剖面圖； 圖二A顯示的是依據本發明的一較佳實施例，在導 電結構（矽化鎢層）被蝕刻之前，半導體元件之剖面圖； 圊二B顯示的是依據本發明的一較佳實施例，在形 成複晶矽化金屬層並加以圖案化（pattern)之後，半導體 元件之結構剖面圖； 圖二C顯示的是依據本發明的一較佳實施例，在可 選擇要不要形成的第二氧化層被進一步蝕刻*並且複晶 矽層也被蝕刻而形成複層結構之後，半導體元件之結構 ---------^---- ---- —---訂--------I {請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 經濟部智慧財產局員工消費合作社印製 23 1 U 9 A7 _B7_____五、發明說明（） 剖面圖； 圖二D顯示的是依據本發明的一較佳實施例，形成 間隙壁於複層結構側壁，並且因為後續的氡化製程而在 複層結構側壁上產生複晶矽化金屬突出物之後，半導體 元件之結構剖面圖； 圖二E顯示的是依據本發明的一較佳實施例，在形 成介電層於半導體元件上之後之結構剖面圖； 圖三A顯示的是依據本發明的另一較佳實施例，在 導電結構（矽化鎢層）被蝕刻之前，半導體元件之剖面圖； 圖三B顯示的是依據本發明的另一較佳實施例，在 形成複晶矽化金屬層並加以圖案化（p a 11 e r η)之後，半導 體元件之結構剖面圖； 圖三C顯示的是依據本發明的另一較佳實施例，在 可選擇要不要形成的第二氧化層被進一步蝕刻，並且複 晶矽層也被蝕刻而形成複層結構之後，半導體元件之結 構剖面圖； 圖三D顯示的是依據本發明的另一較佳實施例，形 成間隙壁於複層結構側壁，並且因為後續的氧化製程而 在複層結構側壁上產生複晶矽化金屬突出物之後，半導 體元件之結構剖面圖；以及 圖三Ε顯示的是依據本發明的另一較佳實施例，在 形成介電層於半導體元件上之後之結構剖面圖。 5-5發明詳細說明 -----Γ.---..--I I ·1 I 1 ---訂- - - ------/Λ, (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用t國國家標準（CNS)A4規格（210x 297公釐） 4 231^9 ^ A7 ___ B7_ 五、發明说明（） 在製造半導體元件，例如字元線、位元線或是電晶 體時，經常使用自對準（self-align)技術，並且通常會經 常使用諸如輕摻雜汲·極（LightlyDoped Drain : LDD)氧化 製程，然而上述製程必須要能避免滲透出氧化層側壁之 複晶矽化金屬所導致的粗糙側壁，然後才能避免在複晶 矽化金屬閘極（p〇丨ycide gate)和接觸窗（contact)之間的 絕緣劣化（degrade)。 在本發明的一較佳實施例中，以製造一半導體元 件，如字元線、位元線、或是電晶體的方法為例，在本 發明說明書中用一個電晶體製造方法作為習知技術之說 明°當提供底材40作為上述製程之用時，閘極氧化層 41，複晶矽層4 2、矽化鎢層4 3陸續被沉積在底材4 0上。 然後視需要而選擇要或是不要沉積一層正矽酸乙§旨 (Tetra-Ethy]-Ortho*Silicate ： TE0S)氧化層 44，換句話 說，此形成T E 0 S氧化層4 4的沉積步驟，在另—實施例 中是可以省略的。TE0S氧化層44可以是用正矽酸乙賴 (Tetra-Ethy卜Ortho-Silicate : TE0S}為原料，以化學氣 相沉積（Chemica 丨 Vapor Deposition: CVD)方法沉積之 氧化層44，在本發明的實施例中，以沉積上一層te〇s I 氧化層44於矽化鎢層43上為例進行後續說明。氮化石夕 層45形成於TE0S氧化層44上，然後接著旋塗、曝光 並顯影而產生在氮化矽層45上的光阻層46，在非等向 性（anisotropically)地蝕刻氮化矽層45和TEOS氧化石夕 層44時，作為蚀刻罩幕（mask)之用。 本紙浪尺度適用中國國家梂準（CNS ) A4g UI0X297公釐} f請先閲讀背面之注§項再嗔寫本頁) '壯衣2 0 and an exposed part of the gate oxide layer 1 1. Then, the dielectric layer 25 is removed, and the subsequent steps are performed to form a semiconductor element Q. When an oxidation process is applied to the above-mentioned semiconductor element, the polycrystalline silicon generated on the sidewall of the tungsten silicide layer 13 will cause Rough and embossed paper sizes Applicable to the national standard (CNS) A4 specification (21〇X 297 mm) ----- T --- τι-- 11 -------- Order ---- (Please read the Jiang Yi matter on the back before filling out this page.) Consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs 钍 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 23 1 Ο 9 _Β7_ V. Description of the invention () Side wall, which will cause the degradation of the insulation between the polysilicon gate and the self-aligned contact window, and the above phenomenon is caused by a part of the partition wall 35, which is a part of the partition wall 20 with a reduced thickness . 5-3 Purpose and summary of the invention As in the background of the invention described above, the disadvantages of the traditional method are to prevent the insulation margin caused by the polycrystalline silicided metal protrusions on the side wall of the multilayer structure in the subsequent oxidation (rapid heat treatment) process. (Isolation margin) is a very important issue. The invention provides a simple and extremely feasible method for manufacturing a semiconductor device using self-aligned technology, which can increase the insulation margin between a polycrystalline silicon silicide gate and a self-aligned contact window. The above manufacturing will be disclosed here. Method for semiconductor components. According to the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device. The method includes the following steps: firstly sequentially forming a first oxide layer, a polycrystalline silicon layer, and a polycrystalline silicon silicide layer on a substrate; The polycrystalline silicon silicide layer is a conductive structure. A silicon nitride layer is formed on the conductive structure, and a photoresist pattern is formed on the silicon nitride layer. Then, a part of the silicon nitride layer is etched to expose a part of the polycrystalline silicon silicide layer, and the etched silicon nitride layer is used as a mask. Cover and remove the photoresist pattern. The polycrystalline silicon silicide layer is then etched isotropically to form an undercut in the polycrystalline silicon silicide layer under the silicon nitride layer. At this time, the top width of the polycrystalline silicon silicide layer is smaller than the width of the silicon nitride layer, and then the polycrystalline silicon silicide layer is anisotropically etched, and the polycrystalline silicon layer is etched until a part of the first oxide layer is exposed to form a multilayer structure. In the end, the paper size applies the Chinese National Standard (CNS) A4 gauge (210x 297 mm) / si tsi u I tndnt— n n- ^ nJ * ntn I nn I »(Please read the unintentional matter on the back and fill in this Page > 4 23 1 Ο 9 Α7 Printed by B7 of the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Forming a spacer on the side wall of the multilayer structure to form a semiconductor element, this shrinking polycrystalline siliconization After the oxidizing step of the metal layer is prevented from protruding from the interstitial wall, a brief description of the features of the present invention can be obtained through the following drawings and accompanying descriptions, among which: FIG. 1A shows a cross-sectional view of a conventional structure of a semiconductor device before a conductive structure (fragmented ballast) is etched. FIG. 1B shows a conventional structure of a semiconductor device after forming a multilayer structure. Cross-sectional view; Fig. 1C shows a cross-sectional view of a conventional structure of a semiconductor device after forming a spacer wall on a side wall of the multilayer structure; Fig. 1D shows a self-aligned technology and a contact window A cross-sectional view of a conventional structure of a semiconductor device after a conductive pattern is formed; FIG. 2A shows a cross-sectional view of a semiconductor device before a conductive structure (tungsten silicide layer) is etched according to a preferred embodiment of the present invention; Figure 2B shows a cross-sectional view of the structure of a semiconductor device after forming a polycrystalline silicon silicide metal layer and patterning it; Figure 2C shows a comparative example according to the present invention. In a preferred embodiment, after the second oxide layer that can be selected is further etched * and the polycrystalline silicon layer is also etched to form a multi-layered structure, the structure of the semiconductor device -------- ^^ ----- ----- Order -------- I {Please read the notes on the back before filling in this page) This paper size is applicable to China National Standard (CNS) A4 (210 * 297) (%) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 23 1 U 9 A7 _B7_____ V. Description of the invention () Sectional view; Figure 2D shows a preferred embodiment of the present invention, forming a partition wall in the multi-layer Structure sidewalls, and Cross-sectional view of a semiconductor device after a polycrystalline silicided metal protrusion is generated on the sidewall of the multi-layer structure; FIG. 2E shows a cross-sectional view of the structure after a dielectric layer is formed on the semiconductor device according to a preferred embodiment of the present invention. Figure 3A shows a cross-sectional view of a semiconductor device before a conductive structure (tungsten silicide layer) is etched according to another preferred embodiment of the present invention; Figure 3B shows another comparison according to the present invention In a preferred embodiment, after forming a polycrystalline silicon silicide layer and patterning it (pa 11 er η), a sectional view of the structure of the semiconductor element is shown; FIG. 3C shows another preferred embodiment according to the present invention. Should the formed second oxide layer be further etched, and the polycrystalline silicon layer is also etched to form a multi-layer structure, a sectional view of the structure of the semiconductor device; FIG. 3D shows another preferred embodiment according to the present invention After forming a gap wall on the side wall of the multilayer structure, and after the subsequent oxidation process generates a polycrystalline silicided metal protrusion on the side wall of the multilayer structure, the junction of the semiconductor device Sectional view; and Figure III Ε shows the structure of the cross-sectional view according to another preferred embodiment of the present invention, after forming a dielectric layer on the semiconductor element. 5-5 Detailed description of the invention ----- Γ .---..-- II · 1 I 1 --- Order--------- / Λ, (Please read the precautions on the back before (Fill in this page) The size of this paper is applicable to the national standard (CNS) A4 specification (210x 297 mm) 4 231 ^ 9 ^ A7 ___ B7_ V. Description of the invention () In the manufacture of semiconductor components, such as word lines, bit lines When it is a transistor, self-align technology is often used, and usually a lightly doped drain (LDD) oxidation process is often used. However, the above process must be able to prevent the oxide layer from seeping out. The rough sidewalls caused by the polycrystalline silicon silicide of the sidewall can then avoid the insulation degradation between the polycrystalline silicon silicide gate and the contact. In a preferred embodiment of the present invention, taking a method of manufacturing a semiconductor element, such as a word line, a bit line, or a transistor as an example, a transistor manufacturing method is used as a conventional technique in the description of the present invention. Explanation: When the substrate 40 is provided for the above process, the gate oxide layer 41, the polycrystalline silicon layer 4 2, and the tungsten silicide layer 4 3 are successively deposited on the substrate 40. Then, if necessary, choose whether or not to deposit a layer of Tetra-Ethy] -Ortho * Silicate: TEOS oxide layer 44. In other words, this is a deposition step of forming a TE 0 S oxide layer 44. It can be omitted in another embodiment. The TEOS oxide layer 44 may be an oxide layer 44 deposited using Tetra-Ethy Ortho-Silicate: TEOS as a raw material and chemical vapor deposition (Chemica 丨 Vapor Deposition: CVD) method. In the embodiment, a subsequent description is made by depositing a te0s I oxide layer 44 on the tungsten silicide layer 43. A nitride nitride layer 45 is formed on the TE0S oxide layer 44 and is then generated by spin coating, exposure, and development. The photoresist layer 46 on the silicon nitride layer 45 is used as an etching mask when the silicon nitride layer 45 and the TEOS oxide layer 44 are anisotropically etched. Applicable to China National Standards (CNS) A4g UI0X297 mm} f Please read the note § on the back before writing this page) 'Zhuang Yi
S1T 經濟部智慧財產局員工消費合作社印f 423109 A7 B7 五、發明説明（） 然後參考圖二B，剝除光阻層46，並接著以非等向 性蝕刻步驟，利用氮化矽層4 5為遮罩，以钱刻砂化辑層 4 3 ’然後以一選擇性濕蝕刻步驟，α橫向的蝕刻妙化笔 層4 3 ’使得矽化鎢層4 3退縮一段距離。上述選擇性麵 刻步驟使用A Ρ Μ溶液以蝕刻矽化鎢層4 3，並且對氣化石夕 層45具有不小於100的蝕刻選擇比。上述的αΡμ溶液 包含ΝΗ3/Η202/Η20的混合溶液之比值介於1:1.5及 1:5:20。 在TEOS氧化層44形成於矽化鎢層43之上以後， TEOS氧化層 44接著被以 HF/BOE(Buffer〇x丨deEtching) 溶液而蝕刻。參考圖二C，下一個步驟是利用氮化夺層 45為遮罩，以蝕刻複晶矽層42，藉以形成複層結構，其 包含有經蝕刻的複晶矽層42、經蝕刻的矽化鎢層43、經 蝕刻的TEOS氧化矽層44以及經蝕刻的氬化矽層45。 參考圊二D ’形成間隙壁（space「）5〇於上述形成的 複層結構的側壁上’而上述間隙壁可以是由氮化矽所構 成。在後績製程中，雖然用氧化步驟以處理半導體元件 中上述的複層结構後’在經過蝕刻的矽化鎢層4 3之側壁 表面上，仍然可能產生複晶矽化金屬突出層5 2，但是在 間隙壁5 0表面和複晶矽化金屬突出層5 2之間的距離， 經濟部智慧財產局員工消費合作社印製 I I - — - —h. I - I !-1- I _ I - m (請先閲讀背面之注意事項再填寫本頁} 因為本發明利用的選擇性濕蝕刻步驟（橫向蝕刻），仍然是 小於習知技術者。當使用自對準（self_align)技術以製造 上述的半導體元件時，形成介電層55於半導體元件上， 並接著定義其圖樣，以裸露出一部份的閘極氣化層41以 本紙張尺度遑用中國國家橾孪（CNS ) A4規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 423109 A7 B7 I II 圓—m _ " - i m _ _______—瞧 1 五、發明説明（） 及部分的間隙壁5 0，其餘的步驟可以被用來施於上述的 半導體元件上’例如閉極’以製造其他種類的元件’例 如電晶艘。 在本發明的另一較佳實施例中所提出的用以製造 半導體元件的方法，在本發明的說明書接著的部分中加 以說明。在製程申提供底材60，而閘極氧化層61、複晶 矽層6 2、矽化鎢層6 3陸續被沉積在底材6 0上。然後視 需要而選擇要或是不要沉積一層正矽酸乙酯（丁etra_ Ethy卜Ortho-Silicate : TEOS)氧化層 64 於矽化鎢層 63 上。換句話說，此形成TE0S氧化層64的沉積步驟，在 另一實施例中是可以省略的。此處以沉積上一層TE0S 氧化層64於矽化鎢層63上為例，進行後續說明。氮化 矽層65形成於TE0S氧化層64上，然後接著旋t、曝 光並顯影而產生在氮化矽層65上的光阻層66，在非等 向性（anisotropically)地触刻氮化石夕層65和TE0S氧化 矽層64時，作為蝕刻罩幕（mask)之用。然後參考圖三B， 以一選擇性濕蝕刻步驟’以蝕刻矽化鎢層6 3，使得矽化 鎢層63退縮一段距離，並且在TE0S氧化矽層64下方 的矽化鎢層63中形成底切（undercut)67。上述的選擇性 蝕刻步驟使用APΜ溶液以蝕刻矽化鎢層63，並且對矽化 鎢層63具有不小於100的蝕刻選擇比。上述的ΑΡΜ落 液包含ΝΗ3/Η202/Η20的混合溶液之比值介於1:1:5及 1 :5:2 0 之間。 然後剝除光阻層66，並當TE0S氡化發層64 本紙張尺度遑用中國國家橾準（CNS ) Α4洗格（210X297公釐^ -----.------t.------^------〆， (請先聞讀背面之注意事項再填寫本頁) A7 B7 d23^09 五'發明説明（） 被沉積在矽化鎢層63上時’ TEOS氧化矽層64被接著 以經稀釋的 HF/BOE(Buffer Oxide Etching)溶液作轴 刻。參考圊三C ’接著的步驟是利用氮化矽層6 5作為遮 單，以蝕刻矽化鎢層6 3和複晶矽層6 2，，藉以形成複 廣結構，其包含有經蝕刻的複晶矽層6 2、經蝕刻的矽化 總廢63 '經蝕刻的TEOS氧化矽層64以及經蝕刻的氣 化矽層6 5 °其令值得注意的是經敍刻的矽化鎢6 3之頂 層因為底切67而往後退縮了一段距離’並且TEOS氧化 £夕層64亦往後退縮。 參考圓三D ’形成間隙壁（spacer)70於上述形成的 複層結構的側壁上，而上述間隙壁7 〇可以是由氮化矽所 構成。在後續製程中’雖然用氧化步驟以處理半導體元 件中上述的複層結構後，在經過蝕刻的矽化鎢層6 3之側 壁表面上，仍然可能產生複晶矽化金屬突出層72 ’但是 在間隙壁7 0表面和複晶矽化金屬突出層 7 2之間的距 離，因為本發明利用的選擇性濕蝕刻步驟，仍然是小於 習知技術者。 當使用自對準（self-align)技術以製造上述的半導體 元件時，形成介電層75於半導體元件上，並接著定義其 圖樣，以裸露出一部份的閘極氧化層61以及部分的間隙 壁70，其餘的步驟可以被用來施於上述的半導體元件 上，例如閘極，以製造其他種類的元件，例如電晶體。 因為上述用來製造其他種類的元件之步驟並不是本發明 的重點，所以這些步驟於本發明說明書中不加以贅述， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之汶意事項再填寫本I) * 裝 ----- -- 訂----— II--^ 經濟部智慧財產局員工消費合作社印製 A7 _B7_ 五、發明說明（） 並且未以圖示說明這些步驟。矽化金屬層（本發明的實施 例中為矽化鎢層），以及τ E 0 S氧化矽層（本發明的實施例 中為矽）的退縮，增加了半導體元件的.複晶矽化金屬突出 物至其間隙壁表面之間的距離，所以在本發明中，介於 複晶矽閘極和半導體元件之自對準接觸窗之間的絕緣邊 限（i s ο丨a t i ο n m a r g i π >，則因此而增加。在本發明的說明 書當中，T E 0 S氡化層可以由氧化矽以外的物質來構成。 並且在複層結構（包括退縮的複晶矽化金屬層）側壁上的 間隙壁，在一氧化步驟（快速熱處理製程）之後，仍可以防 止複晶矽化金屬層侧壁上所產生的複晶矽化金屬突出間 隙壁。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍；凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，例如使用不同的蝕刻 劑，只要利用到先行蝕刻閘極結構中的矽化金屬，以增加 半導體元件的絕緣邊限時，即應包含在本發明的精神與範 圍之内，故均應包含在下述之申請專利範圍内。 <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）S1T Intellectual Property Bureau Employees ’Cooperative Cooperative Print of Ministry of Economic Affairs f 423109 A7 B7 V. Description of the Invention () Then refer to Figure 2B, strip off the photoresist layer 46, and then use the anisotropic etching step to use the silicon nitride layer 4 5 As a mask, the layer 4 3 ′ is etched with money and then a selective wet etching step is performed, and the pen layer 4 3 ′ is etched laterally to make the tungsten silicide layer 4 3 retract a distance. The above-mentioned selective engraving step uses an AP solution to etch the tungsten silicide layer 43, and has an etching selection ratio of not less than 100 for the gasified stone layer 45. The ratio of the aforementioned αPμ solution to the mixed solution containing N 包含 3 / Η202 / Η20 is between 1: 1.5 and 1: 5: 20. After the TEOS oxide layer 44 is formed on the tungsten silicide layer 43, the TEOS oxide layer 44 is then etched with a HF / BOE (Buffer) deEtching solution. Referring to FIG. 2C, the next step is to use the nitrided layer 45 as a mask to etch the polycrystalline silicon layer 42 to form a multi-layer structure, which includes the etched polycrystalline silicon layer 42 and the etched tungsten silicide. Layer 43, an etched TEOS silicon oxide layer 44, and an etched silicon argon layer 45. With reference to the second D ', a space 50 is formed on the side wall of the multilayer structure formed above, and the space wall may be made of silicon nitride. In the later production process, although an oxidation step is used to process After the above-mentioned multilayer structure in a semiconductor device, on the sidewall surface of the etched tungsten silicide layer 43, a polycrystalline metal silicide protruding layer 52 may still be generated, but on the surface of the barrier wall 50 and the polycrystalline silicon silicide protruding layer 5 The distance between 2 is printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs II----h. I-I! -1- I _ I-m (Please read the precautions on the back before filling this page} because The selective wet etching step (lateral etching) utilized by the present invention is still smaller than those of conventional techniques. When the self-align technology is used to manufacture the above-mentioned semiconductor device, a dielectric layer 55 is formed on the semiconductor device, and Then define its pattern to expose a part of the gate gasification layer 41 on this paper scale, using the Chinese National Twin (CNS) A4 specification (210X297 mm) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4231 09 A7 B7 I II circle—m _ "-im _ _______— see 1 V. Description of the invention () and part of the gap wall 50 0, the remaining steps can be used to apply to the above-mentioned semiconductor element 'such as closed pole 'To manufacture other kinds of components', such as crystal wafers. The method for manufacturing semiconductor components proposed in another preferred embodiment of the present invention is described in the following part of the description of the present invention. A substrate 60 is provided, and the gate oxide layer 61, the polycrystalline silicon layer 6 2, and the tungsten silicide layer 6 3 are successively deposited on the substrate 60. Then, if necessary, whether or not to deposit a layer of ethyl orthosilicate (Etra_Ethy Bu Ortho-Silicate: TEOS) An oxide layer 64 is formed on the tungsten silicide layer 63. In other words, the step of forming the TEOS oxide layer 64 can be omitted in another embodiment. A layer of TE0S oxide layer 64 on tungsten silicide layer 63 is taken as an example for subsequent description. A silicon nitride layer 65 is formed on TE0S oxide layer 64, and then t, exposure, and development are performed to generate light on silicon nitride layer 65. Resistive layer 66, in anisotropic (anisotro pically) when etching the nitride nitride layer 65 and the TEOS silicon oxide layer 64, it is used as an etching mask. Then referring to FIG. 3B, a selective wet etching step is used to etch the tungsten silicide layer 63. The tungsten silicide layer 63 is retracted a distance, and an undercut 67 is formed in the tungsten silicide layer 63 under the TEOS silicon oxide layer 64. The selective etching step described above uses an APM solution to etch the tungsten silicide layer 63, and silicides the silicon silicide. The tungsten layer 63 has an etching selection ratio of not less than 100. The ratio of the above APM falling solution to the mixed solution of NΗ3 / Η202 / Η20 is between 1: 1.5 and 1: 5: 20. Then peel off the photoresist layer 66 and use it as the TE0S chemical conversion layer 64 paper standard, using the Chinese National Standard (CNS) A4 grid (210X297 mm ^ -----.------ t. ------ ^ ------ 〆, (Please read the precautions on the back before filling this page) A7 B7 d23 ^ 09 Five 'Invention () When deposited on tungsten silicide layer 63' The TEOS silicon oxide layer 64 is then etched with a diluted HF / BOE (Buffer Oxide Etching) solution. Refer to Section III C 'The next step is to use the silicon nitride layer 65 as a mask to etch the tungsten silicide layer 6 3 and the polycrystalline silicon layer 6 2 to form a complex structure, which includes the etched polycrystalline silicon layer 6 2. The etched silicidation waste 63 'etched TEOS silicon oxide layer 64 and the etched gas The siliconized layer 6 5 ° It is worth noting that the top layer of the tungsten silicide 63, which has been engraved, is retracted by a distance because of the undercut 67 ', and the TEOS oxidation layer 64 is also retracted. Refer to circle three D 'A spacer 70 is formed on the side wall of the multilayer structure formed above, and the above-mentioned spacer 70 may be composed of silicon nitride. In the subsequent process, although an oxidation step is used, After processing the above-mentioned multi-layer structure in the semiconductor device, on the sidewall surface of the etched tungsten silicide layer 63, a polycrystalline metal silicide protruding layer 72 'may still be generated, but on the surface of the barrier wall 70 and the polycrystalline silicon silicide protruding. The distance between the layers 72 is still smaller than that of a skilled person because of the selective wet etching step utilized by the present invention. When self-align technology is used to manufacture the above-mentioned semiconductor element, a dielectric layer is formed 75 on the semiconductor element, and then define its pattern to expose a part of the gate oxide layer 61 and a part of the spacer 70. The remaining steps can be applied to the above-mentioned semiconductor element, such as the gate, In order to manufacture other types of components, such as transistors. Because the above steps for manufacturing other types of components are not the focus of the present invention, these steps will not be repeated in the description of the present invention. This paper size applies the Chinese National Standard (CNS ) A4 size (210 X 297 mm) (please read this matter on the back before filling in this I) * Equipment ------Order ----- II-^ Ministry of Economic Affairs Wisdom Printed by the Consumer Bureau of Industry Bureau A7 _B7_ V. Description of the invention () and these steps are not illustrated. The silicided metal layer (the tungsten silicide layer in the embodiment of the present invention), and the τ E 0 S silicon oxide layer (this In the embodiment of the invention, the shrinkage of silicon) increases the distance between the polycrystalline silicon silicide protrusion and the surface of the spacer wall. Therefore, in the present invention, it is between the polycrystalline silicon gate and the semiconductor element. The insulation margin (is ο 丨 ati ο nmargi π > between self-aligned contact windows) is increased accordingly. In the specification of the present invention, the T E 0 S halogenated layer may be made of a substance other than silicon oxide. In addition, the spacers on the sidewalls of the multilayer structure (including the shrinking polycrystalline silicon silicide layer) can still prevent the polycrystalline silicon silicide generated on the sidewalls of the multiple crystal silicide metal layer after an oxidation step (rapid heat treatment process). Protrude the gap. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention, such as using different etchings As long as the agent is used to etch the silicided metal in the gate structure in advance to increase the insulation margin of the semiconductor element, it should be included in the spirit and scope of the present invention, so it should be included in the scope of the patent application described below. < Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)