463315 6361twf.doc/006 A7 ____B7 五、發明說明（/ ) 本發明是有關於一種自行對準接觸窗（Self-Ahgned Contact Window，SAC)的形成方法，且特別是有關於一種在 一埋入式動態隨機記憶體（Embedded Dynamic Rand⑽ Access Memory，Embedded DRAM)的 DRAM 區域中，形成 自fr對準接觸窗的形成方法。 在單純的動態隨機記憶體中，形成自行對準接觸窗的 方法通常包括在整個基底上先形成一內層金屬介電層 (Inter-Poly Dielectric Layer，IPD)，再對此一內層金屬介電 層進行微影蝕刻，以定義出閘極之間的接觸窗，曝露出其 中之源/汲極區。由於在閘極上方通常形成有一頂蓋層，而 在閘極兩側壁上則形成有一間隙壁，因此，蝕刻該內層金 屬介電層爲一自行對準的蝕刻步驟。 一般而言，在半導體元件的電極上，例如是閘極及源/ 汲極，常會形成一層形成自行對準金屬矽化物(Self-Aligned Silicide，Salicide)，以降低其接觸電阻，增加導電性能。然 而在埋入式動態隨機記憶體中，若是在記憶元件區域之源/ 汲極區上形成自行對準金屬矽化物，極易造成接面的洩漏 電流（junction Leakage)，因此，通常僅在邏輯元件區之電 極上形成此一自行對準金屬矽化物，以避免洩漏電流的發 生。 第1圖繪示出一種形成自行對準接觸窗的傳統製造方 法，其屮僅繪示出不欲形成金屬矽化物的DRAM區域，在 一基底100上包括有兩個閘極結構’該閘極結構包括基底 100表面上之閘氧化層102’閘氧化層102上之複晶矽層 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） <請先閲讀背面之注意事項再填寫本頁) 裝 • |> ϋ 經濟部智慧財產局員Η消費合作社印製 經濟部智慧財產局員工消費合作社印製 4633 1 5 6361twf.doc/006 A7 ____B7 五、發明說明（2j HM，複晶砂層104上之氮化砂頂蓋層106，在兩側壁表面 之氧化層108，以及在氧化層108上之間隙壁110。在閘極 結構以及基底的表面上，形成一層自行對準金屬矽化物之 阻障層（Salicide Block)，在此爲氮化矽層，以防止在記憶 元件區中形成自行對準金屬矽化物1】2。然後，在整個基 底100的表面形成了二氧化矽層114,再利用一光阻層116， 以蝕刻該氧化層114，定義出自行對準接觸窗120。 在此一傳統的製造方法中，是採用一次蝕刻步驟，同 ' 時去除氧化層114以及基底100表面的自行對準金屬矽化 物阻障層112。因此，由於蝕刻進行到閘極結構的上端之 時，在氮化矽頂蓋層106以及間隙壁110表面之自行對準 金屬矽化物之阻障層112勢必先行曝露出來，亦即在基底 100表面之自行對準金屬矽化物之阻障層112尙未曝露出 來之間，此處已曝露於蝕刻劑中，因此，極有可能造成對 閘極結構之頂蓋層106及間隙壁110之損壞。爲避免此一 損壞的發生，必需採取相當高的氧化矽對氮化矽之蝕刻 比。 除了要考慮到氧化物對氮化物的蝕刻比之外，當蝕刻 氧化層114之蝕刻劑遇到了氮化矽材料時，不可避免地， 會在其表面產生一高分子層，而影響要對自行對準金屬矽 化物之阻障層的蝕刻。因此，要避免對間隙壁110的損害 又要能將自行對準金屬矽化物之阻障層蝕刻去除，其蝕刻 之裕度(Etching Window)相當有限。 因此本發明提供一種一種在一埋入式動態隨機記憶體 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） --------- 、 I !^-1··--!*^ (請先Η讀背面之注$項再填寫本頁) 4 6 331 5 6361twf.doc/006 B7 五、發明說明（$) 之邏輯元件區域中，形成自行對準接觸窗的形成方法。首 先，提供一半導體基底，在該半導體基底上包括了至少-· 個記億元件區域以及一邏輯元件區域。而在邏輯元件區域 中，至少包括了兩個閘極結構，閘極結構的上方包括有一 頂蓋層，而閘極結構的側壁上包括有一間隙壁。首先，在 整個基底表面，形成一層共形的自行對準金屬矽化物之阻 障層。然後，在自行對準金屬矽化物之阻障層上形成一內 層金屬介電層。利用一已定義之光阻層，曝露出位於閘極 結構之間，源/汲極上方的內層金屬介電層。然後，對內層 金屬介電層進行蝕刻，直到曝露出基底表面，亦即源/汲極 表面之自行對準金屬政化物之阻障層。此時，在其表面上 包括有高分子層。接著，將光阻層蝕刻去除，並同時去除 表面的高分子層，以曝露出源/汲極表面之自行對準金屬砂 化物之阻障層。然後，利用乾式蝕刻去除自行對準金屬矽 化物之阻障層，以曝露出源/汲極，形成自行對準接觸窗。 經濟部智慧財產局員工消費合作社印製 根據以上之方法，由於內層金屬介電層以及自行對準 金屬矽化物之阻障層是在兩個不同的步驟中所蝕刻的，因 此，其蝕刻比可依據所需各自調整，此外，在蝕刻去除光 阻層時’由於高分子層隨之去除，不至影響自行對準金屬 矽化物之阻障層的蝕刻。所以，本發明提供一種自行對準 接觸窗的製造方法，不但蝕刻裕度增加，更不會損害到聞 極之間隙壁，而影響元件的品質。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，F文特舉較佳實施例，並配念所附圖式，作詳細 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印制衣 4 633 1 5 6361twf.doc/006 A7 _B7__ 五、發明說明（+ ) 說明如下： 圖式之簡單說明： 第1圖所繪示爲一種傳統自行對準接觸窗的形成方 法；以及 第2A圖至第2E圖繪示出依據本發明之一實施例中， 形成一自行對準接觸窗的方法。 圖式之標記說明： 100/200 :基底 102/202 :閘氧化層 104/204 :閘極導電層 106/206 :頂蓋層 108/208 :氧化層 110/210 :閘極間隙壁 112/212:自行對準金屬矽化物之阻障層 114/214 :內層金屬介電層 116/216 :光阻層 118/218 :高分子層 120/220 :自行對準接觸窗 222 :自行對準金屬矽化物 實施例 請參照第2A-2E圖，其所繪示的是依照本發明之一實 施例，一種在埋入式動態隨機記憶體之邏輯元件區域中， 形成一自行對準接觸窗，以及在曝露於自行對準接窗中之 源/汲極區上，形成一砍化金屬層的方法。如第1A圖所不， 7 (锖先閲讀背面之注意事項再填寫本頁) ---- ----訂 ----I I I *^|[ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 463315 經濟部智慧財產局員工消費合作社印製 63 61twf. doc/006 ___^§7 五、發明說明（f) 首先，提供一半導體基底200，該基底200至少包括一記 憶元件區域以及一邏輯元件區域。而在邏輯元件區域中， 至少包括兩個閘極結構形成於基底200上。該閘極結構包 括形成於基底200表面之閘氧化層202，在閘氧化層202 上之閘極導電層204，通常爲一厚約1000-2000埃左右的 複晶矽層，閘極導電層204上之頂蓋層206，例如是一厚 約1000-2000埃的氮化矽層，以及在閘極導電層204以及 頂蓋層206側壁上之氧化層208，及在氧化層208上之間 隙壁210。 由於在埋入式動態隨機記憶體中，若是在記憶元件區 域中之源/汲極區上形成自行對準金屬矽化物會造成接面洩 漏電流，因此，在整個基底200的表面上，形成一層自行 對準金屬矽化物之阻障層212，例如是一厚約80·300埃的 氮化矽層。接著，再於自行對準金屬矽化物之阻障層212 上形成一內層金屬介電層214，例如是一氧化層，以覆蓋 住所有的基底200表面，以及基底200上之閘極結構。然 後，形成一已定義之光阻層216，該光阻層216具有至少 一個開口，曝露出邏輯元件區域中，欲形成自行對準接觸 窗的源/汲極區。此時，由於所有的記憶元件區在形成自行 對準接觸窗時，皆被光阻層216以及內層金屬介電層214 所覆蓋，因此，在第2Α圖中並未明顯繪示出記憶元件區 域，或是邏輯元件區域以及記憶元件區域的分界。 請參考第2Β圖，利用該光阻層216爲蝕刻罩幕，對 該內層金屬介電層214進行蝕刻，直到曝露出兩閘極結構 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱) (請先閲讀背面之注意事項再填寫本頁》 ·芙463315 6361twf.doc / 006 A7 ____B7 V. Description of the Invention (/) The present invention relates to a method for forming a Self-Ahgned Contact Window (SAC), and in particular, to a buried-in-place contact window (SAC). A method for forming a self-aligned contact window in a DRAM area of an embedded dynamic random access memory (Embedded DRAM). In pure dynamic random memory, a method of forming a self-aligned contact window usually includes forming an inter-poly dielectric layer (IPD) on the entire substrate, and then interposing the inner metal dielectric layer on the entire substrate. The electrical layer is lithographically etched to define a contact window between the gate electrodes, exposing the source / drain regions therein. Since a cap layer is usually formed above the gate electrode and a gap wall is formed on both side walls of the gate electrode, etching the inner metal dielectric layer is a self-aligned etching step. Generally speaking, on the electrodes of semiconductor devices, such as the gate and source / drain electrodes, a layer of self-aligned silicide (Salicide) is often formed to reduce its contact resistance and increase its conductivity. However, in the embedded dynamic random access memory, if a self-aligned metal silicide is formed on the source / drain region of the memory element region, junction leakage is easily caused. Therefore, it is usually only in the logic This self-aligned metal silicide is formed on the electrode in the element region to avoid leakage current. FIG. 1 illustrates a conventional manufacturing method for forming a self-aligned contact window. It only illustrates a DRAM region where no metal silicide is to be formed. A substrate 100 includes two gate structures. The structure includes a gate oxide layer 102 on the surface of the substrate 100 and a polycrystalline silicon layer on the gate oxide layer 102. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) < Please read the note on the back first Please fill in this page for further information) Equipment • | > Η Member of the Intellectual Property Bureau of the Ministry of Economic Affairs Η Printed by the Consumer Cooperatives Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4633 1 5 6361twf.doc / 006 A7 ____B7 5. Description of the invention The nitrided sand capping layer 106 on the polycrystalline sand layer 104, the oxide layer 108 on the two sidewall surfaces, and the spacer 110 on the oxide layer 108. A self-aligned metal is formed on the surface of the gate structure and the substrate. A silicide block (Salicide Block), which is a silicon nitride layer, to prevent the formation of self-aligned metal silicides in the memory element region. [2] Then, silicon dioxide is formed on the entire surface of the substrate 100 Layer 114, then A photoresist layer 116 is used to etch the oxide layer 114 to define a self-aligned contact window 120. In this traditional manufacturing method, an etching step is used to remove the oxide layer 114 and the surface of the substrate 100 at the same time. Self-align the metal silicide barrier layer 112. Therefore, since the etching proceeds to the upper end of the gate structure, the self-aligned metal silicide barrier layer 112 is on the surface of the silicon nitride cap layer 106 and the spacer 110. It is bound to be exposed first, that is, the barrier layer 112 of self-aligned metal silicide on the surface of the substrate 100 is not exposed, and has been exposed to the etchant here. Therefore, it is very likely that the gate structure will be damaged. Damage to the cap layer 106 and the spacer 110. To avoid this damage, it is necessary to adopt a relatively high etching ratio of silicon oxide to silicon nitride. In addition to considering the oxide to nitride etching ratio, when When the etchant for etching the oxide layer 114 encounters a silicon nitride material, a polymer layer is inevitably generated on the surface, which affects the etching of the barrier layer that is self-aligned to the metal silicide. Therefore, In order to avoid damage to the spacer 110, it is necessary to be able to etch and remove the self-aligned metal silicide barrier layer, and its etching margin (Etching Window) is quite limited. Therefore, the present invention provides an embedded dynamic random Memory 5 This paper size is in accordance with China National Standard (CNS) A4 (210 * 297 mm) ---------, I! ^-1 ·-!! * ^ (Please read the back first (Note the item in $, then fill in this page) 4 6 331 5 6361twf.doc / 006 B7 V. Method of forming self-aligned contact windows in the logic element area of the invention description ($). First, a semiconductor substrate is provided, and the semiconductor substrate includes at least −100 million memory element regions and a logic element region. In the logic element area, at least two gate structures are included, a cap layer is included above the gate structure, and a gap wall is included on the side wall of the gate structure. First, a conformal self-aligned metal silicide barrier is formed on the entire substrate surface. Then, an inner metal dielectric layer is formed on the self-aligned metal silicide barrier layer. A defined photoresist layer is used to expose the inner metal dielectric layer between the gate structures and above the source / drain. Then, the inner metal dielectric layer is etched until the substrate surface is exposed, that is, the barrier layer on the source / drain surface that is self-aligned with the metallization. In this case, a polymer layer is included on the surface. Next, the photoresist layer is etched away and the polymer layer on the surface is removed at the same time to expose the self-aligned metal sand barrier layer on the source / drain surface. Then, the self-aligned metal silicide barrier layer is removed by dry etching to expose the source / drain electrodes and form a self-aligned contact window. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs According to the above method, since the inner metal dielectric layer and the self-aligned metal silicide barrier layer are etched in two different steps, the etch ratio is It can be adjusted individually according to the needs. In addition, when the photoresist layer is removed by etching, the polymer layer is removed accordingly, which will not affect the etching of the self-aligned metal silicide barrier layer. Therefore, the present invention provides a method for manufacturing a self-aligned contact window, which not only increases the etching margin, but also does not damage the gap between the electrodes and affects the quality of the device. In order to make the above and other objects, features, and advantages of the present invention more obvious and easier to understand, F text presents a preferred embodiment and reads the attached drawings for details. 6 The paper dimensions are applicable to Chinese National Standards (CNS). A4 specifications (210 X 297 mm) Clothing printed by employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 633 1 5 6361twf.doc / 006 A7 _B7__ V. Description of the invention (+) The description is as follows: Brief description of the diagram: Figure 1 A conventional method for forming a self-aligned contact window is shown; and FIGS. 2A to 2E illustrate a method for forming a self-aligned contact window according to an embodiment of the present invention. Description of the symbols of the drawings: 100/200: substrate 102/202: gate oxide layer 104/204: gate conductive layer 106/206: cap layer 108/208: oxide layer 110/210: gate gap 112/212 : Self-aligned barrier layer of metal silicide 114/214: Inner metal dielectric layer 116/216: Photoresist layer 118/218: Polymer layer 120/220: Self-aligned contact window 222: Self-aligned metal For a silicide embodiment, please refer to FIGS. 2A-2E, which shows an embodiment of the present invention, a self-aligned contact window is formed in a logic element region of an embedded dynamic random access memory, and A method of forming a metallized layer on a source / drain region exposed in a self-aligned junction window. As shown in Figure 1A, 7 (锖 Please read the notes on the back before filling this page) ---- ---- Order ---- III * ^ | [This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 463315 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 63 61twf. Doc / 006 ___ ^ §7 V. Description of the Invention (f) First, a semiconductor substrate 200 is provided. The substrate 200 includes at least one A memory element area and a logic element area. In the logic element region, at least two gate structures are formed on the substrate 200. The gate structure includes a gate oxide layer 202 formed on the surface of the substrate 200, and a gate conductive layer 204 on the gate oxide layer 202. Generally, the gate oxide layer is a polycrystalline silicon layer having a thickness of about 1000-2000 angstroms, and the gate conductive layer 204 The upper cap layer 206 is, for example, a silicon nitride layer having a thickness of about 1000-2000 Angstroms, and an oxide layer 208 on the sidewalls of the gate conductive layer 204 and the cap layer 206, and a spacer on the oxide layer 208. 210. In the embedded dynamic random access memory, if the self-aligned metal silicide is formed on the source / drain region in the memory element region, the junction leakage current will be caused. Therefore, a layer is formed on the entire surface of the substrate 200 The self-aligned metal silicide barrier layer 212 is, for example, a silicon nitride layer with a thickness of about 80.300 angstroms. Next, an inner metal dielectric layer 214, such as an oxide layer, is formed on the self-aligned metal silicide barrier layer 212 to cover all the surface of the substrate 200 and the gate structure on the substrate 200. Then, a defined photoresist layer 216 is formed. The photoresist layer 216 has at least one opening exposed in the area of the logic element, and the source / drain region of the self-aligned contact window is to be formed. At this time, since all memory element regions are covered by the photoresist layer 216 and the inner metal dielectric layer 214 when forming a self-aligned contact window, the memory element is not clearly shown in FIG. 2A Area, or the boundary between logic device area and memory device area. Please refer to FIG. 2B. Using the photoresist layer 216 as an etching mask, the inner metal dielectric layer 214 is etched until the two gate structures are exposed. 8 This paper is in accordance with China National Standard (CNS) A4 specifications ( 210 X 297 public love) (Please read the notes on the back before filling in this page.
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----訂i Bf El I 經濟部智慧財產局員工消費合作社印製 6 33 1 5 一 6 1 twf * <i〇c/ 0 0 6 A7 ---_B7 五、發明說明（厶） 之間’基底200表面，亦源/汲極區表面之自行對準金屬砂 化物之阻障層212爲Lh。在此一蝕刻步驟中，由於閘極結 構&間隙壁210以及自行對準金屬矽化物之阻障層212之 材料皆爲氮化矽，爲防止對間隙壁21〇產生任何損害，採 用了 —個氧化矽對氮化矽相當高的触刻比。再者，由於內 層金屬介電層爲氧化矽，而蝕刻氧化矽之蝕刻劑在碰到氮 化；砂材料時，亦即在曝露出頂蓋層206、間隙壁210以及 自行對準金屬矽化物之阻障層212,會產生一層薄的高分 ί層218，阻擋了進一步蝕刻自行對準金屬矽化物之阻障 層 212。 接著，如第2C圖所示，在對自行對準金屬矽化物之 阻障層212進行蝕刻之前，將光阻層216先行蝕刻去除， 以曝露出內層金屬介電層214。而在蝕刻去除光阻層216 的同時’亦可將產生於氮化矽層(包括間隙壁2i0以及自行 對準金屬矽化物之阻障層212)上之高分子層2i8予以去 除’以將源/汲極之基底200表面上的自行對準金屬矽化物 之阻障層212曝露出來。 請參照第2D圖，以內層金屬介電層214爲一蝕刻罩 幕層，對曝露之自行對準金屬矽化物之阻障層212進行蝕 亥！I，例如是乾式蝕刻，以將源/汲極區之基底表面曝露出來， 而被內層金屬介電層216所覆蓋的部分基底200(包括部分 的邏輯元件區域以及記憶元件區域表面，則仍然被自行對 準金屬矽化物之阻障層212所覆蓋。 然後，參考第2E圖，在曝露的源/汲極基底200表面 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------裝--------訂· I ------‘ (請先閲讀背面之注意事項再填寫本頁) 4 633 15 6361twf.doc/006 A7 _B7__ 五、發明說明（j ) 上形成另一自行對準砂化金屬層222。在形成自行對準金 屬矽化層222之前，依據實施所需，內層金屬介電層214 可能被進一步定義或蝕刻，以形成元件所需之金屬內連 線，而在蝕刻該內層金屬介電層214之後，因爲基底200 的表面仍然覆蓋有該自行對準金屬矽化物之阻障層212, 因此，不會在其他部分形成自行對準金屬矽化物，因此， 可以保持界面的完整性，避免接面洩漏電流的產生。接著， 可在自行對準接觸窗220中塡入導導層，以形成位元線。 雖然本發明已以較佳實施例掲露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 — III---111— I I ! i I — t 1 — ! — ·@ {請先W讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）---- Order i Bf El I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 33 1 5 1 6 1 twf * < i〇c / 0 0 6 A7 ---_ B7 V. Description of Invention (厶) The barrier layer 212 on the surface of the substrate 200 and the surface of the source / drain region is self-aligned with metal sand. The barrier layer 212 is Lh. In this etching step, since the material of the gate structure & the spacer 210 and the barrier layer 212 which is self-aligned to the metal silicide are silicon nitride, in order to prevent any damage to the spacer 21,- The ratio of silicon oxide to silicon nitride is quite high. In addition, since the inner metal dielectric layer is silicon oxide, the etchant for etching silicon oxide encounters nitridation; when sanding the material, the cap layer 206, the spacer 210 and the self-aligned metal silicide are exposed. The physical barrier layer 212 generates a thin high-resolution layer 218, which prevents further etching of the barrier layer 212 that is self-aligned with the metal silicide. Next, as shown in FIG. 2C, before etching the self-aligned metal silicide barrier layer 212, the photoresist layer 216 is etched and removed to expose the inner metal dielectric layer 214. While removing the photoresist layer 216 by etching, the polymer layer 2i8 generated on the silicon nitride layer (including the spacer 2i0 and the self-aligned metal silicide barrier layer 212) can also be removed to remove the source The self-aligned metal silicide barrier layer 212 on the surface of the / drain substrate 200 is exposed. Please refer to FIG. 2D. With the inner metal dielectric layer 214 as an etching mask layer, the exposed self-aligned metal silicide barrier layer 212 is etched! I, for example, is dry etching to expose the substrate surface of the source / drain region, and part of the substrate 200 (including part of the surface of the logic element region and the memory element region) covered by the inner metal dielectric layer 216 is still Covered by self-aligned metal silicide barrier layer 212. Then, referring to Figure 2E, on the surface of the exposed source / drain substrate 200 9 This paper is sized to the Chinese National Standard (CNS) A4 (210 X 297 mm) (Li) ------------ install -------- Order · I ------ '(Please read the precautions on the back before filling this page) 4 633 15 6361twf .doc / 006 A7 _B7__ 5. Description of the Invention (j) Another self-aligned sanding metal layer 222 is formed. Before forming the self-aligned metal silicide layer 222, depending on the implementation requirements, the inner metal dielectric layer 214 may be Is further defined or etched to form the metal interconnects required for the device, and after the inner metal dielectric layer 214 is etched, the surface of the substrate 200 is still covered with the self-aligned metal silicide barrier layer 212 Therefore, self-aligned metal silicide is not formed in other parts, so, In order to maintain the integrity of the interface and avoid the occurrence of leakage current at the interface. Next, a conductive layer can be inserted into the self-aligned contact window 220 to form a bit line. Although the present invention has been disclosed above in a preferred embodiment However, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be regarded as the scope of patent application attached to it. The definitions shall prevail. — III --- 111— II! I I — t 1 —! — · @ {Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)