經濟部中央橾準局貝工消费合作社印*. 318267 at B7 五、發明説明（/) 發明背景 發明領域 本發明係關於一種獨特的動態隨機存取記憶體(DRAM)元件結構 及其製法，更仔細地說，係關於^種DRAM的垂直鰭型電容器結構及 其製法。 相關申請案 申請案號八五一一五〇四四號，名爲「四眉鰭型電容器結構的製 造方法」的專利申請案與本案一起提出申請，其中包含了與本申請案 相關的資料。這件申請案的內容可作爲本案的參考。 習知技藝 一個DRAM記憶體一般都包含一個電晶體和一個電容器。二進位 的資料(例如，0或1)即透過電荷的形式儲存在電容器中。電容器無法 將電荷儲存得很好，如果沒有定期(比方毎2毫秒)加以更新，電荷就 會流失。但是，電容器可以很快速地儲存和擷取資料(以電荷的形 式)。 圖1中，說明了一個典型的DRAM細胞元100。圖1的DRAM細胞 元100包含一個金屬氣化物半導體場效電晶體(MOSFET)102和一個電 容器104。有一條字元線連至MOSFET 102的閘極G，位元線連至 MOSFET 102的源極S，電容器104則連至MOSFET 102的汲極D。 DRAM細胞元100的狀態是由電容器是否儲存有電荷來決定的。 DRAM細胞元是由字元線所定址(觸動)的。當DRAM細胞元已經被觸 動時，就可以讀取裏面的資料，或將資料寫入細胞元。當讀取DRAM 細胞元100時，位元線可以決定源楹S處是否具有一個電壓，而顳示 出電容器104內是否具有電荷。如果要將資料寫入DRAM細胞元時， 也是利用位元線將電荷加於電容器104上，或將電荷從電容器104上 本纸張尺度適用中國困家揉準（CNS》A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) --s 經濟部中央樣準局WC工消费合作杜印裝 318267 A7 A7 B7 五、發明説明（；？） 去除。 隨著DRAM技術的精進，一個DRAM細胞元的晶片面積愈來愈 小。這樣一來，毎單位面積就可以製造更多的DRAM細胞元，使同樣 面積的記憶截陣列可以儲存更多的資料。但是，晶片面稍縮小以後， 傳統T型的電容器或填實的節點罨容器都變得太小，以致電容値都不 足。要製造一個具有足夠電容値的電容器，可以將電荷儲存一段足夠 的時間，是愈來愈困難了。 要提高DRAM細胞元電容器的電容値，有兩個方法。一個方法是 降低電容器有效介電眉的厚度；另一個方法是增加電容器的表面面 積。DRAM細胞元通常會在兩眉漉摻雜的複晶矽和/或矽電楹之間， 夾入介電材料，相信未來超薄介霉材料的品質與儲存能力將會大大地 影響DRAM細胞元的性能。但是，使用超薄的介電材料，固然可以提 高電容値，但也會嚴重地影響到元件的保持時間(即兩次更新之間的 時間）。這是因爲當膜層薄於50埃時，直接載子穿隧的效應會使漏電 流變得很大。因此，若要設計更小的DRAM細胞元，最好是增加 DRAM的表面面積，使電容値得以提高到足使電荷儲存一段足夠的時 間。在設計DRAM細胞元時，一方面最好使細胞元整體的大小愈小愈 好，另一方面電容器的表面面稍則是愈大愈好，道兩個互相衝突的設 計特性，使得設計這樣的DRAM細胞元仍是一項挑戰，有待克服。 本發明的一個目的是提出一種DRAM，因爲提高了電容器的表面 面積，所以具有更高的電容値。 本發明的另一個目的是提出一種DRAM，具有垂直鳍型的電容器 結構。 發明的簡要說明 爲達成本發明的道些目的，本發明提出了一種獨特的DRAM，具 本紙ft尺度適用中國國家梂準（CNS ) Α4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 衣· ,ΤΓ 經濟部中央揉準局負工消费合作社印製 318267 at B7 五、發明説明（·> ) 有平行鱈型的電容器結構，並且提出製造這種DRAM的有效方法。 本發明DRAM細胞元的第一實施例開始時，先預備一面具有第一 導電型的矽基板。基板上定義了場氧化物(FOX)，以便隔開各DRAM 細胞元。基板上也製作了汲極和源極。在汲極和源極之間的基板表面 上，並有閘楹區。閘極區包含了一眉閘楹氧化物、接雜成與第一導電 型相反之第二導電型的第一複晶矽眉(Poly-Ι)、矽化鎢(WSi)眉和諸如 Si02的氣化眉或SiN眉。在閘楹區的側壁上覆蓋了氧化物或TEOS(四 乙基砂酸鹽)的空間子。在閘極區上則是一眉TEOS作成的絕緣眉。具 有第二導電型的第二複晶矽眉(Poly-2)與源極接觸，並形成位元線。 在位元線上則覆蓋WSi、氣化眉或薄薄的TEOS和Si3N4之類的SiyN# 膜層。位元線的側壁也由TEOS空間子所覆蓋。另有小小的TEOS區接 觸部份的汲極與源極區。 具有平行鳍型結構的電容器會與汲極接觸。這個電容器包含了摻 雜成第二導電型的第三複晶矽届(Poly-3)、諸如氮化膜/氣化膜(NO) 或氣化膜/氮化膜/氣化膜(ΟΝΟ)等類薄薄的介電屑和摻雜成第二導 電型的第四複晶矽雇(Poly-4)。 本發明DRAM細胞元的第一實施例，係由以下的步驟製作的： 1. 在基板內定義出FOX區，以隔開相鄰的細胞元。 2. 在毎一個細胞元內，以第一複晶矽靥(Poly-Ι)製作一個閘極。 3. 在閘極的側壁上製作閘極空間子，並且利用閘極和閘極空間子 作爲光罩，在基板露出來的區域內製作一個導電區，形成 DRAM的源楹和汲極區。 4. 用TEOS覆蓋住細胞元，加上光罩後進行蝕刻，露出源極。 5. 用第二複晶矽眉(Poly-2)製作位元線，與露出來的源極區接 觸。在位元線上覆蓋一眉厚厚的氣化眉，將用來製作平行的鳍 本纸張尺度適用中國國家揉準（CNS ) A4规格（210X297公釐) (請先閲讀背面之注意事項再填寫本頁) tPrinted by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs *. 318267 at B7 5. Description of the invention (/) BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a unique dynamic random access memory (DRAM) device structure and its manufacturing method, more In detail, it is about the vertical fin capacitor structure of the DRAM and its manufacturing method. Related Application Case No. 851115044, a patent application called "Manufacturing Method of Four-brow Fin-type Capacitor Structure" was filed together with this case, and it contained information related to this case. The content of this application can be used as a reference for this case. Known Techniques A DRAM memory generally contains a transistor and a capacitor. Binary data (for example, 0 or 1) is stored in the capacitor in the form of charge. The capacitor cannot store the charge very well, and if it is not renewed regularly (for example, 2 milliseconds), the charge will be lost. However, capacitors can store and retrieve data very quickly (in the form of charge). In Figure 1, a typical DRAM cell 100 is illustrated. The DRAM cell 100 of FIG. 1 includes a metal vapor semiconductor field effect transistor (MOSFET) 102 and a capacitor 104. A word line is connected to the gate G of the MOSFET 102, a bit line is connected to the source S of the MOSFET 102, and a capacitor 104 is connected to the drain D of the MOSFET 102. The state of the DRAM cell 100 is determined by whether the capacitor stores charge. The DRAM cell is addressed (triggered) by the word line. When the DRAM cell has been touched, you can read the data inside or write the data into the cell. When reading the DRAM cell 100, the bit line can determine whether there is a voltage at the source S, and the time indicates whether there is a charge in the capacitor 104. If you want to write data into the DRAM cell, you also use the bit line to add charge to the capacitor 104, or charge the capacitor 104 from the capacitor 104. This paper standard is suitable for China ’s poor home (CNS) A4 specification (210X297 mm ) (Please read the precautions on the back before filling in this page) --s Central Printing Bureau of the Ministry of Economic Affairs WC Industry Consumer Cooperation Du Printing 318267 A7 A7 B7 V. Invention description (;?) Removed. With the advancement of DRAM technology The chip area of a DRAM cell is getting smaller and smaller. In this way, more DRAM cells can be manufactured per unit area, so that the memory area of the same area can store more data. However, the chip surface is slightly reduced In the future, traditional T-type capacitors or filled node containers have become too small, so that the capacitance value is not enough. To manufacture a capacitor with a sufficient capacitance value, it is more and more difficult to store the charge for a sufficient period of time There are two ways to increase the capacitance value of the DRAM cell capacitor. One method is to reduce the thickness of the effective dielectric eyebrow of the capacitor; the other method is to increase the surface of the capacitor The DRAM cell is usually sandwiched between the double-crystal doped polycrystalline silicon and / or silicon pedestal, and dielectric materials are sandwiched between them. The performance of the cell. However, the use of ultra-thin dielectric materials can certainly improve the capacitance value, but it will also seriously affect the retention time of the device (that is, the time between two updates). This is because when the film layer is thin At 50 angstroms, the direct carrier tunneling effect will cause a large leakage current. Therefore, if you want to design a smaller DRAM cell, it is best to increase the surface area of the DRAM to increase the capacitance value to a sufficient level. The charge is stored for a sufficient period of time. When designing the DRAM cell, on the one hand, it is best to make the overall size of the cell as small as possible, on the other hand, the surface of the capacitor is slightly larger, the better, the two conflict with each other. The design characteristics make designing such a DRAM cell still a challenge that needs to be overcome. An object of the present invention is to propose a DRAM that has a higher capacitance value because it increases the surface area of the capacitor. Another purpose is to propose a DRAM with a vertical fin-type capacitor structure. Brief description of the invention In order to achieve some of the purposes of the invention, the present invention proposes a unique DRAM with the ft scale of this paper suitable for China National Standards (CNS) ) Α4 specification (210X297mm) (please read the precautions on the back before filling in this page) Yi ·, ΤΓ Printed by the Ministry of Economic Affairs, Central Bureau of Accreditation and Consumer Cooperatives 318267 at B7 5. Description of the invention (· >) Yes A parallel cod type capacitor structure, and an effective method for manufacturing such a DRAM is proposed. At the beginning of the first embodiment of the DRAM cell of the present invention, a silicon substrate having the first conductivity type is prepared first. The field oxide ( FOX), in order to separate each DRAM cell. The drain and source are also made on the substrate. On the surface of the substrate between the drain and the source, there is a gate area. The gate region contains an eyebrow gate oxide, a first polycrystalline silicon eyebrow (Poly-Ι), a tungsten silicide (WSi) eyebrow, and a gas such as Si02, conjugated into a second conductivity type opposite to the first conductivity type Brow or SiN eyebrow. The side walls of the gate area are covered with spaces of oxide or TEOS (tetraethyl silicate). On the gate area is an insulating eyebrow made of TEOS. The second polycrystalline silicon eyebrow (Poly-2) having the second conductivity type is in contact with the source and forms a bit line. On the bit line, it is covered with SiSiN # films such as WSi, vaporized eyebrows, or thin TEOS and Si3N4. The side walls of the bit line are also covered by TEOS spaces. Another small TEOS area contacts the drain and source areas. Capacitors with parallel fin structures will be in contact with the drain. This capacitor contains a third polycrystalline silicon (Poly-3) doped into the second conductivity type, such as a nitride film / vaporized film (NO) or a vaporized film / nitride film / vaporized film (ΟΝΟ) Such thin dielectric chips and the fourth polysilicon doped into the second conductivity type (Poly-4). The first embodiment of the DRAM cell of the present invention is made by the following steps: 1. A FOX area is defined in the substrate to separate adjacent cells. 2. In each cell, make a gate with the first polycrystalline silicon (Poly-Ι). 3. Create gate spacers on the sidewalls of the gate, and use the gate and gate spacers as photomasks to create a conductive region in the exposed area of the substrate to form the source and drain regions of the DRAM. 4. Cover the cell with TEOS, add a photomask and etch to expose the source. 5. Use the second polycrystalline silicon eyebrow (Poly-2) to make the bit line and contact the exposed source region. Cover the bit line with a thick vaporized eyebrow, which will be used to make parallel fin paper. The paper size is suitable for China National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling in This page) t
經濟部中央棣準局貞工消费合作社印製 A7 B7 五、發明説明（4) 型電容器。將露出來的TEOS蝕刻去除，而在位元線的側壁上 形成了位元線的空間子。 6. 在整個細胞元上沉稍第三複晶矽眉(Poly-3)-包括露出的汲極 區和厚厚的氣化眉-然後加以蝕刻，形成了與汲極接觸的第一 電容器電極。 7. 用氧化眉覆蓋整個細胞元。蝕去這眉氧化届的一部份，露出 /Printed by the Ministry of Economic Affairs, Central Bureau of Precision Industry, Zhengong Consumer Cooperative A7 B7 V. Description of the invention (4) Type capacitors. The exposed TEOS is etched away, and a space for the bit line is formed on the side wall of the bit line. 6. Sink the third polycrystalline silicon eyebrow (Poly-3) on the entire cell-including the exposed drain region and the thick vaporized eyebrow-and then etch it to form the first capacitor electrode in contact with the drain . 7. Cover the entire cell with an oxidized eyebrow. Eroding a part of this eyebrow oxidation session, revealing /
Poly-3眉的頂面部份。然後蝕去P〇ly-3眉露出的部份。道樣會 將P〇ly-3眉分隔成獨立的電容器電楹。 8. 去除厚厚的氧化眉。在電楹上沉積介電眉，並在介電眉上沉稹 另一眉複晶矽(P〇ly-4)，形成第二電容器電楹。 本發明DRAM細胞元的第二實施例開始時，先預備一面具有第一 導電型的矽基板。基板上定義了場氣化物(FOX)，以便隔開各DRAM 細胞元。基板上也製作了汲極和源極。在汲極和源極之間的基板表面 上，並有閘極區。閘極區包含了一眉閘極氣化物、接雜成與第一導電 型相反之第二導電型的第一複晶矽眉(Poly-Ι)、矽化鎢(WSi)層、氧化 眉和一眉SiO^SiN。在閘極區的側壁上覆蓋了SiO^SiN的空間子。 在閘極區上則是一屑TEOS或BPSG(棚磷矽酸鹽)作成的絕緣眉。具有 第二導電型的Poly-2眉與源極、汲極區接觸。Poly-2眉形成位元線， 並與源極接觸。在位元線上則覆蓋WSi、熱氧化眉或薄薄的TEOS和 Si3N4之類的SiyNx等膜眉。位元線的側壁也由SiyN^間子所覆蓋。 具有平行篇型結構的電容器會與接觸汲極的P〇ly-2眉接觸。這個 電容器包含了摻雜成第二導電型的P〇ly-3眉、諸如NO或ΟΝΟ等類薄 薄的介霣眉和摻雜成第二導電型的P0ly-4眉。 本發明DRAM細胞元的第二賁施例，係由以下的步驟製作的： 1.在基板內定義出FOX區，以隔開相鄰的細胞元。 (請先聞讀背面之注意事項再填寫本頁) 裝·The top part of the Poly-3 eyebrow. Then etch away the exposed part of the P〇ly-3 eyebrow. Dao will separate the P〇ly-3 eyebrows into separate capacitors. 8. Remove thick oxide eyebrows. A dielectric eyebrow is deposited on the electrical jaw, and the other eyebrow polycrystalline silicon (Poly-4) is deposited on the dielectric eyebrow to form a second capacitor electrical jaw. At the beginning of the second embodiment of the DRAM cell of the present invention, a silicon substrate having a first conductivity type is first prepared. A field vaporization (FOX) is defined on the substrate to separate the DRAM cells. The drain and source are also made on the substrate. There is a gate area on the surface of the substrate between the drain and the source. The gate area contains a brow gate vapor, a first polycrystalline silicon brow (Poly-Ι), a tungsten silicide (WSi) layer, a brow oxide and a sputtered into a second conductivity type opposite to the first Eyebrow SiO ^ SiN. The sidewalls of the gate region are covered with SiO ^ SiN spacers. On the gate area is an insulating eyebrow made of TEOS or BPSG (shed phophosilicate). The Poly-2 eyebrow with the second conductivity type is in contact with the source and drain regions. The Poly-2 eyebrow forms a bit line and contacts the source. On the bit line is covered with WSi, thermally oxidized eyebrows or thin TEOS and Si3N4 like SiyNx film eyebrows. The side walls of the bit line are also covered by SiyN ions. A capacitor with a parallel profile structure will come into contact with the P〇ly-2 eyebrow that contacts the drain. This capacitor contains a P0ly-3 eyebrow doped into the second conductivity type, a thin meso eyebrow such as NO or ΟΝΟ, and a P0ly-4 eyebrow doped into the second conductivity type. The second embodiment of the DRAM cell of the present invention is made by the following steps: 1. A FOX area is defined in the substrate to separate adjacent cell cells. (Please read the precautions on the back before filling out this page)
-.1T 本紙張尺度適用中國國家梯準（CNS ) A4规格（210X297公釐） 經濟部中央標準局貝工消费合作社印装 A7 ___B7 五、發明説明（/) 2. 在毎一個細胞元內，以第一複晶矽眉(P〇ly-l)製作一個閘極。 3. 在閘極的側壁上製作閘極空間子，並且利用閘極和閘極空間子 作爲光罩，在基板露出來的區域內製作一個導電區，形成 DRAM的源楹和汲楹區。_ 4. 用TEOS覆蓋住細胞元，加上光罩後進行蝕刻，露出源楹和汲 極，只留下鄰近源楹區之閘楹上方的TEOS。 5. 沉積Poly-2眉，與露出的汲楹和源極區接觸。接觸霪出之源楹 區的Poly-2並形成位元線。在位元線上覆蓋一眉厚厚的氧化 眉，將用來製作平行的鳍型霣容器。在位元線的側壁上也形成 位元線的空間子。 6. 在整個細胞元上沉積第三複晶矽眉(Poly-3)-包括汲極區上露 出的Poly_2眉和厚厚的氣化眉-然後加以蝕刻，形成第一電容 器電楹。 7. 用氣化層覆蓋整個細胞元。蝕去道屑氧化層的一部份，露出 P〇ly-3眉的頂面部份。然後蝕去Poly-3層露出的部份。這樣會 將P〇ly-3眉分隔成獨立的電容器電楹。 8. 去除厚厚的氣化眉。在電極上沉積介電眉，並在介電眉上沉積 一眉Poly-4，形成第二電容器電極。 這個方法不需要分別進行沉稹和蝕刻的步驟，也就是說不需要先 露出源楹、形成位元線，然後再露出汲楹、形成電容器。因此，這個 DRAM細胞元的第二種製造方法，製程步驟比第一種方法更少。 附圖的簡要說明 本發明在說明時，係參考了以下的附圖： 圖1是一個DRAM的簡圖； 圖2是本發明DRAM第一實施例的横剖面圖； 本纸fltX度逋用中國國家揉準（CNS ) A4规格（210X297公釐） " (請先鬩讀背面之注意事項再填寫本頁) 裝· 、11 318267 A7 B7 五、發明説明（汐） 圖3是本發明一個賁施例中平行鰭型電容器的容積說明圖； 圖4A至圖4J說明了製造圖2之DRAM的第一個較佳實施例； 圖5是圖4G中DRAM陣列的上視圖；而 圖6A至圈6H則說明了本發明DRAM的第二實施例和一個更理想 的製造方法。 實施例的詳細說明 圔2的横剖面圖說明了本發明具有平行鳍型電容器之DRAM的第 一個較佳實施例。圈2中的兩個DRAM細胞元共用一個源楹。虛線C 所包含的是一個細胞元的結構。在這個實施例中，細胞元200是製作 在P型的矽基板202上。基板202內定義了場氧化物(FOX)區204，以便 隔開各DRAM細胞元。基板內也製作了汲楹和源楹區(D、S)。在汲楹 和源極之間的基板表面上，並有閘極區(G)。閘極區包含了一眉閘極 氧化物206、一屑摻雜成與第一導電型相反之第二導電型的第一複晶 砂眉(My-Ι)、一眉矽化鎢(WSi)眉208、和諸如Si02的氣化眉或SiN層 210。在閘極區的側壁上覆蓋了8沁2或丁£08(四乙基矽酸鹽)的空間子 212。在閘楹區上則是一眉TEOS作成的絕緣眉214。 經濟部中央梂準局*C工消费合作社印«. (請先閱讀背面之注意事項再填寫本頁) 具有N型導電型的第二複晶砂眉(Poly-2)與源極接觸，並形成位元 線。在位元線上則覆蓋WSi216、TE0S之類的氧化薄層218和Si3N4之 類的SiyNx220。位元線露出來的部份則由TE0S空間子222所覆蓋。另 有小小的TE〇S區224接觸部份的汲楹與源極區。具有平行鳍型結構 的電容器230與汲極接觸。這個電容器包含了摻雜成N型導電型的第 三複晶矽眉(Poly-3)、諸如氮化膜/氣化膜(NO)或氧化膜/氮化膜/ 氣化膜(ΟΝΟ)等類薄薄的介電眉232、和摻雜成N型導電型的第四複 晶矽眉(Poly-4)。圖3是平行鳍型罨容器230的容積說明圖。 圖4A至圈4J的橫剖面圜說明了製造圖2之DRAM的第一個較佳的 本紙張尺度逋用中两B家標準（CNS ) A4规格（210X297公釐） 經濟部中央揉準局貝工消费合作杜印«. A7 B7 五、發明説明（) 實施方法。 圖4A中有一面P型的矽基板202，但熟習此技藝的人士都可瞭解!^ 型基板也一樣適用。如果使用N型基板，在道裏所說明的導電型也要 隨之改變成相反的導電型。 在基板202上，先利用熱氣化法，成長一層厚約150至350埃的氧 化墊膜402，然後再利用化學氣相沉積法(CVD)，在氧化墊膜402上沉 積一屑厚約1000至2000埃的氮化矽(SiyNx)膜404 〇 利用微影技術與電漿蝕刻去除部份的氣化墊膜402和氮化膜404 後，就會在選定部位上露出基板來。 圖4B中，露出來的部位上已經長成場氧化物區(FOX)204。成長 FOX時，最好利用熱氧化法，再用濕蝕刻去除氮化矽膜，最後並去除 氣化墊膜。 圖4C中，已在基板上利用熱氣化法成長了厚約50至150埃的閘楹 氣化膜206。然後利用CVD法，在閘極氧化膜上成長一眉厚約500至 1500埃的Poly-Ι眉，最好是複晶矽眉。利用同步氣截接雜源，使P〇ly-1眉摻雜成N型的導電型。接著利用CVD法，在摻雜的Poly-1眉上沉 積一眉厚約500至1500埃的矽化鎢(WSi)208。隨即利用CVD法，在 WSi眉上沉積一眉厚約500至2000埃諸如Si02的氧化屑或SiN層210。 最後利用微影技術將這些膜靥用光罩加以覆蓋後，再以RIE或電漿蝕 刻蝕去，形成DRAM細胞元的閘極區。 圖4D中，在整個細胞元上，已經利用CVD法沉積了一眉厚約 1000至2000埃的第二Si〇2屑或TE0S。非均向性地蝕刻這膜眉後，就 在閘極區的側壁上形成了空間子212。接著就可以利用任何已知的方 式形成汲楹和源楹區。 圈4E中，已經利用CVD法，沉積了一層厚約1000至2000埃的 本纸張尺度逍用中國國家標準（CNS ) A4此楼 ( 210X297公釐) ---1------(¢------、玎------^ (請先閱讀背面之注意事項再填寫本頁} 經濟部中央標準局貝工消费合作社印裝 318267 at B7 五、發明説明（/) TEOS絕緣屑214。接著利用微影技術將這屑膜層遮蔽後，再以RIE或 電漿蝕刻回蝕刻，露出源極區。TEOS有一部份224會留在空間子212 和源極區之間。 圖4F中，在包括露出來的璩楹區的整個細胞元上，已經利用 CVD法沉積了一層厚約500至2000埃的Poly-2層，最好是複晶矽層。 P〇ly-2雇利用同步摻雜氣體源加以摻雜後，具有N型的導電型。Poly-2層與露出來的濂極接觸。在摻雜的P〇ly-2層上，接著利用CVD法沉 積一層厚約500至1500埃的矽化鎢(WSi)層216。在WSi層上，再成長 一層厚約100至500埃的熱氧化層或TEOS薄層218。接下來，在氧化層 218上，再沉積一層厚約1000至2000埃Si3N4—類的SiyNx 220，所用的 方法可以是化學氣相沉積(CVD)法。這屑氧化層(或TEOS)218是爲了 釋放應力，因爲WSi層216與SiyNx 220的熱膨脹係數不一樣，所以必 須避免SiyNx直接與WSi層接觸。然後在SiyNx雇上，再以CVD法沉積 一層厚約3000至6000埃的氧化厚靥410，可以是SiO。接著利用CVD 法，在氧化厚眉410上沉稍一眉厚約500埃的非晶矽或複晶矽412。最 後利用微影技術將這屑膜層遮蔽後，再以R1E或電漿蝕刻回蝕刻，定 義出接觸源極區的位元線。這些膜層將用來製作平行鰭型的電容器。 圖4G中，利用RIE或電漿蝕刻蝕去露出來的TEOS 214後，露出了 汲極區。小小的TEOS層224會留在空間子212與汲極區之間。然後在 整個細胞元上，利用CVD法沉積了一層厚約500至2000埃的第二 TEOS或熱氧化層。以選擇性楹高的氧化物蝕刻技術非均向性地蝕刻 這膜眉後，就在位元線的側壁上形成了空間子222。膜層412可作爲氧 化物的蝕刻障蔽，避免膜層410被蝕去，維持膜層的外型。 圖4H中，已經在整個的細胞元上，利用CVD法沉積了一層厚約 .^^1- In In n^i ---1 1^1 1^1 In m ^1· n In - ------ — - - (請先閲讀背面之注意Ϋ項再填寫本頁) 本纸法尺度通用中國國家樑準（CNS ) A4規格（210X2.97公釐） 經濟部_央揉準局負工消费合作社印«. A7 _B7_ 五、發明説明（f ) 300至1000埃的P&ly_3眉，最好是複晶矽。P〇ly-3眉並利用同步的摻雜 氣體源，摻雜成N型的導電型。這眉Poly-3眉將成爲電容器的一個電 楹。接著在整個的細胞元上，利用CVD或旋佈的沉積法，沉積一眉 厚約1000至10000埃的氣化眉或犧牲眉420，可用的材料有SOG、光 阻、驿乙醯胺或BPSG，填滿Poly_3眉內的凹窪處，並高到圖中虛線 所表示的地方。利用RIE或電漿蝕刻對氧化眉進行平坦化和回蝕刻之 後，就露出圖4H中Poly-3眉的頂面。 圖41中，Poly-3雇露出的部位和膜眉412已經利用RIE或電漿蝕刻 回蝕刻過了。這道蝕刻的步驟使得Poly-3屑隔絕成許多獨立的電容器 電極。填在凹窪處的氧化眉也利用氧化物對複晶矽、或高分子對複晶 矽的選擇性RIE去除了。至於非晶矽眉412和氧化厚屑410則利用氧化 物對複晶矽的選擇性RIE和SiN RIE加以回蝕刻。接著利用微影技 術，再一次將P〇ly-3靥遽蔽後，加以蝕刻。這是爲了隔開Poly-2沿線 上相鄰的電容器節點。在P〇ly-3眉上並沉積一眉HSG，使電極的表面 極不平滑，更增加了表面面積。隨即利用複晶矽對氧化物的選擇性 RIE，對這眉HSG回蝕刻。最後，利用CVD，在Poly-3眉上沉積一眉 厚約40至60埃、諸如ΟΝΟ或NO的介電眉232。 圖4J中，已經在介電眉232上，利用CVD法沉積了一眉厚約1000 至2000埃的Poly-4眉，可以是複晶矽。這眉Poly-4層並利用同步的摻 雜氣體源，摻雜成N型的導電型。接著利用微影技術，將Poly_4雇遮 蔽後，再利用複晶矽對氣化物的選擇性RIE或電漿蝕刻進行回蝕刻。 接下來完成這個細胞元製程所需要的後段製程，是大家熟知的， 在這裏不作詳細的說明。 圈5是圖4G中DRAM細胞元陣列的上視圈。汲楹露在外面，閘楹 空間子212緊鄰在露出來的汲楹旁。Poly-Ι閘楹位在氣化眉210底下， I.h-------裝------訂------ (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度逋用中國國家揉率（CNS ) A4规格（210X297公釐） 經濟部中央揉準局属工消费合作杜印製 A7 _B7_______ 五、發明説明（/(?)-.1T This paper scale is applicable to China National Standards (CNS) A4 specification (210X297 mm) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 ___B7 5. Description of the invention (/) 2. Within each cell, The first polycrystalline silicon eyebrow (Poly-1) is used to make a gate. 3. Create gate spacers on the sidewalls of the gate, and use the gate and gate spacers as photomasks to create a conductive area in the exposed area of the substrate to form the source and drain areas of the DRAM. _ 4. Cover the cell with TEOS, add a photomask, and etch to expose the source and drain, leaving only the TEOS above the gate in the adjacent source. 5. Deposit the Poly-2 eyebrow and make contact with the exposed jiying and source regions. It touches Poly-2 in the source jade area and forms a bit line. Cover the bit line with a thick oxidized eyebrow, which will be used to make parallel fin-shaped dimples. Spaces on the bit line are also formed on the side walls of the bit line. 6. Deposit the third polycrystalline silicon eyebrow (Poly-3) on the entire cell-including the Poly_2 eyebrow exposed on the drain region and the thick vaporized eyebrow-and then etch it to form the first capacitor electrode. 7. Cover the entire cell with a vaporized layer. A portion of the oxide layer of the chip was etched away, exposing the top surface portion of the P〇ly-3 eyebrow. Then etch away the exposed part of the Poly-3 layer. This will separate the P〇ly-3 eyebrows into separate capacitors. 8. Remove thick vaporized eyebrows. A dielectric eyebrow is deposited on the electrode and a eyebrow Poly-4 is deposited on the dielectric eyebrow to form a second capacitor electrode. This method does not require separate steps of sinking and etching, that is, there is no need to first expose the source jade and form the bit line, and then expose the sink and form the capacitor. Therefore, the second manufacturing method of this DRAM cell has fewer process steps than the first method. Brief Description of the Drawings The present invention refers to the following drawings when explaining the present invention: FIG. 1 is a schematic diagram of a DRAM; FIG. 2 is a cross-sectional view of a first embodiment of the DRAM of the present invention; the paper fltX degree is used in China National Standard (CNS) A4 specification (210X297mm) " (please read the precautions on the back and then fill in this page) 装 ·, 11 318267 A7 B7 Fifth, the description of the invention (XI) Figure 3 is a diagram of the invention 4A to 4J illustrate the first preferred embodiment for manufacturing the DRAM of FIG. 2; FIG. 5 is a top view of the DRAM array in FIG. 4G; and FIG. 6A to circle 6H illustrates the second embodiment of the DRAM of the present invention and a more ideal manufacturing method. Detailed Description of Embodiments The cross-sectional view of Fig. 2 illustrates the first preferred embodiment of the DRAM of the present invention having parallel fin capacitors. The two DRAM cells in circle 2 share a source. The dotted line C contains the structure of a cell. In this embodiment, the cell 200 is fabricated on a P-type silicon substrate 202. A field oxide (FOX) region 204 is defined in the substrate 202 to separate DRAM cell elements. Jiying and Yuanying areas (D, S) were also made in the substrate. On the surface of the substrate between the jiying and the source, there is a gate region (G). The gate region includes a brow gate oxide 206, a first polycrystalline sand eyebrow (My-I) doped with a second conductivity type opposite to the first conductivity type, and a tungsten silicide (WSi) eyebrow 208, and a vaporized eyebrow or SiN layer 210 such as SiO2. The side wall of the gate area is covered with a space element 212 of 8 Q 2 or D 08 (tetraethyl silicate). On the gate area is an insulating eyebrow 214 made of TEOS. Printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs * C Industrial and Consumer Cooperative «. (Please read the precautions on the back before filling this page) The second polycrystalline sand eyebrow (Poly-2) with N-type conductivity contacts the source Form a bit line. On the bit line, it is covered with thin oxide layer 218 such as WSi216, TEOS and SiyNx220 such as Si3N4. The exposed part of the bit line is covered by the TEOS space sub-222. There is also a small TEOS region 224 in contact with the sink and source regions. The capacitor 230 having a parallel fin structure is in contact with the drain. This capacitor contains a third polycrystalline silicon eyebrow (Poly-3) doped into an N-type conductivity, such as a nitride film / vaporized film (NO) or an oxide film / nitride film / vaporized film (ΟΝΟ), etc. A thin dielectric eyebrow 232, and a fourth polycrystalline silicon eyebrow (Poly-4) doped with an N-type conductivity. FIG. 3 is an explanatory diagram of the volume of the parallel fin-shaped container 230. Figures 4A to 4J are cross-sectional diagrams illustrating the first preferred paper standard for manufacturing the DRAM of Figure 2 using the two Chinese standards (CNS) A4 specifications (210X297 mm). Industrial and consumer cooperation Du Yin «. A7 B7 V. Description of invention () Implementation method. In FIG. 4A, there is a P-type silicon substrate 202, but anyone skilled in the art can understand! The ^ -type substrate is also applicable. If an N-type substrate is used, the conductivity type described in Dori should also be changed to the opposite conductivity type. On the substrate 202, first use a thermal vaporization method to grow an oxide pad film 402 with a thickness of about 150 to 350 Angstroms, and then use chemical vapor deposition (CVD) to deposit a chip thickness of about 1000 to 5,000 A 2000 angstrom silicon nitride (SiyNx) film 404. After removing part of the vaporized pad film 402 and the nitride film 404 using lithography and plasma etching, the substrate will be exposed at selected locations. In FIG. 4B, a field oxide region (FOX) 204 has grown on the exposed portion. When growing FOX, it is best to use thermal oxidation, wet etching to remove the silicon nitride film, and finally remove the vaporization pad film. In FIG. 4C, a gate vaporization film 206 having a thickness of about 50 to 150 Angstroms has been grown on the substrate by a thermal vaporization method. Then, a CVD method is used to grow a Poly-1 eyebrow with a thickness of about 500 to 1500 Angstroms on the gate oxide film, preferably a polycrystalline silicon eyebrow. The synchronous gas is used to intercept the impurity source, and the P〇ly-1 eyebrow is doped into an N-type conductivity type. Next, a tungsten silicide (WSi) 208 with a thickness of about 500 to 1500 angstroms is deposited on the doped Poly-1 eyebrows by CVD. Immediately using the CVD method, an oxide swarf or SiN layer 210 having a thickness of about 500 to 2000 Angstroms is deposited on the WSi eyebrow. Finally, these photocatalysts are covered with a photomask using lithography technology, and then etched away by RIE or plasma etching to form the gate region of the DRAM cell. In FIG. 4D, on the entire cell, a second SiO2 shavings or TEOS having a thickness of about 1000 to 2000 angstroms has been deposited by CVD. After anisotropically etching the eyebrow, a space 212 is formed on the side wall of the gate region. Then the Jiying and Yuanying regions can be formed using any known method. In circle 4E, a layer of this paper with a thickness of about 1000 to 2000 Angstroms has been deposited using the CVD method. The Chinese National Standard (CNS) A4 this building (210X297mm) --- 1 ------ ( ¢ ------ 、 玎 ------ ^ (Please read the precautions on the back before filling in this page) Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 318267 at B7 V. Description of the invention (/) TEOS insulating chips 214. After masking this chip layer with lithography, it is etched back by RIE or plasma to expose the source region. A part of TEOS 224 will be left between the space sub 212 and the source region In Fig. 4F, a poly-2 layer, preferably a polycrystalline silicon layer, with a thickness of about 500 to 2000 angstroms has been deposited on the entire cell including the exposed yingying area by CVD. P〇ly- 2 After being doped with a synchronous doping gas source, it has an N-type conductivity. The Poly-2 layer is in contact with the exposed pole. On the doped P〇ly-2 layer, a layer is then deposited by CVD A tungsten silicide (WSi) layer 216 with a thickness of about 500 to 1500 angstroms. On the WSi layer, a thermal oxide layer or a thin layer of TEOS 218 with a thickness of about 100 to 500 angstroms is grown. Next, the oxide layer 218 On top, deposit a layer of SiyNx 220 with a thickness of about 1000 to 2000 Angstroms, such as Si3N4-type, which can be a chemical vapor deposition (CVD) method. The chip oxide layer (or TEOS) 218 is used to release stress because the WSi layer 216 The thermal expansion coefficient is different from that of SiyNx 220, so it is necessary to avoid direct contact of SiyNx with the WSi layer. Then, on SiyNx, a layer of thick oxide 410 of about 3000 to 6000 angstroms is deposited by CVD, which may be SiO. Then use CVD Method, the amorphous silicon or polycrystalline silicon 412 with a thickness of about 500 Angstroms is deposited on the thick oxide eyebrow 410. Finally, the lithography technology is used to mask this chip layer, and then etched back by R1E or plasma etching, definition The bit lines contacting the source region. These films will be used to make parallel fin-type capacitors. In Figure 4G, after using RIE or plasma etching to etch the exposed TEOS 214, the drain region is exposed. The TEOS layer 224 will remain between the space 212 and the drain region. Then, a second TEOS or thermal oxide layer with a thickness of about 500 to 2000 Angstroms is deposited on the entire cell by CVD. After the oxide etching technology anisotropically etched this film, Spacer 222 is formed on the side wall of the bit line. Membrane layer 412 can be used as an etch barrier for oxide to prevent membrane layer 410 from being eroded and maintain the appearance of membrane layer. In Figure 4H, the entire cell On the top, a layer of about ^^ 1- In In n ^ i --- 1 1 ^ 1 1 ^ 1 In m ^ 1 · n In------- —--(please first Read the notes on the back Ϋ and fill out this page) The standard of this paper is the general Chinese National Liang Zhun (CNS) A4 specification (210X2.97mm). The Ministry of Economic Affairs _ Central Ruzhun Bureau Printed by Cooperative Consumers «. A7 _B7_ V. Description of the invention (f) 300 & 1000 Angstrom P & ly_3 eyebrows, preferably polycrystalline silicon. P〇ly-3 eyebrows are doped into an N-type conductivity using a simultaneous doping gas source. This eyebrow Poly-3 eyebrow will become a capacitor of the capacitor. Then, on the entire cell, a vaporized eyebrow or sacrificial eyebrow 420 with a thickness of about 1000 to 10,000 Angstroms is deposited by CVD or spin cloth deposition. Available materials are SOG, photoresist, acetamide, or BPSG , Fill the depression in the Poly_3 eyebrow, and rise to the place indicated by the dotted line in the figure. After RIE or plasma etching is used to planarize and etch back the oxidized eyebrow, the top surface of the Poly-3 eyebrow in Fig. 4H is exposed. In Figure 41, the exposed part of Poly-3 and the eyebrow 412 have been etched back by RIE or plasma etching. This etching step isolates Poly-3 chips into many independent capacitor electrodes. The oxide eyebrows filled in the depressions were also removed by the selective RIE of oxides on polycrystalline silicon or polymers on polycrystalline silicon. As for the amorphous silicon eyebrow 412 and the thick oxide 410, the selective RIE and SiN RIE of the polycrystalline silicon are etched back with oxide. Then, using photolithography technology, Poly-3 was masked again and then etched. This is to isolate adjacent capacitor nodes along the Poly-2 line. An eyebrow HSG is deposited on the P〇ly-3 eyebrow, making the surface of the electrode extremely uneven and increasing the surface area. Immediately using the selective RIE of polycrystalline silicon to oxide, the HSG was etched back. Finally, using CVD, a dielectric eyebrow 232 of about 40 to 60 Angstroms thick, such as ΟΝΟ or NO, is deposited on the Poly-3 eyebrow. In FIG. 4J, a Poly-4 eyebrow with an eyebrow thickness of about 1000 to 2000 Angstroms has been deposited on the dielectric eyebrow 232 by CVD, which may be polycrystalline silicon. The Poly-4 layer of this eyebrow is doped into an N-type conductivity type by using a synchronous doping gas source. Next, using the lithography technology, the Poly-4 is masked, and then the polycrystalline silicon is used to etch back the selective RIE or plasma etching of the vaporized gas. The subsequent process required to complete this cell process is well known and will not be described in detail here. Circle 5 is the upper view circle of the DRAM cell array in FIG. 4G. Jiying is exposed outside, and Zhaying space 212 is next to the exposed Jiying. The Poly-Ι gate is located under the vaporized eyebrow 210, Ih ------- installed ------ ordered ------ (please read the precautions on the back before filling this page) This paper Zhang Jixing used the China National Rubbing Rate (CNS) A4 specification (210X297mm). The A7 _B7_______ is printed by the industrial and consumer cooperation of the Central Rubbing and Accreditation Bureau of the Ministry of Economic Affairs. 5. Description of the invention (/ (?))
Poly-2位元線則延伸在各個汲極之間，並與源極接觸，但在圖5中無 法看見源極。位元線空間子222—路緊鄰位元線，位元線上則覆蓋著 氧化厚層410。 圖6A至圖6H說明的本發明的第二個較佳實施例600，並說明了製 造的方法。請注意，爲了使圖面的說明更爲清晰，圖6A至圖6H中省 略了一些膜層。舉例來說，閘極氧化層就沒有在附圖中表現出來。 從圖6H可以看到第二個實施例中的DRAM細胞元600，所用的矽 基板(未畫出)具有第一導電型。基板內定義了場氧化物(FOX)區，以 便隔開各DRAM細胞元。基板內也製作了汲極和源極區(D、S)。在汲 極和源極之間的基板表面上，並有閘極區(G)。閘極區包含了一層閘 極氧化物(未畫出）、一層摻雜成與第一導電型相反之第二導電型的 Poly-Ι層、一層砂化鎮(WSi)雇602、一層氧化眉604、和一眉Si02或 SiN層606。在閘極區的側壁上覆蓋了3102或3丨1^的空間子608。在閘極 區上則是一層TE0S或BPSG(硼磷矽酸鹽)作成的絕緣層610。具有第 二導電型的P〇ly-2眉與源極和汲楹接觸。這層Poly-2層形成位元線， 並與源極區接觸。在位元線上則覆蓋WSi 612、熱氧化層或TEOS薄層 614和Si3N4之類的SiyNx 616。位元線的側壁則由SiyNx空間子620所覆 蓋。 具有平行鳍型結構的電容器與接觸汲極區的P〇ly-2届接觸。這個 電容器包含了摻雜成第二導電型的第三P〇ly-3層、諸如NO或ΟΝΟ等 類薄薄的介電屑624、和摻雜成第二導電型的Poly-4層。 圖6A中，基板上已經照前面的說明製作好FOX區、閘極氧化層 和Poly-Ι層。這層Poly-Ι層最好是複晶矽化物，厚約500至1500埃，是 照前面說明的方式沉積並接雜的。接著利用CVD法，在摻雜的P〇ly-l 層上沉積一眉厚約500至1500埃的矽化鎢(WSi)602。隨即在WSi層上 (請先閎讀背面之注意事項再填寫本頁) :策. 訂 本紙張尺度適用中國國家揉隼（CNS ) A4规格（210X297公釐） 經濟部中央揉準扃貝工消费合作社印製 318267 五、發明説明（//) 成長一層氧化層604。在這層氧化層604上，再沉積一靥厚約100至500 埃的氮化層(SiN)或氧化層(SiO2)606，可以利用的方法有CVD。這層 氧化層604是爲了釋放應力，因爲WSi層與SiyNx的熱膨脹係數不一 樣，所以必須避免SiyNx直接與WSi届接觸。最後利用微影技術將這層 膜層遮蔽後，再以RIE或電漿蝕刻蝕去，形成DRAM細胞元的閘極 區0 圖6B中，在整個細胞元上，已經利用CVD法沉積了一層厚約 1000至2000埃的第二SiyNxSSiO^。非均向性地蝕刻這膜屑後，就 在閘極區的側壁上形成了空間子608。接著就可以利用任何已知的方 式形成汲極和源極區。 圖6C中，已經利用CVD法，在整個細胞元上沉稽了一層厚約 1000至4500埃的TEOS或BPSG(硼磷矽酸鹽)絕緣届610。接著利用微 影技術將這層TEOS或BPSG遮蔽後，再以RIE或電漿蝕刻進行蝕刻。 殘留的TEOS(或BPSG)會留在緊鄰源極的閘極區頂面上。這樣一來就 會暴露出汲極和源極區。 圖6D中，在整個細胞元上，已經利用CVD法沉積了一層厚約500 至2000埃的Poly-2層，最好是複晶矽化物層。Poly-2層與露出來的汲 極和源極接觸。P〇ly-2層最好摻雜成N型導電型，舉例來說，所用的 方法可以是同步摻雜氣體源。在接雜的P〇ly-2靥上，接著利用CVD法 沉積一眉厚約500至1500埃的矽化鎢(WSi)層612。在WSi層頂面上， 再成長一層厚約100至500埃的熱氧化眉或TEOS薄屑614。接下來，在 氧化層614上，再沉積一層厚約1000至2000埃Si3N4—類的SiyNx 616， 所用的方法可以是CVD。然後在SiyNx眉616上，再以CVD法沉積一層 厚^3000至9000埃的氧化厚届618，可以是SiO。接著利用CVD法， 在氧化厚層410上沉積一眉厚約5⑻埃的非晶矽或複晶矽 (請先聞讀背面之注項再填寫本I ) 、11 ^! 本紙張又度遑用中國困家樣準（CNS ) A4洗格（210 X 297公簸） A7 B7 五、發明説明（/j) 412。最後利用微影技術將SiO、SiyNx、TEOS、和WSi等膜屑遮蔽 後，再以RIE或電漿蝕刻加以蝕刻。殘留的膜層會覆蓋在源極上方的 P〇ly-2位元線區域。其餘露出來的Poly-2將蝕去部份，而呈凹下的狀 態，所以在汲極區上方留下部份凹窪的Poly-2。 圖6E中，在整個細胞元上，利用CVD法沉積了一層厚約300至 1000埃的第二SiyNjl。非均向性地蝕刻這膜層後，就在位元線的側 壁上形成了空間子620。 圖6F中，已經在整個的細胞元上，利用CVD法沉積了一層厚約 300至1000埃的Poly-3層。Poly-3層最好摻雜成N型導電型，舉例來 說，可以利用同步摻雜氣體源。需要注意的是，這層Poly-3層會接觸 到Pdy-2層，形成一個接處到汲極區的導電區。接著在整個的細胞元 上，利用CVD或旋佈的沉積法，沉積一眉氧化層622，可用的材料有 S0G、聚乙醯胺、光阻或BPSG，填滿Pdy-3眉內的凹窪處，並高到 圖中虛線所表示的地方。利用RIE或電漿蝕刻對氧化眉進行平坦化和 回蝕刻之後，就露出圖6F中Poly-3眉的頂面。 經濟部中央揉準局負工消費合作社印裝 (請先聞讀背面之注意事項再填寫本頁) 圖6G中，Poly-3層露出的部位已經利用RIE或電漿蝕刻回蝕刻過 了。這道蝕刻的步驟使得P〇ly-3層隔絕成許多獨立的電容器電極。填 在凹窪處的氧化層也利用氧化物對複晶矽、或高分子對複晶矽的選擇 性R1E去除了。至於氧化厚雇618則利用氧化物對SiN和氧化物對複晶 砂的選擇性RIE加以回蝕刻。在P〇ly-3眉上並沉積一層HSG，更增加 了表面面積。隨即利用RIE或電漿蝕刻，對這層HSG回蝕刻。然後， 利用CVD，在Pdy-3眉上沉積一眉厚約40至60埃、諸如0N0或NO的 介電層624。最後，利用微影技術將Poly-3層遮蔽後，再進行蝕刻， 使P〇ly-2沿線上的相鄰電容器可以彼此隔離。 圖6H中，已經在介電眉624上，利用CVD沉積了一眉厚約1000至 本紙張尺度遄用中國國家揉準（〇«)八4规格（210乂297公釐） A7 _ B7 五、發明説明（/)) 2000埃的Poly-4層，最好是複晶矽。這眉P〇ly-4眉最好利用同步的摻 雜氣體源，摻雜成N型導電型。接著利用徼影技術，將P〇ly-4眉遮蔽 後，再利用RIE或電漿蝕刻進行回蝕刻。 接下來完成道個細胞元製程所需要的後段製程，是大家熟知的， 在這裏不作詳細的說明。圖6A至圖6H所說明的這個方法，不需要分 別進行沉積和蝕刻的步驟，也就是先露出源極、形成位元線，然後再 露出汲極、形成電容器(參考圖4E至圖4G)。因此，圖6A至圖6H所說 明DRAM細胞元的製造方法，製程步驟更少。 我們提出了一種利用平行鳍型電容器提高電容値的DRAM。同 時，我們也提出了兩種有效方法，可以用來製造這種帶有鰭狀結構的 DRAM。 以上本發明的實施例只是用來舉例說明本發明，熟習本技藝的人 士仍可以設計出許多不同的實施例，卻仍不離開以下申請專利範圍的 精神與範圍。 ^ -裝 I 訂 II (請先閲讀背面之注意事項再填寫本頁)- 經濟部中央搮準局貝工消费合作社印装 本纸張从適用中1IBI家揉準（CNS )从賴· ( 21GX297公釐）The Poly-2 bit line extends between each drain and contacts the source, but the source cannot be seen in Figure 5. The bit line space 222-way is close to the bit line, and the bit line is covered with a thick oxide layer 410. 6A to 6H illustrate the second preferred embodiment 600 of the present invention and illustrate the method of manufacture. Please note that in order to make the description of the drawing clearer, some film layers are omitted in FIGS. 6A to 6H. For example, the gate oxide layer is not shown in the drawings. From FIG. 6H, it can be seen that the DRAM cell 600 in the second embodiment uses a silicon substrate (not shown) having the first conductivity type. A field oxide (FOX) area is defined in the substrate to separate DRAM cell elements. Drain and source regions (D, S) are also made in the substrate. On the surface of the substrate between the drain and the source, there is a gate region (G). The gate area contains a layer of gate oxide (not shown), a layer of Poly-Ι doped with a second conductivity type opposite to the first conductivity type, a layer of WSI 602, and a layer of oxide eyebrows 604, and one eyebrow Si02 or SiN layer 606. The side wall of the gate region is covered with a space 608 of 3102 or 31 mm. On the gate region is an insulating layer 610 made of TEOS or BPSG (borophosphosilicate). The P〇ly-2 eyebrow with the second conductivity type is in contact with the source and the jiying. This Poly-2 layer forms a bit line and is in contact with the source region. On the bit line, it is covered with WSi 612, thermal oxide layer or TEOS thin layer 614 and SiyNx 616 like Si3N4. The sidewall of the bit line is covered by the SiyNx space 620. The capacitor with the parallel fin structure is in contact with the Poly-2 contacting the drain region. This capacitor includes a third P〇ly-3 layer doped to the second conductivity type, a thin dielectric chip 624 such as NO or ONO, and a Poly-4 layer doped to the second conductivity type. In FIG. 6A, the FOX region, gate oxide layer, and Poly-1 layer have been formed on the substrate according to the previous description. This Poly-1 layer is preferably polycrystalline silicide, about 500 to 1500 Angstroms thick, deposited and contaminated in the manner described above. Next, a tungsten silicide (WSi) 602 with an eyebrow thickness of about 500 to 1500 Angstroms is deposited on the doped Poly-1 layer by CVD. Immediately on the WSi layer (please read the precautions on the back and then fill out this page): Policy. The standard paper size is applicable to the Chinese National Falcon (CNS) A4 specification (210X297 mm). Printed by the cooperative 318267 5. Description of the invention (//) An oxide layer 604 is grown. On this oxide layer 604, a nitride layer (SiN) or oxide layer (SiO2) 606 with a thickness of about 100 to 500 Angstroms is deposited. CVD can be used. This oxide layer 604 is for stress relief. Because the WSi layer and SiyNx have different thermal expansion coefficients, it is necessary to avoid direct contact between SiyNx and WSi. Finally, using lithography technology to mask this film layer, and then etched away by RIE or plasma to form the gate region of the DRAM cell. In Figure 6B, a thick layer of CVD has been deposited on the entire cell About 1000 to 2000 Angstroms of the second SiyNxSSiO ^. After etching the film debris anisotropically, a space 608 is formed on the sidewall of the gate region. The drain and source regions can then be formed using any known method. In FIG. 6C, a layer of TEOS or BPSG (borophosphosilicate) with a thickness of about 1000 to 4500 Angstroms has been deposited on the entire cell by CVD method 610. Then, this layer of TEOS or BPSG is masked by lithography, and then etched by RIE or plasma etching. The remaining TEOS (or BPSG) will remain on the top surface of the gate area immediately adjacent to the source. In this way, the drain and source regions are exposed. In FIG. 6D, a layer of Poly-2 with a thickness of about 500 to 2000 Angstroms, preferably a polycrystalline silicide layer, has been deposited on the entire cell by CVD. The Poly-2 layer is in contact with the exposed drain and source. The P〇ly-2 layer is preferably doped to an N-type conductivity. For example, the method used may be a simultaneous doping gas source. A tungsten silicide (WSi) layer 612 with an eyebrow thickness of about 500 to 1500 Angstroms is then deposited on the conjugated Polly-2 titanium by CVD. On the top surface of the WSi layer, another layer of thermal oxide eyebrows or TEOS flakes 614 with a thickness of about 100 to 500 angstroms is grown. Next, on the oxide layer 614, a layer of SiyNx 616 with a thickness of about 1000 to 2000 Angstroms of Si3N4-type is deposited. The method may be CVD. Then, on the SiyNx eyebrow 616, a layer of oxide with a thickness of 3,000 to 9,000 angstroms is deposited by CVD, which may be SiO. Then use CVD method to deposit an amorphous silicon or polycrystalline silicon with an eyebrow thickness of about 5 ⑻ Angstroms on the thick oxide layer 410 (please read the notes on the back and fill in this I), 11 ^! This paper is used again China's homeless standard (CNS) A4 wash grid (210 X 297 public bumps) A7 B7 V. Description of the invention (/ j) 412. Finally, lithography technology is used to mask the film scraps such as SiO, SiyNx, TEOS, and WSi, and then etched by RIE or plasma etching. The remaining film layer will cover the P〇ly-2 bit line area above the source. The rest of the exposed Poly-2 will be etched away, and it will be in a concave state, so part of the concave Poly-2 is left above the drain region. In FIG. 6E, a second layer of SiyNjl with a thickness of about 300 to 1000 angstroms is deposited on the entire cell by CVD. After etching the film anisotropically, a space 620 is formed on the side wall of the bit line. In Figure 6F, a layer of Poly-3 with a thickness of about 300 to 1000 Angstroms has been deposited on the entire cell by CVD. The Poly-3 layer is preferably doped with an N-type conductivity. For example, a simultaneous doping gas source can be used. It should be noted that this Poly-3 layer will contact the Pdy-2 layer to form a conductive region from the drain region. Then, on the entire cell, a CVD or spin cloth deposition method is used to deposit an eyebrow oxide layer 622. The available materials are SOG, polyacetamide, photoresist, or BPSG to fill the depressions in the Pdy-3 eyebrow To the place indicated by the dotted line in the figure. After the RIE or plasma etching is used to planarize and etch back the oxidized eyebrow, the top surface of the Poly-3 eyebrow in FIG. 6F is exposed. Printed by the Consumer Labor Cooperative of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). In Figure 6G, the exposed part of the Poly-3 layer has been etched back by RIE or plasma etching. This etching step isolates the Poly-3 layer into many independent capacitor electrodes. The oxide layer filled in the depression is also removed by the selective R1E of oxide to polycrystalline silicon, or polymer to polycrystalline silicon. For the thick oxide 618, the selective RIE of oxide to SiN and oxide to polycrystalline sand is etched back. Depositing a layer of HSG on the P〇ly-3 eyebrow further increases the surface area. Then use RIE or plasma etching to etch back this layer of HSG. Then, using CVD, a dielectric layer 624 with a thickness of about 40 to 60 Angstroms, such as ONO or NO, is deposited on the Pdy-3 eyebrow. Finally, after masking the Poly-3 layer using lithography, etching is performed to isolate adjacent capacitors along the line of Poly-2. In Fig. 6H, a dielectric eyebrow 624 has been deposited by CVD with an eyebrow thickness of about 1000 to the paper size. Using the Chinese National Standard (〇 «) 84 specifications (210 to 297 mm) A7 _ B7 V. Description of the invention (/)) Poly-4 layer of 2000 angstroms, preferably polycrystalline silicon. This eyebrow P〇ly-4 eyebrow is preferably doped into an N-type conductivity by using a synchronized doping gas source. Next, using the shadowing technique, the P〇ly-4 eyebrow is masked, and then etched back using RIE or plasma etching. It is well known that the subsequent process required to complete the cell process is completed here, and no detailed description will be given here. The method illustrated in FIGS. 6A to 6H does not require separate deposition and etching steps, that is, firstly exposing the source and forming the bit line, and then exposing the drain and forming the capacitor (refer to FIGS. 4E to 4G). Therefore, FIGS. 6A to 6H illustrate the manufacturing method of the DRAM cell, and there are fewer process steps. We have proposed a DRAM that uses parallel fin capacitors to increase capacitance. At the same time, we have also proposed two effective methods that can be used to manufacture such DRAMs with fin structures. The above embodiments of the present invention are only used to illustrate the present invention. Those skilled in the art can still design many different embodiments without departing from the spirit and scope of the following patent applications. ^-Install I Order II (please read the precautions on the back before filling out this page)-Printed copies of this paper from the Central Bureau of Economic Affairs of the Ministry of Economic Affairs, Beigong Consumer Cooperative from 1IBI Homepage (CNS) from Lai (21GX297 Mm)