A7 B7 44701 9 B657twf.d〇c/〇〇e 五、發明説明（/ ) 本發明是有關於一種半導體元件的製造方法，且特 別是有關於一種減低應力產生之閘極結構的製造方法。 在高積集度的半導體製程中，金屬氧化物半導體電 HBli(metal oxide semiconductor transistor, MOS transistor) 5 簡稱金氧半電晶體，已經被廣泛地採用，取代了在半導體 元件中用以導通電流之傳統雙極性電晶體的地位。通常， 金氧半電晶體包括：在正常情況下被提供輸入訊號之閘極 結構、以及輸出電壓橫越其上產生且輸出電流流過其中之 源/汲極區。 習知閘極結構的製造流程包括在隔離結構所定義之 基底的主動區上形成閘極氧化層，接著在閘極氧化層上形 成閘極堆疊結構，包括多晶矽層、金屬矽化物層、以及氮 化矽層，緊接著，於閘極堆疊結構的側壁形成緩衝氧化層， 且在緩衝氧化層的側壁形成氮化矽間隙壁。第1A圖至第 1E圖舉例說明了習知閘極結構的製造流程，以及當使用不 同的氧化方法增成緩衝氧化層時所產生的一些問題。 請參照第1A圖，提供基底100,伴隨著由基底100 中之隔離結構102所定義之主動區（並未繪出），閘極氧化 層104隨後形成於基底1〇〇上，並接著形成閘極堆疊結構 111。閘極堆疊結構111包括提供電荷導通的摻雜多晶矽 層106、提升傳送速率的金屬矽化物層1〇8、以及用來作 爲保護的氮化矽層110。形成閘極堆疊結構111的方法爲， 於閘極氧化層104上依序沉積摻雜多晶矽層106、金屬矽 化物層108、以及氮化矽層11〇,並隨後圖案化此三層結 3 本紙張尺度適用中國國家CNS > A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁〕 *° 經濟部智慧財是局員工消費合作社印製 4470 1 9 5 6 5 7 twf . d〇c/0 〇 6 A7 B7 五、發明説明（2) 構，於主動區上獲得閘極堆ft結構1丨1。 請參照第1B圖，緩衝氧化層112a是用來覆蓋閘極堆 疊結構111與閘極氧化層104，並減低氮化矽間隙壁(並未 繪出）所引起之應力。且熟知形成緩衝氧化層112a的方法 爲低壓化學氣相沉積法（low-pressure chemical vapor deposition, LPCVD) ° 經濟部智慧財產局員工消費合作社印製 請參照第1C圖，用來形成氮化矽間隙壁114的另一 氮化矽層（並未繪出）於緩衝氧化層112a上形成。氮化政間 隙壁114是使用回蝕製程，移除多餘的氮化矽層所形成， 回蝕製程進一步地移除氮化矽層110上多餘的緩衝氧化層 112a。輕微摻雜汲極（light doped dram, LDD)植入法是用來 摻雜離子進入基底100,藉以形成源/汲極區116,然而， 在接下來的蝕刻步驟形成自動對準接觸窗(self-align contact, SAC)開口時，上述形成的緩衝氧化層112a會產生蝕穿問 題。如第1C圖所示，在形成氧化矽層Π8以作爲隔離作 用之後，大部份的緩衝氧化層112a會隨著部份氧化矽層118 被移除，如此將產生V型刻痕，使曝露出之閘極堆疊結構 111中的導電材料，與後繼製程步驟所沉積的金屬層接觸， 結果’將於製程上產生與電性有關的問題，例如電路短路。 第1C圖所描述的製程步驟與第id圖及第ie圖所描 述的步驟’其不同點只在於形成緩衝氧化層的氧化方法， 因此’相似的製程步驟不再贅述。請參照第1D圖，緩衝 氧化層112b形成於閘極氧化層1〇4、金屬矽化物層1〇8的 側壁、以及多晶矽層106之上。緩衝氧化層U2b是由快 4 本紙張尺度適用中國國家標準（ϋ ) M規格（U0X297公釐） " 447〇1 9A7 B7 44701 9 B657twf.doc / 〇〇e 5. Description of the Invention (/) The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate structure that reduces stress generation. In high-concentration semiconductor manufacturing processes, HBli (metal oxide semiconductor transistor, MOS transistor) 5 is simply referred to as a metal-oxide semiconductor, and has been widely used to replace the current used in semiconductor devices to conduct current. Status of traditional bipolar transistors. Generally, a metal-oxide-semiconductor transistor includes a gate structure that is normally supplied with an input signal, and an output voltage generated across the source / drain region through which the output current flows. The manufacturing process of the conventional gate structure includes forming a gate oxide layer on the active region of the substrate defined by the isolation structure, and then forming a gate stack structure on the gate oxide layer, including a polycrystalline silicon layer, a metal silicide layer, and nitrogen. A silicon layer is formed, and then, a buffer oxide layer is formed on a sidewall of the gate stack structure, and a silicon nitride spacer is formed on a sidewall of the buffer oxide layer. Figures 1A to 1E illustrate the manufacturing process of the conventional gate structure and some problems that occur when different oxidation methods are used to increase the buffer oxide layer. Referring to FIG. 1A, a substrate 100 is provided. With an active area (not shown) defined by the isolation structure 102 in the substrate 100, a gate oxide layer 104 is then formed on the substrate 100, and then a gate is formed. Extremely stacked structure 111. The gate stack structure 111 includes a doped polycrystalline silicon layer 106 that provides charge conduction, a metal silicide layer 108 that enhances the transfer rate, and a silicon nitride layer 110 for protection. The method for forming the gate stack structure 111 is to sequentially deposit a doped polycrystalline silicon layer 106, a metal silicide layer 108, and a silicon nitride layer 110 on the gate oxide layer 104, and then pattern the three-layer junction 3 The paper size applies to China's national CNS > A4 specification (210X297 mm) (please read the precautions on the back before filling out this page) * ° Printed by the Ministry of Economic Affairs's Smart Financial Staff Consumer Cooperatives 4470 1 9 5 6 5 7 twf. d〇c / 0 〇6 A7 B7 V. Description of the invention (2) structure, the gate stack ft structure 1 丨 1 is obtained on the active area. Please refer to FIG. 1B, the buffer oxide layer 112a is used to cover the gate stack structure 111 and gate oxide layer 104, and reduce the stress caused by the silicon nitride spacer (not shown). And the well-known method for forming the buffer oxide layer 112a is low-pressure chemical vapor deposition, LPCVD) ° Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics Please refer to Figure 1C. Another silicon nitride layer (not shown) used to form the silicon nitride spacer 114 is formed on the buffer oxide layer 112a. Nitrogen The chemical partition wall 114 uses an etch-back process The excess silicon nitride layer is formed, and the etch-back process further removes the excess buffer oxide layer 112a on the silicon nitride layer 110. A lightly doped dram (LDD) implantation method is used for doping The impurity ions enter the substrate 100 to form the source / drain region 116. However, when a self-align contact (SAC) opening is formed in the subsequent etching step, the buffer oxide layer 112a formed above will be etched. As shown in Figure 1C, after the silicon oxide layer Π8 is formed as an isolation function, most of the buffer oxide layer 112a will be removed along with part of the silicon oxide layer 118, which will cause a V-shaped nick. So that the exposed conductive material in the gate stack structure 111 is in contact with the metal layer deposited in the subsequent process steps, and as a result, electrical-related problems such as short circuits in the process will be generated. As described in FIG. 1C The process steps are different from the steps described in the id and ie diagrams. 'The only difference lies in the oxidation method of forming the buffer oxide layer. Therefore, similar process steps are not repeated. Please refer to FIG. 1D, the buffer oxide layer 112b is formed on brake The polar oxide layer 104, the side wall of the metal silicide layer 108, and the polycrystalline silicon layer 106. The buffer oxide layer U2b is made from 4 times faster. This paper size applies the Chinese national standard (ϋ) M specification (U0X297 mm) " 447〇1 9
/ Ο Ο 6 五、 Α7 Β7 發明説明（彡） ' 速熱氧化法（rapid thermal oxidation，RTO)所形成，所以形 砂；閛極氧化層1 〇4上的緩衝氧化層Π 2b較形成於金屬 ^匕物層側壁上與多晶砂層106上的緩衝氧化層112b 為 15。、 …、叻’以快速熱氧化法所形成的緩衝氧化層1丨2b 門^形成條件，例如高溫與短期間，這些條件會產生剝蝕 氧化層的應力。除了閘極氧化層剝蝕的問題外，製程 舉右包含快速熱氧化法，亦會導致高的熱預算。第1E圖 .例说明了另一個形成緩衝氧化層112c的方法，其中， 1氧化層112c是在爐管（並未繪出）中氧化出一層薄膜所 ·" °此氧化方法無可避免地會產生例如氧化侵蝕（〇xide =^ac：hmeru)的問題’也就是說，部份緩衝氧化層112c成 《進入多晶矽層106,破壞閘極堆疊結構U1。根據此氧 1 匕法’形成於閘極堆疊結構m側壁的緩衝氧化層112c， 了 >度較厚’導致臨界尺寸（critical dimensj〇n，⑶)的降低， '皮装斗'導體兀件的更新時間（refresh time)。 因此本發明就是在提供一種閘極結構的製造方法， ^方法降低由氮化矽間隙壁所引起的應力產生。 蛵濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 本發明提供一種閘極結構的製造方法。提供一基底， 伴^者形成於基底的隔離結構，其中，隔離結構在基底中 疋·義了—主動區。在基底上形成緩衝氧化層，並形成氮化 ϊ夕層與罩幕氧化層。接著，圖樣化氮化矽層與光罩氧化層 以形成閘極開口，其中閘極開口描繪出形成於閘極開口之 _極堆疊結構的輪廓。由閘極開口曝露出之部份緩衝氧化 層被移除’接著形成閘極氧化層。然後，在閘極氧化層上 本紙張尺度適用中國國家七準（CNS ) A4规格（210X 297公釐） 44701 9 5657twf .doc/〇〇6 A7 B7 五、發明説明（妒） 依序沉積摻雜多晶矽層、金屬矽化物層、以及頂蓋氮化砂 層，作爲閘極堆疊結構。其次，移除光罩層，再進行輕微 摻雜汲極（LDD)植入法以形成源/汲極區。最後，於閘極堆 疊結構的側壁形成氮化矽間隙壁，完成閘極結構的製作。 根據本發明’提出一種閘極結構的製造方法。本發 明之閘極堆疊結構於形成緩衝氧化層之後形成，因此由不 同氧化方法形成緩衝氧化層所引起的問題能被解決。更明 確地’本發明具有下述優點及利益：因爲在閘極堆疊結構 上形成緩衝氧化層之步驟並不須要進行快速熱氧化法，使 元件的植入具有低熱預算。本發明亦免除了側壁氧化步 驟，因爲閘極堆疊結構於緩衝氧化層形成之後形成，所以 不再發生如氧化侵蝕、臨界尺寸縮短、以及更新時間變化 等問題。除此之外，本發明亦解決了於形成自動對準接觸 窗開口的蝕刻步驟時，緩衝氧化侵蝕的問題。 爲讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1A圖至第1E圖繪示習知製造閘極結構程序之剖 面圖，特別是在第1C圖、第1D圖、以及第1E圖中，繪 示由不同氧化方法所形成的緩衝氧化層，以及於每一案例 中所引起的問題； 第2A圖至第2F圖繪示根據本發明之較佳實施例， 閘極結構之製造流程及剖面圖。 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注項再填寫本頁) 丁 -'5 經濟部智慧財產局員工消費合作杜印製 44701 9 )c / 0 0 6 A7 B7 五、發明説明（f) 圖式之標記說明： (請先閱讀背面之注意事項再填寫本頁) 100、200 :基底 102、202 :隔離結構 104、212.:閘極氧化層 106、214 :摻雜多晶矽層 108、216 :金屬砂化物層 110 :氮化矽層 m、219 :閘極堆疊結構 112a、1 12b、204 :緩衝氧化層 114 :氮化矽間隙壁 116、220 :源/汲極區 118 :氧化5夕層 206 :光罩氮化砂層 208 :光罩氧化層 210 :鬧極開口區 218 :頂蓋層 222 :間隙壁 實施例 經濟部智慧財產局員工消費合作社印製 請參照第2A圖至第2F圖，其繪示依照本發明較佳 實施例，一種閘極結構製造流程圖，本發明將據此詳述如 下。 請參照第2A圖，基底200伴隨著隔離結構202，例 如於基底200上形成淺溝渠隔離結構。此隔離結構202於 基底200上定義一主動區（並未繪出），且閘極結構於主動 經濟部智慧財產局員工消費合作社印製 4470 1 9 5657twf . doc/006 A7 __B7 五、發明説明（g) 區上形成。緩衝氧化層204形成於基底200上’其中緩衝 氧化層204的材料包栝氧化矽，且形成緩衝氧化層2〇4的 方法爲化學氣相沉積。一層薄的罩幕氮化矽層2〇6形成於 緩衝氧化層204上’且光罩氧化層208隨後形成於光罩氮 化矽層206上’其中光罩氧化層2〇8厚於光罩氮化矽層 206。 一微影蝕刻製程被進行以使光罩氧化層208與光罩氮 化砂層206圖案化，形成由圖案化的光罩氧化層208與圖 案化的光罩氮化矽層206所描廓出的閘極開口區210，曝 露部份緩衝氧化層204，如2B圖所示。此閘極開口區210 提供一能於後續步驟形成閘極堆疊結構的空間。 請參照第2C圖，緩衝氧化層204曝露於閘極開口區 的部份須被移除，直至位於閘極開口區210的基底200曝 露出來，移除此緩衝氧化層204的方法包括非等向性蝕刻。 接著，閘極氧化層212形成於基底200曝露於閘極開口區 210的部份，形成此閘極氧化層212的材料包括氧化矽， 且此閘極氧化層212是以熱氧化法於氧化爐管（並未繪出) 中形成。 請參照第2D圖，摻雜多晶矽層214形成於閘極氧化 層212之上，形成摻雜多晶矽層214的方法包括數個步驟： 首先，於閘極氧化層212上沉積多晶矽層；其次’以離子 摻雜此多晶矽層，形成摻雜多晶矽層214 :最後，移除位 於閘極開口區210外的摻雜多晶矽層214 °接著’金屬矽 化物層216形成於摻雜多晶砂層214之上’形成金屬矽化/ 〇 Ο 6 V. Α7 Β7 Description of the invention (彡) ′ formed by rapid thermal oxidation (RTO), so the sand is shaped; the buffer oxide layer Π 2b on the electrode oxide layer 104 is more formed on the metal ^ The buffer oxide layer 112b on the sidewall of the object layer and on the polycrystalline sand layer 106 is 15. …,… The formation conditions of the buffer oxide layer 1 丨 2b formed by the rapid thermal oxidation method, such as high temperature and short period of time, these conditions will cause stresses that will ablate the oxide layer. In addition to the problem of gate oxide erosion, the process includes rapid thermal oxidation, which also results in a high thermal budget. Fig. 1E illustrates another method for forming a buffer oxide layer 112c. The oxide layer 112c is oxidized by a thin film in a furnace tube (not shown). This oxidation method is inevitable. A problem such as oxidative attack (0xide = ^ ac: hmeru) will occur, that is, a portion of the buffer oxide layer 112c enters the polycrystalline silicon layer 106 and destroys the gate stack structure U1. According to this oxygen method, the buffer oxide layer 112c formed on the m side wall of the gate stack structure has a > thickness ' leading to a reduction in critical dimensions (critical dimensjon, ⑶), and a 'leather bucket' conductor element Refresh time. Therefore, the present invention is to provide a method for manufacturing a gate structure. The method reduces the stress caused by the silicon nitride spacer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) The present invention provides a method for manufacturing a gate structure. A substrate is provided, with an isolation structure formed on the substrate, wherein the isolation structure is defined in the substrate—the active area. A buffer oxide layer is formed on the substrate, and a nitride layer and a mask oxide layer are formed. Next, the silicon nitride layer and the mask oxide layer are patterned to form a gate opening, wherein the gate opening traces the outline of the _pole stacking structure formed in the gate opening. A portion of the buffer oxide layer exposed through the gate opening is removed 'and a gate oxide layer is formed. Then, the paper scale on the gate oxide layer is applicable to China National Seven Standards (CNS) A4 specification (210X 297 mm) 44701 9 5657twf .doc / 〇〇6 A7 B7 V. Description of the invention (jealous) Sequential deposition of doping The polycrystalline silicon layer, the metal silicide layer, and the cap nitrided sand layer serve as a gate stack structure. Secondly, the mask layer is removed, and a lightly doped drain (LDD) implantation method is performed to form a source / drain region. Finally, a silicon nitride spacer is formed on the sidewall of the gate stack structure to complete the fabrication of the gate structure. According to the present invention ', a method for manufacturing a gate structure is proposed. The gate stack structure of the present invention is formed after the buffer oxide layer is formed, so the problems caused by forming the buffer oxide layer by different oxidation methods can be solved. More specifically, the present invention has the following advantages and benefits: Because the step of forming a buffer oxide layer on the gate stack structure does not require a rapid thermal oxidation method, the implantation of the device has a low thermal budget. The invention also eliminates the side wall oxidation step, because the gate stack structure is formed after the buffer oxide layer is formed, so problems such as oxidative erosion, shortening of the critical size, and change of the update time, etc. no longer occur. In addition, the present invention also solves the problem of buffering oxidative erosion during the etching step of automatically aligning the contact window opening. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below, and in conjunction with the accompanying drawings, the detailed description is as follows: Brief description of the drawings: FIG. 1A to FIG. Figure 1E shows a cross-sectional view of a conventional gate structure manufacturing process, especially in Figures 1C, 1D, and 1E, showing buffer oxide layers formed by different oxidation methods, and in each case The problems caused in Figs. 2A to 2F show the manufacturing process and sectional views of the gate structure according to the preferred embodiment of the present invention. 6 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the note on the back before filling out this page) Ding-'5 Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Du Printing 44701 9) c / 0 0 6 A7 B7 V. Description of the invention (f) Symbols of drawings: (Please read the precautions on the back before filling out this page) 100, 200: Base 102, 202: Isolation structure 104, 212 .: Gate Oxide layers 106, 214: doped polycrystalline silicon layers 108, 216: metal sand layer 110: silicon nitride layer m, 219: gate stack structure 112a, 112b, 204: buffer oxide layer 114: silicon nitride spacer 116 , 220: source / drain region 118: oxide layer 206: mask nitrided sand layer 208: mask oxide layer 210: anode opening area 218: top cover layer 222: partition wall example Intellectual Property Bureau staff of the Ministry of Economic Affairs Please refer to FIG. 2A to FIG. 2F for the printing of the consumer cooperative, which shows a manufacturing flowchart of a gate structure according to a preferred embodiment of the present invention. The present invention will be described in detail as follows. Referring to FIG. 2A, the substrate 200 is accompanied by an isolation structure 202. For example, a shallow trench isolation structure is formed on the substrate 200. This isolation structure 202 defines an active area (not shown) on the substrate 200, and the gate structure is printed at the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Active Economy 4470 1 9 5657twf. Doc / 006 A7 __B7 V. Description of the invention ( g) Area formation. The buffer oxide layer 204 is formed on the substrate 200. The material of the buffer oxide layer 204 includes silicon oxide, and the method of forming the buffer oxide layer 204 is chemical vapor deposition. A thin mask silicon nitride layer 206 is formed on the buffer oxide layer 204 'and a mask oxide layer 208 is then formed on the mask silicon nitride layer 206', where the mask oxide layer 208 is thicker than the mask Silicon nitride layer 206. A lithographic etching process is performed to pattern the mask oxide layer 208 and the mask nitrided sand layer 206 to form the outline of the patterned mask oxide layer 208 and the patterned mask silicon nitride layer 206. The gate opening region 210 exposes a portion of the buffer oxide layer 204, as shown in FIG. 2B. The gate opening region 210 provides a space capable of forming a gate stack structure in a subsequent step. Referring to FIG. 2C, the portion of the buffer oxide layer 204 exposed in the gate opening area must be removed until the substrate 200 located in the gate opening area 210 is exposed. The method of removing the buffer oxide layer 204 includes anisotropic性 etching. Next, a gate oxide layer 212 is formed on a portion of the substrate 200 exposed to the gate opening region 210. The material forming the gate oxide layer 212 includes silicon oxide, and the gate oxide layer 212 is thermally oxidized in an oxidation furnace. Formed in a tube (not shown). Referring to FIG. 2D, the doped polycrystalline silicon layer 214 is formed on the gate oxide layer 212. The method for forming the doped polycrystalline silicon layer 214 includes several steps: first, a polycrystalline silicon layer is deposited on the gate oxide layer 212; This polycrystalline silicon layer is ion-doped to form a doped polycrystalline silicon layer 214: Finally, the doped polycrystalline silicon layer 214 outside the gate opening region 210 is removed and then a 'metal silicide layer 216 is formed on the doped polycrystalline sand layer 214' Metal silicide
S 本紙張尺度適用中關家轉（CNS > 21t)x297^ ) ----------...------訂------铁 v (請先閱讀背面之注意事項再填寫本頁) 44701 9 5657twf.doc/006 A7 _ B7 五、發明説明（) 物層216的方法包括下列歩驟：首先’沉積一金屬層於摻 雜多晶矽層214之上；其次，進行熱製程，使金屬層與摻 雜多晶矽層214產生化學反應，形成金屬矽化物層216 ; 最後，移除位於閘極開口區210外的金屬砂化物層216。 此外，金屬矽化物層216亦可由金屬層取代，此金屬層通 常由金屬選擇性沉積法形成，且形成此金屬層的材料包括 鎢與欽。移除摻雜多晶砂層2丨4與金屬砂化物層216的方 法包括回蝕步驟。此摻雜多晶矽層214與金屬矽化物層216 形成閘極結構的導電成份。 請參照第2E圖’頂蓋層218形成於金屬矽化物層216 之上，其中形成此頂蓋層218的材料包括氮化矽，且形成 此頂蓋層218的方法爲：形成氮化矽層覆蓋住金屬矽化物 層216與光罩氧化層208，再以回餓步驟移除位於閘極開 口區210外的氮化矽層。在此須注意，化學機械硏磨法 (chemical mechanical polishing, CMP)亦可以用來移除氮化 矽層’而得到具有較平坦表面的頂蓋層218。然後，光罩 氧化層208被移除，直至光罩氮化矽層206曝露出來爲止， 此時，頂蓋層218、金屬矽化物層216、以及摻雜多晶矽 層214亦曝露出來。最後，頂蓋層218、金屬矽化物層216、 摻雜多晶矽層214、以及閘極氧化層212共同形成閘極堆 疊結構219，如第2E圖所示，突出於基底200之上。 請參照第2F圖，先進行輕微摻雜汲極(LDD)植入法， 於基底200中形成源/汲極區220，再於閘極堆疊結構219 之側壁形成間隙壁222,其中間隙壁222的材料包括氮化 9 本紙张尺度逋用中國a家梂牟（CNS ) Α4规格（210 X 297公釐） (請先閣讀背面之注意事項再填寫本頁) > 、π 經濟部智慧財產局員工消費合作社印製 4470 彳 9 5657twf.d< :/006 A7 B7 五、發明説明（2 ) (請先閱讀背面之注意事項再填寫本頁) 矽，且形成間隙壁222的方法包括：首先，於光罩氮化矽 層206上形成氮化矽層，覆蓋住閘極堆疊結構219 ;隨後， 進行回蝕步驟，移除部份氮化矽層與部份緩衝氧化層204， 形成間隙壁222。如此，即完成閘極結構的製造流程，結 果如第2F圖所示。 綜上所述，可以得知，本發明之製造流程不同於習 知金氧半電晶體之製程，緩衝氧化層先於閘極結構形成。 根據本發明，閘極堆疊結構於緩衝氧化層形成之後形成， 因此，可以解決以不同氧化方法形成緩衝氧化層所產生的 問題。更明確地，因爲於閘極堆疊結構上形成緩衝氧化層 時，不須要進行快速熱氧化法，本發明於元件植入時具有 低熱預算的優點與利益。因爲閘極堆疊結構形成於緩衝氧 化層形成之後，本發明亦避免於側壁的氧化，例如氧化侵 蝕、臨界尺寸縮短、更新時間變化等問題不再發生。除此 之外，本發明亦解決了於形成自動對準接觸窗開口的飩刻 步驟時，緩衝氧化層侵蝕的問題。 經濟部智慧財產局員工消費合作社印製 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作各種之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 I 0 本纸張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）S This paper size is applicable to Zhongguanjiazhuan (CNS > 21t) x297 ^) ----------...------ Order ------ Iron v (Please read first Note on the back, please fill in this page again) 44701 9 5657twf.doc / 006 A7 _ B7 V. Description of the invention () The method of the object layer 216 includes the following steps: First, a metal layer is deposited on the doped polycrystalline silicon layer 214; Secondly, a thermal process is performed to cause a chemical reaction between the metal layer and the doped polycrystalline silicon layer 214 to form a metal silicide layer 216. Finally, the metal sand layer 216 outside the gate opening region 210 is removed. In addition, the metal silicide layer 216 may also be replaced by a metal layer. The metal layer is usually formed by a selective metal deposition method, and the materials forming the metal layer include tungsten and cyan. The method of removing the doped polycrystalline sand layer 2 and the metal sand layer 216 includes an etch-back step. The doped polycrystalline silicon layer 214 and the metal silicide layer 216 form a conductive component of the gate structure. Referring to FIG. 2E, the top cap layer 218 is formed on the metal silicide layer 216. The material forming the top cap layer 218 includes silicon nitride, and the method of forming the top cap layer 218 is: forming a silicon nitride layer The metal silicide layer 216 and the mask oxide layer 208 are covered, and then the silicon nitride layer located outside the gate opening region 210 is removed in a starving step. It should be noted here that chemical mechanical polishing (CMP) can also be used to remove the silicon nitride layer 'to obtain a cap layer 218 having a flatter surface. Then, the mask oxide layer 208 is removed until the mask silicon nitride layer 206 is exposed. At this time, the cap layer 218, the metal silicide layer 216, and the doped polycrystalline silicon layer 214 are also exposed. Finally, the cap layer 218, the metal silicide layer 216, the doped polycrystalline silicon layer 214, and the gate oxide layer 212 together form a gate stack structure 219, as shown in FIG. 2E, protruding above the substrate 200. Referring to FIG. 2F, a lightly doped drain (LDD) implantation method is first performed to form a source / drain region 220 in the substrate 200, and then a gap wall 222 is formed on a side wall of the gate stack structure 219, wherein the gap wall 222 The materials include 9 sheets of nitrided paper, using China's National Standards (CNS) Α4 size (210 X 297 mm) (please read the precautions on the back before filling out this page) > 、 Intellectual Property of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Bureau 4470 彳 9 5657twf.d <: / 006 A7 B7 V. Description of the Invention (2) (Please read the precautions on the back before filling this page) Silicon, and the method of forming the spacer 222 includes: First A silicon nitride layer is formed on the mask silicon nitride layer 206 to cover the gate stack structure 219; then, an etch-back step is performed to remove a part of the silicon nitride layer and a part of the buffer oxide layer 204 to form a gap wall 222. In this way, the manufacturing process of the gate structure is completed, and the result is shown in FIG. 2F. In summary, it can be known that the manufacturing process of the present invention is different from the conventional metal-oxygen semi-transistor process, and the buffer oxide layer is formed before the gate structure. According to the present invention, the gate stack structure is formed after the buffer oxide layer is formed. Therefore, the problems caused by forming the buffer oxide layer by different oxidation methods can be solved. More specifically, because the buffer oxide layer is formed on the gate stack structure, a rapid thermal oxidation method is not required, and the invention has the advantages and benefits of a low thermal budget when the device is implanted. Because the gate stack structure is formed after the formation of the buffer oxide layer, the present invention also avoids the oxidation of the sidewall, such as the problem of oxidative erosion, shortening of critical dimensions, and change of update time. In addition, the present invention also solves the problem of buffer oxide erosion during the engraving step of automatically aligning the contact window openings. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Various modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the attached patent application. I 0 This paper size applies to China National Standard (CNS) A4 (210X297 mm)