A7 B7 4 5 7 5 6 9 6563twf. doc/006 五、發明說明（/ ) 本發明是關於製造閘極之方法，且特別是有關於一種 製造金屬氧化半導體（Metal Oxide Semiconductor，MOS)元 件雙層（dual-layer)閘極之方法。 一般常利用複晶矽當作金屬氧化半導體元件之閘極導 體。以微影技術選擇性的移去複晶矽層，使圖案化閘極導 體覆蓋P-型(p-type)或n-型(n-type) MOS元件上之閘氧化層 和通道區域。複晶矽閘極導體當作導電元件時，其可在通 道位置快速且容易的偏移。因此希望複晶矽閘極導體有較 低之電阻率。而複晶矽電阻率比其他金屬內連線材料，例 如是耐火金屬或金屬矽化物，還要差。一般複晶矽不管是 否經過摻雜其電阻率還是很高，會在單一傳送中導致明顯 的延遲。 隨著半導體元件集積度持續增加的特點，將複晶矽應 用在閘極，必須減少其片電阻。降低閘極電阻率的一種方 法是以耐火金屬取代複晶矽。耐火金屬，例如是鋁，其電 阻率和複晶矽及矽相比是非常低的。然而耐火金屬在製程 中暴露，無法禁得起高溫氧化。因此耐火金屬使用在製造 程序之後段，例如不純物趨入以及退火處理等高溫製程之 後。 目前利用多晶矽化金屬結構來降低閘極之電阻率’多 晶矽化金屬結構是在複晶矽導體上方表面形成一層耐火金 屬矽化物。然而當元件之通道長度持續縮減直到次微米範 圍，需要更低之片電阻時，多晶矽化金屬很明顯的無法合 乎要求。因此，純耐火性金屬閘極仍然是較佳之替代物° -I---— — — — --- ί (請先聞讀背面之注意事項角填寫本頁) · ^ 經濟部智慧財產局員工消費合作社印t 本紙張尺度適用中國國家標準（CNS)A4規格（21〇x 297公釐） 45756 9 6563twf»d〇c/006 A7 B7 五、發明說明（之） 傳統製造閘極結構的方法包括一層複晶砍層及一層純耐火 性金屬，已由Wu揭露在美國專利第4,908,332號。 本發明提供一種製造雙層閙極之方法，其中在複晶矽 層上形成一純耐火性金屬層以提供一低電阻鬧極。 根據此發明之較佳實施例，含有不同蝕刻特性之摻雜 複晶矽層及犧牲層相繼在基底上形成’之後定義摻雜複晶 矽層及犧牲層以形成閘極結構。然後沈積一介電層，覆蓋 住閘極結構並且暴露出閘極結構之犧牲層表面。進一步的 以金屬層取代犧牲層而形成閘極。 因此在摻雜複晶矽層上形成一金屬層，以降低閘極之 總電阻率。當犧牲層和摻雜複晶矽層具有不同之蝕刻特 性，可以良好的控制移除犧牲層。如此可良好的控制金屬 層以及摻雜複晶矽層之厚度，形成含有一薄複晶矽層及一 厚金屬層之閘極。 充分瞭解前述之先前技術敘述及下面之較佳實施例， 以進一步提供發明專利範圍之解釋^ 圖式之簡單說明 讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，並進一步提供發明專利範圍之解釋，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 第1A圖至第1D圖爲根據本發明較佳實施例之雙層 閘極製造流程剖面圖。 圖式標號之簡單說明 100基底 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------Ji-裝— (請先閱讀背面之注f項再填寫本頁) 訂. 經濟部智慧財產局員工消費合作社印製 457569 6563twf * doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（多） 102閘氧化層 104摻雜複晶矽層 106犧牲層 110側壁間隙壁 112源/汲極區 114介電層 116 開口 118金屬層 120閘極 122介電層 實施例 雙層閘極之製造流程分別以第1A圖至第1D圖來說 明。 參照第1A圖，提供一基底100例如是矽基底，在其 上形成一閘氧化層102。閘氧化層102例如是以熱氧化 (thermal oxidation)法形成。在閘氧化層102上形成一導電 層例如是摻雜複晶矽層104。製造摻雜複晶矽層104,傳 統上是先以低壓化學氣相沈積(Low Pressure Chemical Vapor Deposition，LPCVD)形成一層未摻雜複晶砂，之後植入 (implanting)不純物至複晶砂層並且以退火（annealing)熱處 理，活化不純物使複晶矽層導通或摻雜。 接著在摻雜複晶矽層104上形成一犧牲層106。犧牲 層106例如是非晶矽層或氮化矽層，其和下方之摻雜複晶 矽104有不同之蝕刻特性。而犧牲層106之厚度較摻雜複 5 1 n 9— In f t] n ter I (請先閱讀背面之注意事項再填寫本頁) ' - 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） A7 B7A7 B7 4 5 7 5 6 9 6563twf. Doc / 006 V. Description of the Invention (/) The present invention relates to a method for manufacturing a gate electrode, and in particular to a method for manufacturing a double layer of a Metal Oxide Semiconductor (MOS) device (Dual-layer) Gate method. Generally, polycrystalline silicon is often used as the gate conductor of a metal oxide semiconductor device. The lithography technology is used to selectively remove the polycrystalline silicon layer so that the patterned gate conductor covers the gate oxide layer and the channel region on the p-type or n-type MOS device. When a polycrystalline silicon gate conductor is used as a conductive element, it can be quickly and easily shifted in the channel position. It is therefore desirable that the polysilicon gate conductor has a lower resistivity. The resistivity of polycrystalline silicon is worse than that of other metal interconnect materials, such as refractory metals or metal silicides. In general, whether polysilicon is doped or not, its resistivity is still high, which can cause significant delay in a single transmission. With the continuous increase of the degree of integration of semiconductor elements, the application of polycrystalline silicon to the gate must reduce its sheet resistance. One way to reduce the gate resistivity is to replace the polycrystalline silicon with a refractory metal. Refractory metals, such as aluminum, have very low resistivity compared to polycrystalline silicon and silicon. However, refractory metals are exposed during the process and cannot withstand high temperature oxidation. Therefore, refractory metal is used in the later stages of the manufacturing process, such as after the impure impurities enter and after the high temperature process such as annealing treatment. Polycrystalline silicided metal structures are currently used to reduce the gate resistivity. Polycrystalline silicided metal structures form a layer of refractory metal silicide on the surface of a polycrystalline silicon conductor. However, when the channel length of the device is continuously reduced to the sub-micron range, and lower sheet resistance is required, the polysilicon metal is obviously unable to meet the requirements. Therefore, pure refractory metal gate is still a better alternative ° -I ----- — — — --- ί (Please read the note on the back to fill out this page first) · ^ Employees of Intellectual Property Bureau, Ministry of Economic Affairs Consumption cooperative print t This paper size is in accordance with Chinese National Standard (CNS) A4 (21〇x 297 mm) 45756 9 6563twf »d〇c / 006 A7 B7 V. Description of the invention (of) The traditional method of manufacturing the gate structure includes A layer of polycrystalline chopped layer and a layer of pure refractory metal have been disclosed by Wu in US Patent No. 4,908,332. The invention provides a method for manufacturing a double-layered dynode, in which a pure refractory metal layer is formed on a polycrystalline silicon layer to provide a low-resistance anode. According to a preferred embodiment of the present invention, a doped polycrystalline silicon layer and a sacrificial layer containing different etching characteristics are sequentially formed on the substrate, and the doped polycrystalline silicon layer and the sacrificial layer are defined to form a gate structure. A dielectric layer is then deposited to cover the gate structure and expose the surface of the sacrificial layer of the gate structure. Further, the gate is formed by replacing the sacrificial layer with a metal layer. Therefore, a metal layer is formed on the doped polycrystalline silicon layer to reduce the total resistivity of the gate. When the sacrificial layer and the doped polycrystalline silicon layer have different etching characteristics, the sacrificial layer can be removed with good control. In this way, the thicknesses of the metal layer and the doped polycrystalline silicon layer can be well controlled to form a gate including a thin polycrystalline silicon layer and a thick metal layer. Fully understand the foregoing description of the prior art and the following preferred embodiments to further provide an explanation of the scope of the invention patent ^ A brief description of the drawings makes the above and other objects, features, and advantages of the present invention more obvious and understandable, and further To provide an explanation of the scope of the invention patent, a preferred embodiment is given below, and it will be described in detail in conjunction with the attached drawings: Figures 1A to 1D are the two-layer gate manufacturing process according to the preferred embodiment of the present invention. Sectional view. Brief description of the drawing numbering 100 substrate 4 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ------------ Ji-pack— (Please read the back Note f. Please fill in this page again.) Order. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 457569 6563twf * doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Doped polycrystalline silicon layer 106 sacrificial layer 110 sidewall spacer 112 source / drain region 114 dielectric layer 116 opening 118 metal layer 120 gate 122 dielectric layer Example The manufacturing process of a double gate is shown in Figure 1A to This is illustrated in Figure 1D. Referring to FIG. 1A, a substrate 100 such as a silicon substrate is provided, and a gate oxide layer 102 is formed thereon. The gate oxide layer 102 is formed by a thermal oxidation method, for example. A conductive layer is formed on the gate oxide layer 102, such as a doped polycrystalline silicon layer 104. To manufacture the doped polycrystalline silicon layer 104, traditionally, a layer of undoped polycrystalline sand is formed by Low Pressure Chemical Vapor Deposition (LPCVD), and then impurities are implanted into the polycrystalline sand layer and Annealing heat treatment activates impurities to make the polycrystalline silicon layer conductive or doped. A sacrificial layer 106 is then formed on the doped polycrystalline silicon layer 104. The sacrificial layer 106 is, for example, an amorphous silicon layer or a silicon nitride layer, and has different etching characteristics from the doped polycrystalline silicon 104 below. The thickness of the sacrificial layer 106 is 5 1 n 9— In ft] n ter I (please read the precautions on the back before filling this page) ''-This paper size is applicable to China National Standard (CNS) A4 specification (210 * 297 mm) A7 B7
45756S 6563twf. doc/006 五、發明說明（讧） 晶矽層之厚度104厚，例如，犧牲層106厚度大約爲摻雜 複晶砂層104的五倍。接著定義犧牲層106及摻雜複晶砂 層104以形成閘極結構(gate structure)的。 之後，在基底上實行輕微的植入以及在閘極結構之側 邊形成側壁間隙壁110,例如是以在前述產生之結構上以 化學氣相沈積（Chemically Vapor Deposit，CVD)—層二氧化 矽層，並以異相回蝕技術蝕刻二氧化矽層以形成側壁間隙 壁110。進一步使用間隙壁110和閘極結構當罩幕，以重 劑量之不純物植入基底100以在基底100上形成源/汲 (source/drain)極區 112。 參照第1B圖’在前述產生之結構上形成一介電層114 以覆蓋住犧牲層106、側壁間隙壁以及被暴露出之閘 氧化層102。介電層114例如是以化學氣相沈積形成一厚 氧化層。之後’利用犧牲層106爲終止層，以化學機械硏 磨法(Chemical Mechanical Polishing，CMP)移去介電層 114 之一部分直到犧牲層106的表面被暴露出來。 接著參照第1C圖，犧牲層ι06(如第1B圖所示)被選 擇性地移除，形成開口 116而暴露出其下方之複晶矽層 104。如果犧牲層106爲非晶矽或氮化矽，可分別利用氦 氣電發蝕刻或溼式触刻移除犧牲層1〇6。當犧牲層106和 摻雜複晶砂層104有不同之触刻特性，即可妥善地控制犧 牲層106之移除，而保持下方之摻雜複晶砍層丨〇4之完整 參照第1D圖’形成金屬層丨18以塡充開口 ιΐ6(如第 1C圖所不）。金屬層118例如是鎢以選擇性之層積形成。 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — lllll1lilli — . I I I l· I I I ^ t - I I I I-- {請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 457569 6563twf·doc/006 五、發明說明（f) 金屬層118和複晶矽層104 -—起形成閘極120。因此’金 屬層118之厚度和犧牲層106之厚度相同。介電層122進 一步沈積在前述產生之結構上以隔離閘極120。 根據上述，本發明提供一種製造雙層閘極之方法’其 在摻雜複晶矽層上形成一金屬層以降低閘極之總電阻率。 當金屬層在熱製程後形成，例如是完成退火熱處理或趨入 製程，以避免例如是高溫金屬氧化等不利的結果產生。此 外犧牲層有和複晶矽層不同之蝕刻特性，可良好的控制犧 牲層之移除。更進一步的，金屬層取代犧牲層而形成’而 不是以金屬層取代複晶矽層之一部分’因此也可良好的控 制金屬層及其下方之複晶矽層厚度° 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 --I I I I I I ----裝！ h!·訂------t I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）45756S 6563twf. Doc / 006 V. Description of the Invention (ii) The thickness of the crystalline silicon layer is 104 thick. For example, the thickness of the sacrificial layer 106 is about five times that of the doped polycrystalline sand layer 104. Next, a sacrificial layer 106 and a doped polycrystalline sand layer 104 are defined to form a gate structure. After that, a slight implantation is performed on the substrate and a sidewall spacer 110 is formed on the side of the gate structure, for example, by chemical vapor deposition (CVD)-a layer of silicon dioxide on the previously generated structure. Layer, and the silicon dioxide layer is etched by a heterophase etch-back technique to form a sidewall spacer 110. The spacer 110 and the gate structure are further used as a mask, and the substrate 100 is implanted with a heavy amount of impurities to form a source / drain region 112 on the substrate 100. Referring to FIG. 1B ', a dielectric layer 114 is formed on the previously generated structure to cover the sacrificial layer 106, the sidewall spacer, and the exposed gate oxide layer 102. The dielectric layer 114 is, for example, a thick oxide layer formed by chemical vapor deposition. After that, using the sacrificial layer 106 as a stop layer, a portion of the dielectric layer 114 is removed by chemical mechanical polishing (CMP) until the surface of the sacrificial layer 106 is exposed. Referring next to FIG. 1C, the sacrificial layer ι06 (shown in FIG. 1B) is selectively removed to form an opening 116 to expose the polycrystalline silicon layer 104 below it. If the sacrificial layer 106 is amorphous silicon or silicon nitride, the sacrificial layer 106 can be removed by using helium gas etching or wet contacting, respectively. When the sacrificial layer 106 and the doped polycrystalline sand layer 104 have different etch characteristics, the removal of the sacrificial layer 106 can be properly controlled, and the doped polycrystalline cleave layer below is kept as a complete reference to FIG. 1D. A metal layer 18 is formed to fill the opening 6 (as shown in FIG. 1C). The metal layer 118 is formed of, for example, tungsten by selective lamination. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) — lllll1lilli —. III l · III ^ t-III I-{Please read the notes on the back before filling this page) Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 457569 6563twf · doc / 006 V. Description of the invention (f) The metal layer 118 and the polycrystalline silicon layer 104 form the gate electrode 120. Therefore, the thickness of the 'metal layer 118 and the thickness of the sacrificial layer 106 are the same. A dielectric layer 122 is further deposited on the previously generated structure to isolate the gate electrode 120. According to the above, the present invention provides a method of manufacturing a double-layered gate, which comprises forming a metal layer on a doped polycrystalline silicon layer to reduce the total resistivity of the gate. When the metal layer is formed after the thermal process, for example, the annealing heat treatment is completed or the process is advanced, to avoid adverse effects such as high temperature metal oxidation. In addition, the sacrificial layer has an etching characteristic different from that of the polycrystalline silicon layer, and the removal of the sacrificial layer can be well controlled. Furthermore, the metal layer is formed instead of the sacrificial layer to form a portion of the polycrystalline silicon layer instead of the metal layer. Therefore, the thickness of the metal layer and the polycrystalline silicon layer under the metal layer can also be well controlled. The preferred embodiment is disclosed as above, but it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The attached application patent shall prevail. --I I I I I I ---- install! h! · Order ------ t I (Please read the precautions on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 7 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)