Λ7 B7 4U5167 五、發明説明（j ) =發明係有關於一種具有空氣邊隙之自我對準τ型 極場效電晶體元件的製造方法，其製程新賴、簡單且 可用以降低電晶體其閘極與源/沒極間之寄生電阻 及寄生電容。 隨著半導體技術的進步，製程技術一直朝深次微米 引曰所以疋件之積集度增加而尺寸亦隨之減小，因此 電曰曰體之寄生電阻亦開始影響元件之傳輸特性。目前用 以降低寄生電阻之方法，主要有自行對準金屬梦化製程 (ide proeess)。然而，此—方式有其限制而影響其應 用。當製程技術再往深次微米縮小時，在以自行對準金 屬石夕化製程形成極細線寬之傳導線時，傳導線之片電阻 會有急速上升的現象(稱為窄線寬效應，_owline_ width effect)。此外，因為熱而引起之聚合效應 (aggl〇meration effect)會使製程之整合更加困難。 為了解決上述深次微米長度範圍閘極之寄生電阻變 大之問題’ τ型閘極是-個报好之選擇，目前τ型問極 已被應用於高速運算之場效電晶體上。而一般τ型閘極 係使用舉離架構（lift_off scheme)來製造，然而此一方法 並不適用於ULSI石夕-金氧半電晶體之架構，因為良率控 制不易。另外’閘極與源β及極間之寄生電容亦是使電晶 體高速傳輸效能表現不佳的原因。 有鑑於此’本發明之主要目的為提供一種具有空氣 邊隙之自我對準Τ型閘極場效電晶體的製造方法，所製 作之場效電晶體除了可用以降低電晶體其閘極與源/汲 本紙乐尺度適用中國國家標準（CNS ) Λ4規格（2丨〇χ297公#_ ) ^-- > - (請先閱讀背面之注意事項再填寫本頁) 訂-- 經濟部中央標準局員工消費合作社印裝 經濟部中央標準局員工消費合作社印聚 405167 五、發明説明（2) 極間之寄生電阻，可有效解決上述窄線寬效應之問題， 以及降低閘極與源/汲極間之寄生電容，而且製程簡單， 其與傳統製程相容所以更可以輕易應用在一般之生產線 上。 為了達到上述目的，本發明提供一種具有空氣邊隙 之T型閘極場效電晶體電元件之製造方法，包括以下之 步驟。 提供半導體基材，上述基材上定義有電晶體元 件，其中上述電晶體元件包括一複晶矽閘極、一薄氧化 層、和源/汲極區延伸。 沈積一介電層於上述基材之上，其中上述介電層可 由，硼磷矽玻璃、磷矽玻璃、硼矽玻璃、TE〇s中之一 者選擇。 使用例如為化學機械研磨法，將上述介電層加以平 坦化，但勿使上述閘極露出。 使用例如為氫氟酸之蝕刻劑，第一次選擇性蝕刻上 述介電層，使得上述閘極之上端之局部露出於上述介層 之上。 形成一堆疊導電層於上述閘極和介電層上，藉以和 上述閘極構成一 τ型閘極結構，其中上述導電層之材質 係選自複晶矽、矽化金屬、摻雜複晶矽、鎢、鈷、及鈦 金屬之一者。 以濕式钮刻法去除上述介電層，而露出整個τ型閘 極。 4 本紙張尺度適用中國國家標準（CNS ) Α4規格（2丨0X 297公釐） --- I n i— n - I n _ _ _ ^ 1 . Λ (請先閱讀背面之注意事項再填寫本頁) 405167 Λ7 Β7 五、發明説明（3) 進行離子佈植，以形成深源/汲極區 經濟部中央梯準局員工消費合作社印衷 佈植步驟亦可緊接在形成丁型閘極架構之後、進行濕式 蝕刻去除介電質之前加以實施，以形成深源/汲極區。 以化學氣相沈積法形成氧化層於上述半導體基材之 上，其中於上述τ型閘極結構之堆疊導電層下方和上述 源/汲極區延伸之間有空氣邊隙存在。 其中上述堆疊導電層之形成方法有二： 一為先行沈積一導電層於上述閉極和上述介電層之 上，再非等向性蝕刻上述導電層，以形成導電間隔物於 上述閘極上端之侧壁上而作為上述堆疊導電層，藉以和 上述閘極構成了型閘極結構，其中上述導電層之姓刻係 使用以_素氣體、齒素化合物、鹽酸、含溴化合物之一 者、或其混合物來進行非等向性乾式蝕刻。 二為針對上述閘極使用選擇性沈積法，以形成上述 堆疊導電層於上述閘極和介電層上，藉以和上述閉極構 成τ型閘極結構。 依據本發明之自我對準了型閘極場效電晶體電元件 =造方法，其製程簡單4可與傳統製程相融合。又依 據本發明所製作之T型_場效電晶體電元件，由於形 ::τ型導電閉極’使閉極之等效之寬度變大，故可以 有效降低閘極寄生電阻之片電阻值。 圈式之簡單說明： :讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉兩個較佳實施例’並配合所附圖式，做詳 (請先閱讀背面之注意事項再填寫本頁) 裝. -m · 本紙張尺度_ B7 擇 405167 五、發明説明（4 ) 細說明如下： 第1A至第1H圖係顯示依據本發明製造方法之第_ 實施例之流程剖面圖； 第2A〜2C圖係顯示第一實施例部份步驟之另一種選 第3 A〜3D圖係顯示本發明第二實施例之部份流程 圖；以及 第4圖係顯示傳統自動對準金屬矽化物閘極以及本 發明T型閘極其閘極片電阻（sheet res丨stance)與其閘極長 度L間之關係。 符號說明： 1〜半導體基材；2〜薄（閘極）氧化層；3〜複晶矽 閘極；4〜延展源/汲極區；5〜介電層；6〜導電層； 7〜深源/汲極區；8〜氧化層；9〜空氣邊隙；1〇〜導電 層。 實施例一： 第1A至第1G圖係顯示依據本發明之製造方法之流 程剖面圖。以下將配合圖式說明本發明之製造方法。 步驟一 提供一半導體基材1，上述基材丨為一般之矽晶片， 其上定義有MOS電晶體元件，其中上述電晶體元件包括 一厚度約2000 A左右之複晶矽閘極3 ' 一厚度介於 20〜200 A左右之薄氧化層2和延展源/沒極區4，如第 1A圖所示。薄氧化層2係以熱氧化法或是化學氣相沈積 -I - I -- I - - - n n n i _ < - t (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印装 私紙乐尺度咖中國國家標準（CNS) Λ4規格（2丨〇χ297公梦- 405167五、發明説明（5) 法而得。 步驟二 B7 所示 沈積一第一介電層5於上述基材i之上，如第⑺圆 經濟部中央標準局員工消費合作社印聚 其中’上述第一介電層5之材料係選自te〇s 玻璃、财玻璃L夕玻璃之—所構成，其厚度 大於上述複晶㈣極3之高度，亦即必須_完全將i 述問極3覆蓋。在此例中以厚度約為5500 A之丁咖作 為第一介電層。 步驟三 再使用例如化學機械研磨法，將上述介電層5加以 平坦化’使其呈現較平坦之表面，但未露出上述閘極3， 如第1C圖所示。 步驟四 使用例如含氫氟酸之蝕刻劑，對上述介電層5進行 第一次選擇性蝕刻，以去除部份上述介電層，而露出閘 極3上端之局部，如第1D圖所示。所露出之閘極3部份 高度dl以小於閘極3高度的二分之一較佳。 步驟五 先行沈積一導電層於上述閘極3和上述介電層$之 上，其厚度介於500〜2000 A之間可依需要來配合設計， 以本實施例而言厚度為1500 A。再對上述導電層進行非 等向性蝕刻，直到露出介電層5為止，以形成導電層間 隔物（spacer) 6於上述閘極3之側壁上，藉以和上述閘極 本紙張尺度適用中國國家榡準（CNS ) Λ4規輅（210X297公#_ ) (請先閱讀背面之注意事項再填寫本頁} 裝 --° 15 經濟部中央標準局員工消費合作社印裝 405167 發明説明（6 j —--- 3構成τ型閘極結構， * a . 如第1E圖所示。 中，上述導電層之材 摻雜複晶矽、鎢、鈷：選自複晶矽、矽化金屬、 餘刻後施以自我校準者，或選自複晶石夕 金屬，以與閑極3之界面序形成之石夕化 電層之關係使用㈣素氣：良::材質為佳。上述導 京礼體、鹵素化合物、鹽酸、含 /臭化合物之一者、哎直、、▼人 _ A 次其混合物，例如Cl2/HBr/SF6之混合 乳體來進行非等向性乾式蝕刻。 步驟六 以濕式餘刻法去除上述介電層5，以露出τ型問極， 結果如第1F圖所示。 步驟七 使用能量介於10〜50KeV，濃度介於1〇,5〜1〇10之砷 離子進行離子佈植，以形成深源/汲極區，如第1G圖所 示，以此實施例而言，可使用能量25 KeV，濃度5χΐ〇 之砷離子進行離子佈植。 步驟八 以化學氣相沈積法形成厚度介於4〇〇〇〜7〇〇〇 Α之氧 化層8於上述半導體基材之上，而將τ型閘極完全加以 覆蓋’在本實施例中，氧化層之厚度為55〇〇 A。其中於 上述T型閘極結構之堆疊導電層6下方和上述源/汲極區 延伸4之間有空氣邊隙9存在。 本實施例中，上述離子佈植步驟（原步驟七），亦可在 形成T型閘極架構之後（步驟五），使用能量介於50〜100 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） m /^1 I- l^i^i 1^1 I 士.m i^n n^i 0¾ 、=° (請先聞讀背面之注意事項再填寫本頁j Λ7 405167 ------ -- B7 五、發明説明（7 ) '—'-Λ7 B7 4U5167 V. Description of the invention (j) = The invention relates to a method for manufacturing a self-aligned τ-type polar field-effect transistor element with an air gap. The manufacturing process is new, simple and can be used to reduce the gate of the transistor. The parasitic resistance and parasitic capacitance between the electrode and the source / non-electrode. With the advancement of semiconductor technology, the process technology has been moving towards deep sub-microns. As a result, the accumulation of components has increased and the size has also decreased. Therefore, the parasitic resistance of electrical components has also begun to affect the transmission characteristics of components. At present, the methods used to reduce the parasitic resistance mainly include self-alignment metal ide proeess. However, this method has its limitations and affects its application. When the process technology is further reduced to the deep sub-micron, when the ultra-fine line width conductive line is formed by the self-aligned metallization process, the sheet resistance of the conductive line will increase rapidly (called the narrow line width effect, _owline_ width effect). In addition, the agglomeration effect due to heat makes integration of the process more difficult. In order to solve the above problem of increasing the parasitic resistance of the gate in the deep sub-micron length range, the τ-type gate is a good choice. At present, the τ-type gate has been applied to high-efficiency field-effect transistors. In general, the τ-type gate is manufactured using a lift_off scheme. However, this method is not applicable to the structure of the ULSI Shixi-metal oxide semi-transistor because the yield control is not easy. In addition, the parasitic capacitance between the gate and the source β and the electrode is also the reason why the high-speed transmission performance of the electric crystal is not good. In view of this, the main purpose of the present invention is to provide a method for manufacturing a self-aligned T-gate field effect transistor with an air gap. The field effect transistor can be used to reduce the gate and source of the transistor in addition to the field effect transistor. / The Chinese paper standard is applicable to the Chinese National Standard (CNS) Λ4 specification (2 丨 〇χ297 公 #_) ^->-(Please read the notes on the back before filling this page) Order-Central Bureau of Standards, Ministry of Economic Affairs Employees 'Cooperative Cooperatives Printed by the Central Standards Bureau of the Ministry of Economy Employees' Cooperative Cooperatives 405167 V. Description of the Invention (2) The parasitic resistance between the electrodes can effectively solve the problem of the narrow line width effect described above, and reduce the gap between the gate and source / drain The parasitic capacitance is simple, and the process is simple. It is compatible with the traditional process, so it can be easily applied to general production lines. In order to achieve the above object, the present invention provides a method for manufacturing a T-gate field effect transistor with an air gap, including the following steps. A semiconductor substrate is provided, and a transistor element is defined on the substrate, wherein the transistor element includes a polycrystalline silicon gate, a thin oxide layer, and a source / drain region extension. A dielectric layer is deposited on the above substrate. The above dielectric layer may be selected from one of borophosphosilicate glass, phosphosilicate glass, borosilicate glass, and TE0s. The dielectric layer is flattened using, for example, a chemical mechanical polishing method, but the gate is not exposed. The dielectric layer is selectively etched for the first time using an etchant such as hydrofluoric acid, so that a part of the upper end of the gate electrode is exposed on the dielectric layer. Forming a stacked conductive layer on the gate and the dielectric layer to form a τ-type gate structure with the gate, wherein the material of the conductive layer is selected from the group consisting of polycrystalline silicon, silicided metal, doped polycrystalline silicon, One of tungsten, cobalt, and titanium. The above dielectric layer is removed by a wet button engraving method, and the entire τ-type gate is exposed. 4 This paper size applies the Chinese National Standard (CNS) Α4 specification (2 丨 0X 297 mm) --- I ni— n-I n _ _ _ ^ 1. Λ (Please read the precautions on the back before filling this page ) 405167 Λ7 Β7 V. Description of the invention (3) Ion implantation to form the staff consumer cooperatives in the deep source / drain zone economy central government ’s quasi-branch staff consumer cooperatives The imprinting steps may also be followed immediately after the formation of the d-type gate 3. Perform a wet etch before removing the dielectric to form a deep source / drain region. An oxide layer is formed on the semiconductor substrate by a chemical vapor deposition method, and there is an air gap below the stacked conductive layer of the τ gate structure and between the source / drain region extensions. There are two methods for forming the stacked conductive layer: First, a conductive layer is deposited on the closed electrode and the dielectric layer, and then the conductive layer is anisotropically etched to form a conductive spacer on the upper end of the gate. On the side wall, as the above-mentioned stacked conductive layer, a gate structure is formed with the above-mentioned gate. The last name of the above-mentioned conductive layer is engraved with one of the following: Or a mixture thereof to perform anisotropic dry etching. The second is to use a selective deposition method for the gates to form the stacked conductive layers on the gates and the dielectric layers, thereby forming a τ-type gate structure with the closed electrodes. The self-aligned gate field effect transistor according to the present invention is a manufacturing method, and its manufacturing process is simple. 4 It can be integrated with the traditional manufacturing process. According to the T-type field-effect transistor device manufactured according to the present invention, since the shape :: τ-type conductive closed electrode 'makes the equivalent width of the closed electrode larger, it can effectively reduce the sheet resistance value of the gate parasitic resistance. . Brief description of the circle type: To make the above-mentioned objects, features, and advantages of the present invention more obvious and easy to understand. 'The following two specific embodiments are enumerated.' Please fill in this page again.) Pack. -M · This paper size _ B7 405167 5. Description of the invention (4) The detailed description is as follows: Figures 1A to 1H show the process cross section of the _th embodiment of the manufacturing method according to the present invention. Figures 2A ~ 2C are alternatives showing some steps of the first embodiment. Figures 3A ~ 3D are partial flowcharts of the second embodiment of the present invention; and Figure 4 is a conventional auto-alignment. The relationship between the metal silicide gate and the T-gate gate sheet resistance of the present invention and its gate length L. Explanation of symbols: 1 ~ semiconductor substrate; 2 ~ thin (gate) oxide layer; 3 ~ polycrystalline silicon gate; 4 ~ stretched source / drain region; 5 ~ dielectric layer; 6 ~ conductive layer; 7 ~ deep Source / drain region; 8 to oxide layer; 9 to air margin; 10 to conductive layer. Embodiment 1: Figures 1A to 1G are cross-sectional views showing the flow of a manufacturing method according to the present invention. The manufacturing method of the present invention will be described below with reference to the drawings. Step 1 provides a semiconductor substrate 1. The substrate 丨 is a general silicon wafer on which a MOS transistor element is defined, wherein the transistor element includes a compound silicon gate 3 ′ with a thickness of about 2000 A. A thin oxide layer 2 and an extended source / inverted region 4 between about 20 and 200 A are shown in FIG. 1A. Thin oxide layer 2 is thermal oxidation or chemical vapor deposition -I-I-I---nnni _ <-t (Please read the precautions on the back before filling this page) Staff of Central Bureau of Standards, Ministry of Economic Affairs Consumption cooperatives printed private papers and paper scales Chinese National Standard (CNS) Λ4 specification (2 丨 〇χ297 公 梦-405167 V. Invention description (5) method. Step 2 B7 deposit a first dielectric layer 5 On the above-mentioned substrate i, as printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, the material of the above-mentioned first dielectric layer 5 is selected from the group consisting of te0s glass and financial glass. , Its thickness is greater than the height of the above-mentioned polycrystalline silicon pole 3, that is to say, it is necessary to completely cover the semiconductor pole 3. In this example, a Dinga with a thickness of about 5500 A is used as the first dielectric layer. For example, a chemical mechanical polishing method is used to planarize the dielectric layer 5 so as to present a relatively flat surface, but the gate 3 is not exposed, as shown in FIG. 1C. Step 4 Use an etchant containing hydrofluoric acid, for example. For the first selective etching of the dielectric layer 5 to remove a part The dielectric layer is exposed, and a part of the upper end of the gate 3 is exposed, as shown in FIG. 1D. The height dl of the exposed gate 3 is preferably less than one-half of the height of the gate 3. Step 5 First, deposit one The conductive layer is above the gate 3 and the dielectric layer, and its thickness is between 500 and 2000 A, which can be designed according to need. In this embodiment, the thickness is 1500 A. The conductive layer is further processed. Anisotropic etching until the dielectric layer 5 is exposed to form a conductive layer spacer 6 on the side wall of the gate 3, so that the Chinese paper standard (CNS) Λ4 is applied to the paper size of the gate Regulations (210X297 公 #_) (Please read the precautions on the back before filling out this page} 装-° 15 Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 405167 Description of the invention (6 j ----- 3 forms τ type Gate structure, * a. As shown in Figure 1E. In the above, the material of the conductive layer is doped with polycrystalline silicon, tungsten, cobalt: selected from polycrystalline silicon, silicided metal, self-calibration after a while, or Relations between the polycrystalline stone and the galvanic layer formed in the interface sequence with the idler 3 Use ㈣ 素 气: Good :: The material is better. One of the above-mentioned guides, halogen compounds, hydrochloric acid, or odorous compounds, hey ,, ▼ people_ A times the mixture, such as Cl2 / HBr / SF6 Mix the emulsion to perform anisotropic dry etching. Step 6: Remove the dielectric layer 5 by a wet post-etching method to expose the τ-type interrogator. The result is shown in Figure 1F. Step 7 uses energy between 10 ~ 50KeV, arsenic ions with a concentration between 10.5 ~ 1010 for ion implantation to form a deep source / drain region, as shown in Fig. 1G. In this embodiment, an energy of 25 KeV can be used. Arsenic ions at a concentration of 5 × 5 were subjected to ion implantation. Step eight is to form an oxide layer 8 with a thickness of 4,000˜7000 by the chemical vapor deposition method on the semiconductor substrate, and completely cover the τ-type gate. In this embodiment, The thickness of the oxide layer is 5500A. An air gap 9 exists between the stacked conductive layer 6 of the T-gate structure and the source / drain region extension 4. In this embodiment, the above-mentioned ion implantation step (the original step 7) can also use an energy between 50 and 100 after forming the T-gate structure (step 5). (210X297 mm) m / ^ 1 I- l ^ i ^ i 1 ^ 1 I taxi. Mi ^ nn ^ i 0¾, = ° (Please read the notes on the back before filling in this page j Λ7 405167 --- ----B7 V. Description of the invention (7) '--'-
KeV，濃度介於1〇丨5〜1〇丨6之砷離子實施佈植，以形成深 源/汲極區7。接著，再以濕式蝕刻法去除上述介電層$ , 以露出T型閘極。最後，以化學氣相沈積法形成氧化層$ 於上述半導體基材之上，而將T型閘極完全加以覆蓋。 上述有變化之部份流程如第2 A〜2C圖所示。 實施例二： 如上述第一實施例之方法，由步驟一至完成上述步 驟四，如第1D圖，所示。 步驟五 一 針對上述閘極使用選擇性沈積法，以形成導 於上述閘極3和介電層5上，藉以和上述閘極構成丁型 閘極結構’如第3 A圖所述。 上述沈積之導電層其厚度介於500〜2000 A之間可 依需要來配合設計，以本實施例而言厚度為 1500 A。上 述導電層之材質係選自複晶矽、矽化金屬、摻雜複晶矽、 鎢、鈷、及鈦金屬之一者，以與閘極3之界面情形良好 之材質為佳。 步驟六 以濕式姓刻法去除上述介電層5，以露出T型閘極， 結果如第3B圖所示。 步驟七 使用能量介於1〇〜50KeV，濃度介於1〇π〜1〇16之砷 離子進行離子佈植，以形成深源/汲極區，如第3C圖所 不，以此實施例而言’可使用能量25KeV，濃度5χ1〇ΐ5 9 本紙張尺歧-- f靖先閱讀背面之注意事一?再填寫本頁) 裝 、1Τ 經濟部中央標準局員工消費合作社印装 經濟部中央標準局員工消費合作社印装 40516« A7 B7 •、發明説明（8 ) 之砷離子進行離子佈植。 步驟八 以化學氣相沈積法形成氧化層8於上述半導體基材 之上，而將τ型閘極覆蓋，其中於上述τ型閘 極結構之堆疊導電層上述源/汲極區延伸4之間 有空氣邊隙9存在，如第3D圖所示。 同第一實施例，離子佈植之步驟亦可調整在形成τ 型閘極結構之後、蝕刻介電質之前，使用能量介於5〇〜1〇〇KeV, arsenic ions with a concentration between 10 and 5 to 10 and 6 are implanted to form a deep source / drain region 7. Then, the dielectric layer $ is removed by a wet etching method to expose the T-gate. Finally, an oxide layer is formed on the semiconductor substrate by a chemical vapor deposition method, and the T-gate is completely covered. The above part of the process is shown in Figures 2A to 2C. Embodiment 2: As in the method of the above-mentioned first embodiment, the steps from step one to step four are completed, as shown in FIG. 1D. Step 51: A selective deposition method is used for the above gates to form the gates 3 and the dielectric layer 5 so as to form a D-type gate structure with the gates, as shown in FIG. 3A. The thickness of the deposited conductive layer is between 500 and 2000 A, which can be designed as required. In this embodiment, the thickness is 1500 A. The material of the conductive layer is one selected from the group consisting of polycrystalline silicon, silicided metal, doped polycrystalline silicon, tungsten, cobalt, and titanium, and a material with a good interface with the gate 3 is preferred. Step 6: The above dielectric layer 5 is removed by a wet etching method to expose the T-gate. The result is shown in FIG. 3B. Step 7 Use arsenic ions with an energy between 10 ~ 50KeV and a concentration between 10π ~ 1016 to perform ion implantation to form a deep source / drain region, as shown in Fig. 3C. In this embodiment, Say 'Can use energy 25KeV, concentration 5χ1〇ΐ5 9 This paper ruler-f Jing first read the notes on the back? Then fill out this page), 1T Central Standards Bureau of the Ministry of Economic Affairs, Consumer Consumption Coordination, printed central standards of the Ministry of Economic Affairs Bureau employee consumer cooperatives printed 40516 «A7 B7 • Invention description (8) for arsenic ion implantation. Step Eight: A chemical vapor deposition method is used to form an oxide layer 8 on the semiconductor substrate and cover the τ-type gate, wherein the stacked conductive layer of the τ-type gate structure extends between the source / drain region 4 An air gap 9 exists, as shown in Fig. 3D. As in the first embodiment, the ion implantation step can also be adjusted after the formation of the τ-type gate structure and before the dielectric is etched, using an energy between 50 and 100.
KeV，濃度介於10i5〜1〇16之砷離子實施佈植，以形成深 源/汲極區7。 第4圖係顯示傳統自動對準金屬矽化物閘極以及本 發明τ型閘極其閘極片電阻（sheet resistance)與其閘極長 度L間之關係，其中實心點代表傳統閘極，空心點代表 本發明之T型閘極。 請參照第4圖，在閘極長度L減小時（尤其l<〇 4 " m時）’报明顯地傳統閘極之片電阻值隨之急速增加。而 本發明之T型閘極在L約為g.4 // m時，其报0月顯地突 出本發明之效果，閘極電阻相當低。再將L降低時，雖 然由於聚合效應（aggl〇meration effect)之故而使本發明τ 型閘極之片電阻增大，但相較於傳統之閘極，仍有大幅 之改善。 另外，傳統之T型閘極與源/汲極間存在有氧化層等 介電質’而以本發明製造之τ型閘極其與源/沒極間則存 在有空氣邊隙。由於空氣之介電常數為卜】、於—般氧化 10 本纸張尺度適用㈣碎^ ( CNS )鐵格（ nn nn In a^^i— ^^^1 <^1 ^^^1 士穴 -- - - m am ---/ 、-口 (請先閲讀背面之注意事項再填寫本頁}KeV, arsenic ions with a concentration between 10i5 and 1016 are implanted to form a deep source / drain region7. FIG. 4 shows the relationship between the traditional self-aligned metal silicide gate and the gate resistance of the τ-type gate electrode and the gate length L of the present invention, where the solid points represent the traditional gates and the hollow points represent the Invented T-gate. Please refer to FIG. 4, when the gate length L is reduced (especially when l < 〇 4 " m) ', it is obvious that the sheet resistance value of the conventional gate increases rapidly. However, when the T-gate of the present invention is about g.4 // m, it is reported that the effect of the present invention is prominently displayed in January, and the gate resistance is relatively low. When L is lowered, although the sheet resistance of the τ-type gate of the present invention is increased due to the aggregation effect, it is still significantly improved compared to the conventional gate. In addition, there is a dielectric such as an oxide layer between the conventional T-gate and the source / drain, and an air gap exists between the τ-gate and the source / inverter manufactured by the present invention. Since the dielectric constant of the air is bu], it is generally oxidized at 10 paper sizes. (CNS) iron grid (nn nn In a ^^ i— ^^^ 1 < ^ 1 ^^^ 1 Acupoint ----m am --- / 、 -mouth (Please read the precautions on the back before filling this page}
4UD10Y B7 發明説明（9) 層之介電常數（约4左右* )因此本發明製作之電晶體，其 閘極與源/没極間之寄生雷 所會小於傳統之丁型間極， 所以^速傳輸之效能表現上較為優異。 綜上所述，依據本發明所㈣之了㈣極場效電晶 體電元件，形成一T型導雷間朽麻甘 玉等電閘極，使其等效之寬度變大， 故可以有效地降低閘極間之寄生電阻，且制空氣邊隙 之形成，使閘極與源/汲極間之寄生電容值降低。 雖然本發明已以兩個較佳實施例揭露如上，鈇 ^以限定本發明’任何熟悉本項技㈣，在残離本 1明之精神和範圍内，當可做些許之更動和潤飾，因此 本發明之保護範圍當視後附之中請專利範圍所界定 準。 ^ 經濟部中央標準局員工消費合作社印袈 1 n 適 度 尺 張 紙 準 I標 f家 國 國4UD10Y B7 Description of the Invention (9) The dielectric constant of the layer (about 4 or so *). Therefore, the parasitic lightning between the gate and the source / non-electrode of the transistor made by the present invention will be smaller than that of the traditional D-type interpole, so ^ The performance of fast transmission is superior. In summary, according to the present invention, a field-effect transistor transistor element is formed to form a T-type lightning conductor, such as magma jade and other electric gates, so that the equivalent width becomes larger, so it can be effectively reduced. The parasitic resistance between the gates and the formation of air gaps reduce the parasitic capacitance between the gate and the source / drain. Although the present invention has been disclosed as above with two preferred embodiments, it is to limit the present invention. 'Anyone familiar with this technology, within the spirit and scope of the present invention, can make some changes and retouching. The scope of protection of the invention shall be determined by the scope of patents as attached. ^ Seal of the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 1 n Moderate Rule Paper Standard I Standard f
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