4640twf,doc/0 02425611 ^ 經濟部智慧財產局員工消費合作杜印製 五、發明説明（I ) 本發明是有關於一種閘極導體結構之製造方法，且特 別是有關於一種可降低閘極電阻之方法。 在深次微米的積體電路技術中，由於在線寬、接觸面 積及接面深度等都逐漸縮小的情形下，爲了能有效地提高 .元件的工作品質，降低電阻並減少電阻及電容所造成的信 號傳遞延遲(RC Delay)，因此在製作閘極時傾向於以金屬 矽化合物（Silicide)，取代較早的複晶矽。由於金屬矽化物 的製程中不需要微影，故由此類製程製作之金屬矽化物又 稱爲自行對準金屬矽化物（Self-aligned Silicide，Saiicide)。 常見的自行對準金屬矽化物例如矽化鈦（TiSix)及矽化鈷 (C〇Six)等。矽化鈦因具有較低電阻及製程上較易控制等優 點，成爲最常被採用之金屬矽化物材料。 第丨A圖至第1 C圖所繪的是習知的複昂砍閘極自 行對準金屬矽化物之製作流程剖面示意圖。首先，請參照 第1A圖，提供一具有隔離結構102之半導體基底1〇〇， 其上已形成一閘氧化層104和複晶砂聞極1〇6，以及源極/ 汲極區108。 然後，請參照第1B圖，利用濺鍍的方式，在半導體 基底100與複晶矽閘極106表面上沈積一層金屬層110。 接著，利用快速加熱製程(RTP)的方式，使金屬層110與 基底100以及複晶矽閘極1〇6上之矽成份反應，而在複晶 矽閘極106與源極/汲極區108表面形成一層金屬矽化物 1 12 - 接著，再用濕蝕刻的方式將未參與反應或反應後所剩 3 (請先聞讀背面之注iW-項-»填寫本頁) -裝. 訂 線 本紙張尺度適用中國國家標準（CNS ) A4规格（2丨0X297公釐） A7 4 6 4 61 w fs cl 〇 c / 0 0 2 4 2^^1 1_E_ 五、發明説明（i) 餘的金屬去除，即形成如第1C圖所示之閘極結構。 (請先閲讀背面之注意事項再填寫本頁) 然而隨著複晶矽閘極尺寸的日漸縮小，閘極寬度（Gate width)愈小，在複晶矽閘極上之金屬矽化物的成長會因金 屬矽化物與複晶矽接觸的應力（Stress)太大，或是成核位置 .(Nucleation site)太少，導致金屬政化物薄膜品質不佳，致 使片電阻（Sheet Resistant)增加，閘極的阻値愈來愈大且不 穩定，造成閘極操作時間延遲(RC Delay)，影響閘極操作 的效能。 本發明就是在提供一種閘極導電結構之製造方法，可 增加閘極上形成自行對準金屬矽化物之面積，可有效降低 閘極之阻値。而且，並不影響增加元件之通道區長度 (Channel length)= 經濟部智慧財產局員工消費合作社印製 本發明提供一種閘極導電結構之製造方法，適用於半 導體基底，在基底上已形成一閘氧化層，其方法係包括： 在閘氧化層上形成一導體層，之後，在導體層上形成一層 罩幕層，然後，圖案化導體層和該罩幕層，以形成一閘極 導體層和一閘極罩幕層。接著，在閘極導體層和閘極罩幕 層的側壁上形成第一間隙壁。之後，去除閘極罩幕層，然 後在閘極導體層上、緊鄰第一間隙壁側壁形成第二間隙 壁。最後，在第二間隙壁表面和閘極層表面形成一金屬矽 化物層，完成本發明之閘極導體結構。 依照本發明一較佳實施例，本發明所揭露之閘極導體 結構之材質爲多晶矽。此外，本發明所述之閘極導體結構 的製造方法，其中第二間隙壁之形成方法包括：全面性形 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨OX”7公嫠） 46461 νν Γ. d〇c/n〇2 A7 B7 五、發明説明（彡）4640twf, doc / 0 02425611 ^ Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by V. Description of the invention (I) The present invention relates to a method for manufacturing a gate conductor structure, and in particular to a method for reducing gate resistance Method. In deep sub-micron integrated circuit technology, as the line width, contact area, and junction depth are gradually reduced, in order to effectively improve the quality of the components, reduce the resistance and reduce the resistance and capacitance caused by Signal transmission delay (RC Delay), so when manufacturing the gate, tend to replace the earlier polycrystalline silicon with metal silicon compounds (silicide). Since lithography is not required in the process of metal silicide, the metal silicide produced by this process is also called self-aligned silicide (Saiicide). Common self-aligned metal silicides such as titanium silicide (TiSix) and cobalt silicide (CoSix). Titanium silicide has become the most commonly used metal silicide material due to its lower resistance and easier control in the manufacturing process. Figures 丨 A to 1C are cross-sectional schematic diagrams of the conventional manufacturing process of the self-aligned metal silicide of Fu Ang chop gate. First, referring to FIG. 1A, a semiconductor substrate 100 having an isolation structure 102 is provided, on which a gate oxide layer 104, a polycrystalline sand electrode 106, and a source / drain region 108 have been formed. Then, referring to FIG. 1B, a metal layer 110 is deposited on the surfaces of the semiconductor substrate 100 and the polycrystalline silicon gate 106 by sputtering. Next, the rapid heating process (RTP) is used to make the metal layer 110 react with the silicon components on the substrate 100 and the polycrystalline silicon gate 106, and the polycrystalline silicon gate 106 and the source / drain region 108 are reacted. A layer of metal silicide is formed on the surface 1 12-Then, wet etching will be used to remove the remaining 3 or unreacted after the reaction (please read the note iW-item on the back side-»Fill in this page)-binding. Paper size applies Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) A7 4 6 4 61 w fs cl 〇c / 0 0 2 4 2 ^^ 1 1_E_ 5. Description of the invention (i) Removal of remaining metal, That is, the gate structure shown in FIG. 1C is formed. (Please read the notes on the back before filling in this page) However, as the size of the polycrystalline silicon gates is getting smaller and smaller, the gate width becomes smaller. The growth of metal silicides on the polycrystalline silicon gates will be caused by The stress (Stress) between the metal silicide and the polycrystalline silicon is too large, or the nucleation site is too small, which leads to the poor quality of the metallization film, resulting in an increase in sheet resistance. The resistance is getting larger and more unstable, causing gate operation time delay (RC Delay) and affecting the gate operation performance. The present invention is to provide a method for manufacturing a gate conductive structure, which can increase the area of self-aligned metal silicide formed on the gate, and can effectively reduce the resistance of the gate. Moreover, it does not affect the increase of the channel length of the component = printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The present invention provides a method for manufacturing a gate conductive structure, which is suitable for a semiconductor substrate, and a gate has been formed on the substrate. An oxide layer includes the following steps: forming a conductor layer on the gate oxide layer, forming a mask layer on the conductor layer, and then patterning the conductor layer and the mask layer to form a gate conductor layer and A gate cover curtain layer. Next, a first gap wall is formed on the sidewalls of the gate conductor layer and the gate cover curtain layer. After that, the gate cover curtain layer is removed, and then a second gap wall is formed on the gate conductor layer, next to the side wall of the first gap wall. Finally, a metal silicide layer is formed on the second gap wall surface and the gate layer surface to complete the gate conductor structure of the present invention. According to a preferred embodiment of the present invention, the material of the gate conductor structure disclosed in the present invention is polycrystalline silicon. In addition, the manufacturing method of the gate conductor structure according to the present invention, wherein the forming method of the second gap wall includes: comprehensively adapting the size of the paper to the Chinese National Standard (CNS) A4 specification (2 丨 OX ”7mm) 46461 νν Γ. d〇c / n〇2 A7 B7 V. Description of the invention (彡)
成一多晶矽層覆蓋在閘極導體層和第一間隙壁上，以及非 等向性蝕刻此多晶矽層，以形成第二間隙壁。另外罩幕層 之材質包括氮化矽。金屬矽化物層之材質包括矽化鈦。 根據本發明-較佳實施例，本發明提供一種閘極導電 .結構，包括一閘氧化層，一閘極導體層位於閘氧化層上， 一第一間隙壁位於閘極導體層側壁，且高出閘極導體層， 一第二間隙壁位於閘極導體層上，且緊鄰第一間隙壁。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 1 丁 第hA圖至第ic圖繪示習知的複晶矽閘極自行對準 金屬矽化物之製作流程剖面示意圖；以及 一種 第2A圖至第2E圖爲根據本發明一較佳實施例 閘極導體結構的製造方法流程剖面圖。 圖式之標記說明： 經濟部智慧財產局員工消费合作社印製 100、200 :基底 104、202 :閘氧化層 106、204a :閘極導體層 108、212 :源極/汲極區 1 1〇 :金屬層 112 ' 218 :金屬矽化物層 204 :導體層 206 ·罩幕層 本紙張尺度逋用中國國家標率（CNS > A4规潘 U10X297公嫠） 4646lwl'.doc/0 024 2 5 6 1 1 A7 B7 五、發明説明（¥ ) 206a :閘極罩幕層 208 :淺摻雜區 210 :間隙壁 214 :多晶矽層 216:多晶矽間隙壁 經濟部智慧財產局員工消費合作社印製 貫施例 請參照第2圖’其繪示依照本發明一較佳實施例的一 種圖。 第2A圖至第2E圖所示，爲根據本發明一較佳實施例 的一種閘極導體結構的製造方法流程剖面圖。 首先，請參照第2A圖，提供一基底2〇〇 ’妗基底200 .匕依序形成一層閘氧化層202、一層導體層204和一層罩 幕層206。其中氧化層2〇2的材質例如爲二氧化矽，導體 層204的材質例如爲多晶矽，罩幕層206的材質例如是氮 化矽。典型的形成方法例如以熱氧化法在基底200表面形 成一層厚度例如約數百個A的氧化層2〇2，接著例如以化 學氣相沈積法在氧化層202上形成一層多晶矽層204 ’然 後，再以化學氣相沈積在多晶矽層204上形成一層氮化矽 層 206 ° 接著，請參照第2B圖，圖案化多晶矽層2〇4和氮化 矽層206，以形成閘極導體層204a和閘極罩幕層206a。 而典型的形成方法例如爲傳統的微影蝕刻技術。之後，對 本紙張尺度適用中國國家榡準（CNS ) A4说格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4646t w1 <hic/〇()24256 1 1_ b77 __ 五、發明説明（f) 基底200進行一離子植入步驟’以在基底2〇〇中形成之淺 摻雜區208。然後，以任何適用的習知方法，在閘極導體 層204a和閘極卓幕層206a的側壁上形成一間隙壁210。 間隙壁210的材質例如是二氧化矽。 然後，請參照第2C圖，以閘極罩幕層2〇6a和間隙壁 210爲罩幕，對基底200進行一離子植入步驟，在基底2〇〇 形成源極/汲極區212。之後，去除閘極罩幕層2〇6a ’暴露 出閘極導體層204a。其中去除閘極罩幕層2〇6a的方法例 如是濕式蝕刻法。 接著，請參照第2D圖，在基底2〇〇上全面地形成一 層多晶矽層214，且覆蓋閘極導體層2〇4a和間隙壁21〇。 其中多晶矽層典型的形成方法例如是化學氣相沈積法。 接下來，請參照第2E圖，回蝕刻多晶矽層214，以在 在該閘極導體層204a.上、緊鄰間隙壁21〇側壁的位置上 形成一多晶矽間隙壁216。典型的方法例如是非等向性乾 蝕刻法。之後’去除閘極導體層204a和間隙壁210以外 之閘氧化層202，以露出基底200表面後，進行自行對準 金屬矽化物製程，在閘極導體層204a、多晶矽間隙壁216 和源極/汲極2 I2的表面上形成一層金屬矽化物層218。其 中金屬矽化物層的材質例如是矽化鈦、矽化鎢，典型的形 成方法例如是先在閘極導體層204a、多晶矽間隙壁216和 源極/汲極區212的表面上形成一層金屬層，再進行一快 速加熱製程（RTP)，使金屬層與閘極導體層204a、多晶矽 間隙壁.216和源極/汲極212表面的多晶矽面反應，形成 7 (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 旅 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 4M \v i. cl o c / 0 iJ 24 2 56 1 1 五、發明説明（〔） 一層金屬矽化物層218，再例如以濕刻法去除未反應之金 屬層，完成金屬矽化物製程。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 1. 本發明利用在閘極導體層上形成一多晶矽間隙壁， 可增加金屬矽化物與多晶閘極的接觸面，可有效降低閘極 導體層之阻値，避免產生RC延遲，可增加元件品質的可 信度。 2. 本發明提供之閘極導體結構，可在不增加閘極之線 寬的情形下，增加金屬矽化物與多晶矽閘極之間的接觸面 積，金屬矽化物與多晶矽間有較佳的接合，可有效降低聞 極導體層之阻値，可增加元件操作效能。 3. 本發明提供之閘極導體結構和其製造方法，可在不 增加通道寬度之情形下，可有效降低閘極導體層之電阻。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS〉A4規格（210X297公釐）A polycrystalline silicon layer is formed to cover the gate conductor layer and the first spacer, and the polycrystalline silicon layer is anisotropically etched to form a second spacer. In addition, the material of the cover layer includes silicon nitride. The material of the metal silicide layer includes titanium silicide. According to the present invention-a preferred embodiment, the present invention provides a gate conductive structure. The gate conductive layer includes a gate oxide layer, a gate conductor layer on the gate oxide layer, and a first gap wall on a side wall of the gate conductor layer. Out of the gate conductor layer, a second gap wall is located on the gate conductor layer and is adjacent to the first gap wall. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: 1 dingdi Figures hA to ic show schematic cross-sectional schematic diagrams of the conventional fabrication process of self-aligned metal silicides of complex silicon gates; and Figures 2A to 2E are gate conductor structures according to a preferred embodiment of the present invention. Manufacturing process flow sectional view. Symbols of the drawings: 100, 200 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: substrates 104, 202: gate oxide layers 106, 204a: gate conductor layers 108, 212: source / drain regions 1 10: Metal layer 112 '218: Metal silicide layer 204: Conductor layer 206 · Cover layer This paper standard uses Chinese national standard (CNS > A4 gauge U10X297 male) 4646lwl'.doc / 0 024 2 5 6 1 1 A7 B7 V. Description of the invention (¥) 206a: Gate cover curtain layer 208: Lightly doped region 210: Spacer wall 214: Polycrystalline silicon layer 216: Polycrystalline silicon spacer Referring to FIG. 2 ', a diagram according to a preferred embodiment of the present invention is shown. Figures 2A to 2E are cross-sectional views showing the flow of a method for manufacturing a gate conductor structure according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a substrate 200 ′ is provided. A gate oxide layer 202, a conductor layer 204, and a mask layer 206 are sequentially formed. The material of the oxide layer 202 is, for example, silicon dioxide, the material of the conductor layer 204 is, for example, polycrystalline silicon, and the material of the mask layer 206 is, for example, silicon nitride. A typical forming method is, for example, forming an oxide layer 200 with a thickness of, for example, several hundreds A on the surface of the substrate 200 by a thermal oxidation method, and then forming a polycrystalline silicon layer 204 ′ on the oxide layer 202 by, for example, a chemical vapor deposition method. Then, a silicon nitride layer 206 is formed on the polycrystalline silicon layer 204 by chemical vapor deposition. Next, referring to FIG. 2B, the polycrystalline silicon layer 204 and the silicon nitride layer 206 are patterned to form a gate conductor layer 204a and a gate. The polar mask layer 206a. A typical formation method is, for example, a conventional lithography technique. After that, the Chinese national standard (CNS) A4 scale (210X297 mm) is applied to this paper standard (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4646t w1 < hic / 〇 () 24256 1 1_ b77 __ 5. Description of the invention (f) The substrate 200 is subjected to an ion implantation step 'to form a shallowly doped region 208 in the substrate 200. A spacer 210 is then formed on the sidewalls of the gate conductor layer 204a and the gate curtain layer 206a by any suitable known method. The material of the partition wall 210 is, for example, silicon dioxide. Then, referring to FIG. 2C, an ion implantation step is performed on the substrate 200 using the gate mask layer 206a and the spacer 210 as a mask to form a source / drain region 212 on the substrate 200. After that, the gate shield layer 206a 'is removed to expose the gate conductor layer 204a. The method of removing the gate shield layer 206a is, for example, a wet etching method. Next, referring to FIG. 2D, a polycrystalline silicon layer 214 is fully formed on the substrate 200, and covers the gate conductor layer 204a and the spacer 21o. A typical method for forming a polycrystalline silicon layer is, for example, a chemical vapor deposition method. Next, referring to FIG. 2E, the polycrystalline silicon layer 214 is etched back to form a polycrystalline silicon spacer wall 216 on the gate conductor layer 204a. And close to the sidewall of the spacer wall 21o. A typical method is, for example, an anisotropic dry etching method. After 'removing the gate conductor layer 204a and the gate oxide layer 202 other than the spacer 210 to expose the surface of the substrate 200, a self-aligned metal silicide process is performed, and the gate conductor layer 204a, the polycrystalline silicon spacer 216, and the source / A metal silicide layer 218 is formed on the surface of the drain electrode 2 I2. The material of the metal silicide layer is, for example, titanium silicide or tungsten silicide. A typical method for forming the metal silicide layer is to first form a metal layer on the surface of the gate conductor layer 204a, the polycrystalline silicon spacer 216, and the source / drain region 212. A rapid heating process (RTP) is performed to make the metal layer react with the gate conductor layer 204a, the polycrystalline silicon spacer. 216, and the polycrystalline silicon surface of the source / drain 212 surface to form 7 (Please read the precautions on the back before filling in this Page)-Binding and ordering. The paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 4M \ v i. Cl oc / 0 iJ 24 2 56 1 1 V. Description of the Invention ([) A metal silicide layer 218, and the unreacted metal layer is removed, for example, by a wet etching method to complete the metal silicide process. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has the following advantages: 1. The present invention utilizes the formation of a polycrystalline silicon spacer on the gate conductor layer, which can increase the contact surface between the metal silicide and the polycrystalline gate, which can effectively Reducing the resistance of the gate conductor layer and avoiding RC delay can increase the reliability of component quality. 2. The gate conductor structure provided by the present invention can increase the contact area between the metal silicide and the polysilicon gate without increasing the line width of the gate, and the metal silicide and the polysilicon have a better joint. It can effectively reduce the resistance of the smell conductor layer and increase the operation efficiency of the device. 3. The gate conductor structure and manufacturing method provided by the present invention can effectively reduce the resistance of the gate conductor layer without increasing the channel width. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) This paper size applies to Chinese national standards (CNS> A4 specification (210X297 mm)