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TW371364B - Method for making buried diffusion junction - Google Patents

Method for making buried diffusion junction

Info

Publication number
TW371364B
TW371364B TW087100942A TW87100942A TW371364B TW 371364 B TW371364 B TW 371364B TW 087100942 A TW087100942 A TW 087100942A TW 87100942 A TW87100942 A TW 87100942A TW 371364 B TW371364 B TW 371364B
Authority
TW
Taiwan
Prior art keywords
buried diffusion
diffusion junction
forming
short circuit
cause
Prior art date
Application number
TW087100942A
Other languages
English (en)
Inventor
Nai-Jen Peng
ming-zong Yang
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW087100942A priority Critical patent/TW371364B/zh
Priority to US09/063,021 priority patent/US6020251A/en
Application granted granted Critical
Publication of TW371364B publication Critical patent/TW371364B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
TW087100942A 1998-01-23 1998-01-23 Method for making buried diffusion junction TW371364B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW087100942A TW371364B (en) 1998-01-23 1998-01-23 Method for making buried diffusion junction
US09/063,021 US6020251A (en) 1998-01-23 1998-04-20 Method of forming buried diffusion junctions in conjunction with shallow-trench isolation structures in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087100942A TW371364B (en) 1998-01-23 1998-01-23 Method for making buried diffusion junction

Publications (1)

Publication Number Publication Date
TW371364B true TW371364B (en) 1999-10-01

Family

ID=21629401

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087100942A TW371364B (en) 1998-01-23 1998-01-23 Method for making buried diffusion junction

Country Status (2)

Country Link
US (1) US6020251A (zh)
TW (1) TW371364B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW364180B (en) * 1998-01-12 1999-07-11 United Microelectronics Corp A method for producing buried diffusion junction
US6204147B1 (en) * 1999-03-16 2001-03-20 United Silicon Incorporated Method of manufacturing shallow trench isolation
JP2001135718A (ja) * 1999-11-08 2001-05-18 Nec Corp トレンチ分離構造の作製方法
US6817903B1 (en) 2000-08-09 2004-11-16 Cypress Semiconductor Corporation Process for reducing leakage in an integrated circuit with shallow trench isolated active areas
EP1569263B1 (de) * 2004-02-27 2011-11-23 OSRAM Opto Semiconductors GmbH Verfahren zum Verbinden zweier Wafer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5763309A (en) * 1996-06-24 1998-06-09 Macronix International Co., Ltd. Self-aligned isolation and planarization process for memory array
JP3018993B2 (ja) * 1996-07-26 2000-03-13 日本電気株式会社 半導体装置の製造方法
US5960284A (en) * 1997-12-05 1999-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming vertical channel flash memory cell and device manufactured thereby

Also Published As

Publication number Publication date
US6020251A (en) 2000-02-01

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Legal Events

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MK4A Expiration of patent term of an invention patent