3447twf.doc/006 A7 B7 五、發明説明（/ ) 本發明是有關於一種積體電路的製造方法，且特別是 有關於一種淺溝渠隔離（Sha 11 ow Tr ench I s ο 1 a t i on ; STI)區的製造方法。 元件隔離區係用以防止載子（Carrier)通過基底而 在相鄰的元件間移動之用。典型的元件隔離區係形成於稠 密的半導體電路，比如是動態隨機存取記憶體（DRAM)中 相鄰的場效電晶體（Field Effect Transistor ; FET)之 間，藉以減少由場效電晶體產生的漏電流（Current Leakage)現象。典型形成元件隔離區的方法係採用局部 區域氧化技術（LOCOS)。由於局部區域氧化技術的日趨 成熟，因此可藉此技術，以較低的成本獲得信賴度高且有 效之元件隔離結構。然而，採用局部區域氧化的方式具有 應力產生的問題與場隔離結構周圍鳥嘴區（Bird’s Beak) 的形成等缺點。其中，特別是鳥嘴區的形成，使得在小型 的元件上，以LOCOS方式所形成之場隔離結構並不能做有 效地隔離，所以在高密度（High Density)元件中’必須 以較易於調整大小的淺溝渠隔離方式所形成之元件隔離 結構來取代。 淺溝渠隔離法是一種利用非等向性蝕刻方法在半導 體基底中形成溝渠，然後在溝渠中塡入氧化物，以形成元 件之場隔離區的技術。由於淺溝渠隔離法所形成之場隔離 區具有可調整大小（Scaleable)的優點，並且可避免傳 統區域氧化法隔離技術中鳥嘴侵蝕（Bi rd's Beak Encroachment )的缺點，因此，對於次微米（Sub-Micron) 3 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） I.^--------裝-- (請先閲讀背面之注意事項再填寫本頁) -訂 線· 經濟部中央標隼局員工消費合作杜印製 3447t wf.doc/006 3447t wf.doc/006 經齊部中夬瞟隼苟員31¾費說 A7 ____ B7 五、發明説明（之） 的互補式金氧半導體（CMOS)製程而言，是一種較爲理想 與的隔離技術。 第1A圖至第1F圖是習知一種淺溝渠隔離區製造流程 之剖面圖。 δ円梦照弟1A圖首先，以熱氧化（Thermal Oxidation) 法在矽基底100上形成一層墊氧化層（Pad Oxide) 102， 此墊氧化層102係用以在製程中保護矽基底100的表面。 接著’在墊氧化層102上，以低壓化學氣相沉積法（L〇w Pressure Chemical Vapor Deposition; LPCVD)形成一 層氮化矽罩幕層104。 然後，請參照第1B圖，以習知的方法在氮化矽罩幕靥 104表面上形成一層光阻層（圖中未顯示），並依序蝕刻 氮化矽罩幕層104、墊氧化層1〇2與矽基底100，以在石夕 基底100中形成溝渠106。其後，再將光阻層去除。 請參照第1C圖，以高溫熱氧化法，在溝渠106所褰_ 出的矽基底100表面，形成襯氧化層（Liner Layer ) 108， 其中襯氧化層108會延伸至與位於溝渠1〇6之頂端邊角邀 (Top Corner)的墊氧化層1〇2接觸。 請參照第1D圖，在溝渠106中塡入絕緣層110，例如 是利用常壓化學氣相沉積法（APCVD )形成的氧化矽層。 接著，再於高溫下，執行密實化（Dens if icat ion)步驟， 以形成氧化矽材質之絕緣層110。 其後，請參照第1E圖，以氮化矽罩幕層104作爲硏磨 終止層，利用化學機械硏磨法去除氮化矽罩幕層104上;^ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） L--------幕------訂------線 (請先聞讀背面之注意事項再填寫本頁j 3447twf. doc/006 A7 B7 五、發明説明（> ) 多餘的絕緣層110，而在溝渠106中殘餘著絕緣層110a。 (請先閱讀背面之注意事項再填寫本頁) 請參照第1F圖，去除氮化矽罩幕層104，露出墊氧化 層102。其後，利用氫氟酸（HF)溶液浸蝕，以去除墊氧 化層102，在基底100中形成場隔離區110b。 在上述習知的方法中，在絕緣層110進行密實化步驟 時，由於氧化矽材質的絕緣層110會對矽基底100產生機 械應力（Mechanical Stress)，進而造成元件的失效 (Device Failure) ° 因此本發明的目的就是在提供一種淺溝渠隔離區的製 造方法，在淺溝渠中形成流動性的氧化矽層，此流動性的 氧化矽層在製程中可以有效地釋放對矽基底產生的機械 應力，因而可以避免元件的失效。 經濟部中央標準局員工消費合作社印製 根據本發明的主要目的，提出一種淺溝渠隔離區的製 造方法，包括：在基底上形成一墊氧化層，並在墊氧化層 上形成一罩幕層。之後，定義罩幕層與墊氧化層，並在基 底中形成一溝渠後，續在溝渠所裸露的基底表面形成一襯 氧化層。接著，在溝渠中形成一層流動性的絕緣.層，此流 動性的絕緣層包括一層摻雜的氧化矽層，其上再覆蓋一層 氧化砂層。然後，去除罩幕層和墊氧化層，以形成淺溝渠 隔離區。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 5 本^尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 一 3447tvvr\doc/006 3447tvvr\doc/006 經濟、W中央標準局員工消費合作社印製 A7 B7 五、.發明説明（f ) :.第1A圖至第if圖係繪示傳統式淺溝渠隔離區之製造 流程的剖面圖；以及 ,第2A圖至第2H圖係繪示根據本發明之一較佳實施 例，一種淺溝渠隔離區之製造流程的剖面圖。 圖式之標記說明： 100，200 基底 102，202 墊氧化層 104，204 罩幕層 106，206 溝渠 108, 208 襯氧化層 110, 110a, 212, 212a, 212b 絕緣層 110b，214 場隔離區. 210，210a 流動性的絕緣層 實施例 第2A圖至第2H圖係繪示根據本發明之一較佳實施 例’ 一種淺溝渠隔離區之製造流程的剖面圖。 請參照第2A圖，首先，在矽基底200上形成一層墊氧 化層202 ’例如以熱氧化法，此墊氧化層202係用以在製 程中保護該矽基底200的表面。接著，在墊氧化層202上， 例如以低壓化學氣相沉積法（LPCVD)形成一層氮化矽罩 幕層204。 然後，請參照第2B圖，以習知的方法在氮化矽罩幕層 204表面上形成一層光阻層（圖中未顯示），並依序蝕刻 氮化矽罩幕層204、墊氧化層202與矽基底200，例如以 6 本紙張尺度適用中國國家操準（CNS ) A4規格（210X297公釐） 、言 (請先閱讀背面之注意事項再填寫本頁)3447twf.doc / 006 A7 B7 V. Description of the Invention (/) The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a shallow trench isolation (Sha 11 ow Tr ench I s 1 ati on; STI ) Zone manufacturing method. The element isolation area is used to prevent carriers from moving between adjacent elements through the substrate. A typical device isolation region is formed in a dense semiconductor circuit, such as between adjacent field effect transistors (FETs) in dynamic random access memory (DRAM), thereby reducing the generation of field effect transistors. Leakage (Current Leakage) phenomenon. A typical method of forming an element isolation region is to use a local area oxidation technique (LOCOS). As the local area oxidation technology becomes more mature, this technology can be used to obtain a reliable and effective component isolation structure at a lower cost. However, the use of localized area oxidation has the disadvantages of stress generation and the formation of Bird's Beak around the field isolation structure. Among them, the formation of the bird's beak area makes the field isolation structure formed by the LOCOS method on small components not effective for isolation. Therefore, in high density (High Density) components, the size must be adjusted easily. Element isolation structure formed by the shallow trench isolation method. Shallow trench isolation is a technique that uses a non-isotropic etching method to form a trench in a semiconductor substrate, and then implants an oxide into the trench to form a field isolation region for the device. Because the field isolation region formed by the shallow trench isolation method has the advantages of being scalable, and can avoid the shortcomings of Bird's Beak Encroachment in the traditional area oxidation isolation technology, so for the sub-micron (Sub -Micron) 3 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) I. ^ -------- Package-(Please read the precautions on the back before filling this page)-Order Line · Consumer cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs and Du Duan 3447t wf.doc / 006 3447t wf.doc / 006 31 members of the Ministry of Economic Affairs 31¾ Fees said A7 ____ B7 V. Complementation of the invention description (the) As for the CMOS process, it is an ideal isolation technology. Figures 1A to 1F are cross-sectional views of a conventional manufacturing process for a shallow trench isolation area. Figure 1A of Dream Dreamer First, a pad oxidation layer 102 is formed on the silicon substrate 100 by a thermal oxidation method. The pad oxidation layer 102 is used to protect the surface of the silicon substrate 100 during the manufacturing process. . Next, a silicon nitride masking layer 104 is formed on the pad oxide layer 102 by Low Pressure Chemical Vapor Deposition (LPCVD). Then, referring to FIG. 1B, a conventional method is used to form a photoresist layer (not shown) on the surface of the silicon nitride mask 104, and sequentially etch the silicon nitride mask 104 and the pad oxide layer. 102 and the silicon substrate 100 to form a trench 106 in the Shixi substrate 100. After that, the photoresist layer is removed. Referring to FIG. 1C, a high-temperature thermal oxidation method is used to form a liner layer 108 on the surface of the silicon substrate 100 out of the trench 106. The liner oxide layer 108 extends to the trench 106. The top corner pad (102) of the pad oxide layer contacts. Referring to FIG. 1D, an insulating layer 110 is inserted into the trench 106, for example, a silicon oxide layer formed by an atmospheric pressure chemical vapor deposition (APCVD) method. Then, a dens if icat ion step is performed at a high temperature to form an insulating layer 110 made of silicon oxide. Thereafter, please refer to FIG. 1E, using the silicon nitride masking layer 104 as a honing stop layer, and removing the silicon nitride masking layer 104 by a chemical mechanical honing method; ^ This paper standard applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) L -------- curtain ------ order ------ line (please read the precautions on the back before filling in this page j 3447twf. Doc / 006 A7 B7 5. Description of the invention (>) Excessive insulating layer 110, and the insulating layer 110a remains in the trench 106. (Please read the precautions on the back before filling this page) Please refer to Figure 1F to remove the silicon nitride The mask layer 104 exposes the pad oxide layer 102. Thereafter, the pad oxide layer 102 is etched with a hydrofluoric acid (HF) solution to remove the pad oxide layer 102 to form a field isolation region 110b in the substrate 100. In the conventional method described above, When the insulating layer 110 is densified, the silicon oxide-based insulating layer 110 generates mechanical stress on the silicon substrate 100, thereby causing device failure. Therefore, the object of the present invention is to provide a shallow Method for manufacturing trench isolation area, forming fluid silicon oxide layer in shallow trench This fluid silicon oxide layer can effectively release the mechanical stress on the silicon substrate during the manufacturing process, so that the failure of the component can be avoided. Printed by the Consumer Cooperative of the Staff of the Central Standards Bureau of the Ministry of Economic Affairs according to the main purpose of the present invention, a shallow A method for manufacturing a trench isolation area includes: forming a pad oxide layer on a substrate, and forming a mask layer on the pad oxide layer. Then, defining the mask layer and the pad oxide layer, and forming a trench in the substrate, Continue to form a lining oxide layer on the exposed substrate surface of the trench. Then, a fluid insulation layer is formed in the trench. This fluid insulation layer includes a doped silicon oxide layer, which is then covered with an oxide sand layer. Then, the mask layer and the pad oxide layer are removed to form a shallow trench isolation area. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is provided below in cooperation with The attached drawings are described in detail as follows: Brief description of the drawings: 5 This standard applies to China National Standard (CNS) A4 (210X297 mm)-344 7tvvr \ doc / 006 3447tvvr \ doc / 006 Economy, W Printed by A7 B7, Consumer Cooperatives of the Central Bureau of Standards 5. Description of Invention (f): Figures 1A to if show the traditional shallow trench isolation area A cross-sectional view of the manufacturing process; and FIGS. 2A to 2H are cross-sectional views showing a manufacturing process of a shallow trench isolation area according to a preferred embodiment of the present invention. 102, 202 pad oxide layer 104, 204 cover curtain layer 106, 206 trench 108, 208 line oxide layer 110, 110a, 212, 212a, 212b insulation layer 110b, 214 field isolation zone. 210, 210a fluid insulation layer embodiment 2A to 2H are cross-sectional views illustrating a manufacturing process of a shallow trench isolation area according to a preferred embodiment of the present invention. Referring to FIG. 2A, first, a pad oxidation layer 202 'is formed on the silicon substrate 200, for example, by a thermal oxidation method. The pad oxidation layer 202 is used to protect the surface of the silicon substrate 200 during the process. Next, a silicon nitride mask layer 204 is formed on the pad oxide layer 202 by, for example, low pressure chemical vapor deposition (LPCVD). Then, referring to FIG. 2B, a photoresist layer (not shown) is formed on the surface of the silicon nitride mask layer 204 by a conventional method, and the silicon nitride mask layer 204 and the pad oxide layer are sequentially etched. 202 and silicon substrate 200, for example, 6 paper sizes are applicable to China National Standards (CNS) A4 specifications (210X297 mm), words (please read the precautions on the back before filling this page)
3 44 71 w f. d ο c/0 Ο 6 A7 _B7_ 五、發明説明（r) 非等向性蝕刻法，用以在矽基底200中形成溝渠206，而 溝渠206的深度約爲0.2〜0.8 μιη。其後，再將光阻層去除。 請參照第2C圖，以高溫熱氧化法，例如於約 900〜11Q0°C的溫度下，在溝渠206所暴露出的矽基底200 表面，形成襯氧化層208，其厚度約爲100埃〜1000埃， 其中襯氧化層208會延伸至與位於溝渠206之頂端邊角處 的墊氧化層202接觸。 請參照第2D圖，在基底200上形成流動性的絕緣層 210，例如是利用習知的方法塗佈一層流動性氧化矽 (Flowable Oxide ; Fox)層，絕緣層210的厚度約爲5000 埃〜10000埃，且塡滿溝渠206。流動性的氧化矽層較一般 的氧化矽層具有較佳的溝塡能力（Gap-Filling Capability)，且流動性的氧化矽層可以做爲應力釋放緩 衝層（Stress Release Buffer)，在後續的製程中可以 有效地釋放對矽基底產生的機械應力，因而可以避免元件 的失效。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 請參照第2E圖，由於塗佈後的流動性氧化矽裏仍有溶 劑存在，而且流動性氧化矽表面並不平坦，因此需經融化 (Melt)及熱流（Flow)等製程，然後在氮氣（沁）環境 下，於溫度約400°C下，使流動性的絕緣層210進行爐火 固化（Cur ing )。 之後，移除部份的流動性的絕緣層210，例如利用回 鈾刻（Etch Back)步驟，直到溝渠206中之流動性的絕 緣層210a的表面低於基底200的表面，且暴露出部份的 7 本紙張尺度適用中國國家榇準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 3447twf.doc/006 八了 B7 五、發明説明（6) 襯氧化層208。此步驟可以避免在後續進行離子植入步驟 後，含有摻質之流動性的絕緣層210a暴露於基底200的 表面，甚至存在於後續形成閛極的區域。 接著，對流動性的絕緣層210a進行離子植入步驟，離 子植入的摻質例如爲硼或磷等，除了可以避免流動性的絕 緣層210a中殘餘溶劑的出氣（Outgassing)問題，並且 可以使流動性的絕緣層210a的質地變硬。 請參照第2F圖，在基底200'上形成絕緣層212，例如 是利用常壓化學氣相沉積法（APCVD)形成的氧化矽層， 並且塡滿溝渠206。絕緣層212爲摻雜之氧化矽層，其覆 蓋於溝渠206中之流動性的絕緣層210a上，可以防止流 動性的絕緣層210a中的摻質，擴散至後續沈積於基底200 表面上而形成閛極的導電層中，或甚至擴散至通道區 (Channel Region )中。 接著，再於高溫下，例如約700〜1200°C的溫度下，執 行密實化步驟，使氧化矽材質之摻雜的絕緣層212的結構 更爲密實。此一密實化步驟亦可以省略不做。 S靑參照第.2G圖，去除氮化砂罩幕層204上之多餘自勺糸色 緣層212，例如利用化學機械硏磨法（CMP)，以氮化砂罩 幕層204作爲硏磨終止層，而在溝渠206中殘餘箸流動性 的絕緣層210a，且流動性的絕緣層210a上被絕緣餍2l2a 所覆蓋。 請參照第2H圖，依序去除罩幕層204與墊氧化廢2〇2， 以在基底200中形成場隔離區214。典型的方法係以濕式 8 本紙張尺度適用中國國家樣率（CNS ) A4規格（210X297公釐） -~~~ ----------_种衣------1T------# (請先閲讀背面之注意事項再填寫本览) 3447twf.doc/006 A7 B7 五、發明説明（7) (請先閲讀背面之注意事項再填寫本頁) 蝕刻法，例如磷酸溶液去除氮化矽材質之罩幕層204，裸 露出墊氧化層202。其後，再利用濕式鈾刻法，例如氫氟 酸（HF)溶液浸蝕，以去除墊氧化層202，在基底200中 形成場隔離區214，其中場隔離區214係由流動性的絕緣 層210a和絕緣層2.12b所組成。 綜上所述’本發明的特徵在於： 1. 本發明在淺溝渠中形成流動性的絕緣層，續於流動 性的氧化矽層上覆蓋另一絕緣層'，以防止流動性的絕緣層 中的摻質擴散至形成閘極的導電層中，或甚至擴散至通道 區中，此流動性的絕緣層在製程中可以有效地釋放對矽基 底產生的機械應力，因而可以避免元件的失效。 2. 本發明的製程均與現有的製程相容，極適合廠商的 生產安排。 雖然本發明已以一較佳實施例揭露如上’然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 適 度 張 紙 _ 一本 經濟部中央標準局員工消費合作社印製3 44 71 w f. D ο c / 0 Ο 6 A7 _B7_ V. Description of the invention (r) Anisotropic etching is used to form trenches 206 in the silicon substrate 200, and the depth of the trenches 206 is about 0.2 to 0.8 μιη. After that, the photoresist layer is removed. Referring to FIG. 2C, a high-temperature thermal oxidation method, for example, at a temperature of about 900 to 11Q0 ° C, forms a liner oxide layer 208 on the surface of the silicon substrate 200 exposed by the trench 206, and has a thickness of about 100 angstroms ~ 1000 angstroms, wherein the liner oxide layer 208 will extend to contact the pad oxide layer 202 at the top corner of the trench 206. Referring to FIG. 2D, a fluid insulating layer 210 is formed on the substrate 200. For example, a flowable oxide (Fox) layer is coated by a conventional method. The thickness of the insulating layer 210 is about 5000 angstroms ~ 10,000 Angstroms, and filled the trench 206. The flowable silicon oxide layer has better Gap-Filling Capability than the ordinary silicon oxide layer, and the flowable silicon oxide layer can be used as a stress release buffer layer in the subsequent process. It can effectively release the mechanical stress on the silicon substrate, and thus can avoid the failure of the component. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) Please refer to Figure 2E, because there is still a solvent in the flowable silicon oxide after coating, and the surface of the flowable silicon oxide It is not flat, so it needs to undergo processes such as melting and heat flow, and then under a nitrogen atmosphere, at a temperature of about 400 ° C, the fluid insulation layer 210 is cured by fire (Cur ing). ). After that, a part of the fluid insulating layer 210 is removed, for example, by using an Etch Back step, until the surface of the fluid insulating layer 210a in the trench 206 is lower than the surface of the substrate 200, and a part is exposed. 7 This paper size applies to the Chinese National Standard (CNS) A4 (210X297 mm) printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 3447twf.doc / 006 Eight B7 V. Description of the invention (6) Oxidation layer 208. This step can avoid the exposure of the dopant-containing insulating layer 210a to the surface of the substrate 200 even after the subsequent ion implantation step, even in the regions where the cathode is formed later. Next, an ion implantation step is performed on the fluid insulating layer 210a. The dopant of the ion implantation is, for example, boron or phosphorus. In addition to avoiding the problem of outgassing of the residual solvent in the fluid insulating layer 210a, The texture of the fluid insulating layer 210a is hardened. Referring to FIG. 2F, an insulating layer 212 is formed on the substrate 200 ', for example, a silicon oxide layer formed by an atmospheric pressure chemical vapor deposition (APCVD) method, and the trench 206 is filled. The insulating layer 212 is a doped silicon oxide layer, which covers the fluid insulating layer 210a in the trench 206, and can prevent dopants in the fluid insulating layer 210a from diffusing to the subsequent deposition on the surface of the substrate 200 to form The conductive layer of the cathode is even diffused into the channel region. Then, a compaction step is performed at a high temperature, for example, about 700 to 1200 ° C, to make the structure of the doped insulating layer 212 made of silicon oxide more compact. This compaction step can also be omitted. That is, referring to FIG. 2G, the excess self-colored edge layer 212 on the nitrided sand mask layer 204 is removed. For example, using chemical mechanical honing method (CMP), the nitrided sand mask layer 204 is used as a honing termination. In the trench 206, a fluid insulating layer 210a remains, and the fluid insulating layer 210a is covered by an insulating layer 2112a. Referring to FIG. 2H, the mask layer 204 and the pad oxidation waste 202 are sequentially removed to form a field isolation region 214 in the substrate 200. The typical method is to use the wet type 8 paper size to apply China National Sample Rate (CNS) A4 specification (210X297 mm)-~~~ ----------_ seed clothing ----- 1T ------ # (Please read the notes on the back before filling in this list) 3447twf.doc / 006 A7 B7 V. Description of the invention (7) (Please read the notes on the back before filling this page) Etching method, For example, a phosphoric acid solution is used to remove the mask layer 204 made of silicon nitride, and the pad oxide layer 202 is exposed. Thereafter, a wet uranium etching method, such as etching with a hydrofluoric acid (HF) solution, is used to remove the pad oxide layer 202 to form a field isolation region 214 in the substrate 200. The field isolation region 214 is a fluid insulating layer 210a and insulating layer 2.12b. In summary, the present invention is characterized by: 1. The present invention forms a fluid insulating layer in a shallow trench, and continues to cover another insulating layer on the fluid silicon oxide layer, to prevent the fluid insulating layer from flowing. The dopant diffuses into the conductive layer forming the gate electrode, or even into the channel region. This fluid insulating layer can effectively release the mechanical stress on the silicon substrate during the manufacturing process, so that the failure of the component can be avoided. 2. The manufacturing process of the present invention is compatible with the existing manufacturing process, which is very suitable for the manufacturer's production arrangement. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. Moderate sheet of paper _ printed by a consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs
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