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TW360873B - Semiconductor integrated circuit and decoding circuit of memory - Google Patents

Semiconductor integrated circuit and decoding circuit of memory

Info

Publication number
TW360873B
TW360873B TW086117097A TW86117097A TW360873B TW 360873 B TW360873 B TW 360873B TW 086117097 A TW086117097 A TW 086117097A TW 86117097 A TW86117097 A TW 86117097A TW 360873 B TW360873 B TW 360873B
Authority
TW
Taiwan
Prior art keywords
circuit
transistor
common
common transistor
inverters
Prior art date
Application number
TW086117097A
Other languages
English (en)
Inventor
Toru Iwata
Hironori Akamatsu
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Application granted granted Critical
Publication of TW360873B publication Critical patent/TW360873B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
TW086117097A 1996-11-20 1997-11-15 Semiconductor integrated circuit and decoding circuit of memory TW360873B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30904196 1996-11-20

Publications (1)

Publication Number Publication Date
TW360873B true TW360873B (en) 1999-06-11

Family

ID=17988171

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086117097A TW360873B (en) 1996-11-20 1997-11-15 Semiconductor integrated circuit and decoding circuit of memory

Country Status (3)

Country Link
US (1) US5970018A (zh)
KR (1) KR100506644B1 (zh)
TW (1) TW360873B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000100174A (ja) * 1998-09-18 2000-04-07 Oki Micro Design Co Ltd 半導体記憶装置
JP2001267431A (ja) * 2000-03-17 2001-09-28 Nec Corp 半導体集積回路装置及びその製造方法
US6593776B2 (en) * 2001-08-03 2003-07-15 Intel Corporation Method and apparatus for low power domino decoding
US6668358B2 (en) * 2001-10-01 2003-12-23 International Business Machines Corporation Dual threshold gate array or standard cell power saving library circuits
JP2003132683A (ja) * 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP3831270B2 (ja) * 2002-01-31 2006-10-11 株式会社ルネサステクノロジ 論理回路及び半導体集積回路
JP2004021574A (ja) * 2002-06-17 2004-01-22 Hitachi Ltd 半導体装置
US6934181B2 (en) * 2003-02-06 2005-08-23 International Business Machines Corporation Reducing sub-threshold leakage in a memory array
JP4354917B2 (ja) * 2003-02-27 2009-10-28 富士通マイクロエレクトロニクス株式会社 半導体記憶装置
US20060181950A1 (en) * 2005-02-11 2006-08-17 International Business Machines Corporation Apparatus and method for SRAM decoding with single signal synchronization
US7385858B2 (en) * 2005-11-30 2008-06-10 Mosaid Technologies Incorporated Semiconductor integrated circuit having low power consumption with self-refresh
JP2007164922A (ja) * 2005-12-15 2007-06-28 Matsushita Electric Ind Co Ltd デコーダ回路
US20080285367A1 (en) * 2007-05-18 2008-11-20 Chang Ho Jung Method and apparatus for reducing leakage current in memory arrays
JP2008306281A (ja) * 2007-06-05 2008-12-18 Nec Electronics Corp 半導体装置
US20090307891A1 (en) * 2008-06-17 2009-12-17 Ge-Hitachi Nuclear Energy Americas Llc Method and apparatus for remotely inspecting and/or treating welds, pipes, vessels and/or other components used in reactor coolant systems or other process applications
US9672930B2 (en) * 2015-05-29 2017-06-06 Silicon Storage Technology, Inc. Low power operation for flash memory system
JP6417306B2 (ja) 2015-09-18 2018-11-07 日立オートモティブシステムズ株式会社 電子制御装置及びその制御方法
US9653131B1 (en) * 2016-02-12 2017-05-16 Micron Technology, Inc. Apparatuses and methods for voltage level control

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5387827A (en) * 1990-01-20 1995-02-07 Hitachi, Ltd. Semiconductor integrated circuit having logic gates
JP2631335B2 (ja) * 1991-11-26 1997-07-16 日本電信電話株式会社 論理回路
JPH0818021A (ja) * 1994-07-04 1996-01-19 Nippon Telegr & Teleph Corp <Ntt> ゲートアレイ型集積回路
DE69532376T2 (de) * 1995-05-31 2004-06-09 United Memories, Inc., Colorado Springs Schaltung und Verfahren zum Zugriff auf Speicherzellen einer Speicheranordnung
US5808500A (en) * 1996-06-28 1998-09-15 Cypress Semiconductor Corporation Block architecture semiconductor memory array utilizing non-inverting pass gate local wordline driver

Also Published As

Publication number Publication date
US5970018A (en) 1999-10-19
KR100506644B1 (ko) 2006-01-27
KR19980042626A (ko) 1998-08-17

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees