SU873417A1 - Pulse frequency scaler - Google Patents

Description

(54) THE DIVIDER OF THE PULSE OF THE PULSE OF THE PULSE

. , one .

The invention relates to a pulse technique.

 A pulse frequency divider is known, comprising a shift register consisting of N memory elements, two NO elements, an EXCLUSIVE OR element, and an EXCLUSIVE OR NO element, connected together with. shift register bits 11.,

However, the device is not sufficiently reliable.

The closest in technical essence to the invention is a frequency divider, a pulse following, containing an NAND element and four connected in series bits, each of which contains a memory trigger and two switching triggers, the first inputs of each of which are connected to the input bus , the output of the first switching trigger of the first discharge is connected to the second inputs of switching triggers of the second and third discharge and the second input of the second switching trigger of the fourth discharge, the output of the first switch A second trigger trigger is connected to the third and fourth inputs of the second patch trigger of the third bit.

the output of the first switching trigger of the third bit is connected to the third and fourth inputs of the second switching trigger of the fourth bit, the inputs of the additional logic element AND IS NOT connected to the outputs of the second switching trigger of the fourth bit, the single output of the first switching

The 10 trigger of which is connected to the auxiliary input of the first switching trigger of the second bit, and the single output of the second switching trigger of the third discharge of the fourth bit

15 is connected to the auxiliary input of the first switching trigger of the first discharge and the second additional input of the first switching trigger of the second discharge 2.

The disadvantage of this device

20 is low reliability.

The purpose of the invention is to increase the reliability of the device.

To this end, the frequency divider

25 following pulses, containing four bits, each of which, except the third, includes the first and second switching triggers and a memory trigger, the zero input of which is connected to a single output

thirty

the first switching trigger and the zero input of the second switching trigger, the zero output of which is connected to the single memory trigger input, the single output to the zero input of the first switching trigger, and the single input to the single output of the memory trigger of the same bit, while the third The bit contains a memory trigger and a switching trigger, the zero output and the unit input of which are connected respectively to the single input and the single output of the memory trigger of the same bit, and the commutation input to the zero input th trigger discharge to third inputs of the first unit and the zero input of the second trigger switching the input bus is connected, the zero output of the first trigger switching of the first discharge is connected to a zero and unity; .vho-. By the second switching trigger of the second bit, the zero output of the first switching trigger of the second bit is connected to the zero and single inputs of the switching trigger of the third bit, and the first and second inputs of the first additional element AND-NOT are connected to the single and zero outputs of the second switching trigger of the fourth bit Yes, the single output of which is connected to the first additional single input of the first switching trigger of the first bit, was entered into the additional EE element, the output to It is connected to the zero and single inputs of the second switching trigger of the fourth bit whose zero output is connected to the first additional zero inputs of the switching switch of the third bit memory and to the first input of the second additional IS element, the second input of which is connected to the third output switch of the third trigger bit while the single output of the first switching trigger of the fourth bit is connected to the second additional single input of the switching trigger of the first discharge and with additional zero inputs of the first switching trigger and trigger the memory of the third discharge.

The drawing shows a block diagram of the device.

It contains four bits 1–4, the combo trigger triggers of which are executed on AND-NOT elements 5-18, and the memory triggers are executed on AND-NOT elements 19-26, and the additional AND-HE elements 27 and 28, input 29 and output 30 tires.

The device works as follows.

In the initial state, the first-bit memory trigger is in the single state, while the remaining memory trigger is in the zero state.

Under the action of the signal in the divider, the usual —intervalue of incoming pulses in the binary code is performed. With the arrival of the seventh impulse GA, the output of the AND-NE logic element 7 is a signal equal to (logical zero, which sets the fourth-bit memory trigger to a single state, and the third-bit memory trigger — into the zero state and which through the first additional logical IS-NOT 28 enters the output. Next, the incoming pulses are normally recalculated and with the arrival of the fourteenth pulse into A code 1111 is set up in the divider. After the end of the fourteenth pulse, an output equal to a logical zero appears at the output of the NAND 18 logic element, and through the first additional NAND 28 logic element arrives at the output bus 30.

With the arrival of the fifteenth pulse on the pulse, the logical elements AND-NOT 10 and 16 are opened, at the output they appear signals equal to logical zero, which set the memory triggers, except the first bit, to the zero state. Simultaneously, the formation of the output signal is stopped.

The first-bit memory trigger does not change its state, since the logical element AND-NOT 16 remains closed first by a signal equal to a logical zero from the output of the logical element AND-NOT 18, and then by a signal from the output of the logical element AND-NOT 16. After the end The input signal is returned to the initial state 0001.

Thus, the divider outputs two output pulses for 15 input pulses, i.e. frequency division is 7.5. In addition, the divider allows frequency division by 15. The output signal will be the signal from the output of the EPE 16 logic element.

The introduction of the second additional logical element IS-HE 27 with the corresponding 1U1 and connections allows to exclude one switching trigger from the third bit of the frequency divider, which reduces the number of logic elements and significantly increases the reliability of the frequency divider.

Claims (1)

Invention Formula A pulse frequency divider containing four bits, each of which, except the third, includes the first and second switches, 5-position triggers and a memory trigger.