SU884150A1 - Reversible pulse counter digit - Google Patents

Description

(54) DISCHARGE REVERSIBLE COUNTER

one

The invention relates to devices for the reverse division of the frequency of pulsed signals and can be used in the construction of reverse and differential meters for various purposes for measuring, control, and computing equipment.

Reversing pulse counters are known, each bit in which contains a counting trigger, first and second coincidence elements and an assembly element (element OR), the first and second inputs of which are connected respectively to the first and second inputs of the reversible counter, which are connected to the first inputs the first and second matches of the match, the second inputs of which are connected respectively to the direct and inverse outputs of the counting trigger, and the outputs of the first and second elements of the match are connected respectively to ne the left and the second outputs of the discharge pulse counter 1

The disadvantage of this bit of the reversible counter is the relatively large delay in the formation of the output signal in the counting,: - - () so. which is compared with the usual pulses

With binary binary counters, in addition to the time required for the actual triggering trigger to operate, the additional time required for the operation of the interdigit switching element is required (in this case, its functions perform matching and assembly elements).

The known discharge of a reversible pulse counter, containing two input buses, a counting trigger and three IS-NE inputs, an output, the first and second inputs of the first AND-NOT inputs

10 are connected respectively to the counting input of the counting trigger, to the outputs of the second and third IS-NOT elements, the first inputs of which are connected to the first and second respectively.

15 input buses, the second inputs of the second and third elements AND-NOT are connected respectively with the direct and inverse outputs of the counting trigger of the previous bit 2.

A disadvantage of the known device is

Claims (2)

20 is a relatively low speed, -hto is associated with a delay of transfer signals in the elements of NAND, and relatively low functionality, which is due to the fact that the discharge cannot count pulses arriving at the input buses at the same time. The purpose of the invention is to expand the functionality and speed of performance. To achieve the goal, a reversible pulse counter containing two input buses, the first counting trigger, two control buses and a second counting trigger, whose installation input is connected to the forward output of the first counting the trigger, the counting input, the control input and the installation input of which are connected respectively to the first input bus, to the first control bus and to the direct output of the second counting trigger, the counting input and the control input which connects with the second input bus and the second control line respectively, and in the discharge of reversible pulses each counting trigger contains four AND-OR-H elements and two NOT elements, the input of the first element is NOT connected to the counting input of the counting trigger, with the first I inputs of the first structures And the first and second elements AND-I.PI-NOT, the installation input of the counting trigger is connected to the first input of the first structure AND the third element AND-OR-NOT and to the input of the second element NOT, the output of which is connected to the first input of the first structure And the fourth element is AND-IL NOT, the second input of the first structure of which is connected to the inputs of the second structures AND the first and second elements AND-OR-NOT, to the control input of the counting trigger and to the second input of the first structure AND the third element AND-OR-NOT whose output connected to the input of the second structure AND the fourth element AND.ILM-NB and with the second input of the first structure AND the second element AND-YLI-NOT, the output of which is connected to the input of the third structure AND the first element AND-OR-NOT and to the first input of the third structure And the fourth element AND-OR-NOT whose output is connected to the input of the second structure AND the third element AND-OR-NOT and the second input of the first structure AND the first element AND-OR-NOT, the exit of which is connected to the input of the third structure AND the second element and the first input of the third structure AND the third element AND-OR-NOT, the second inputs of the third structures AND the third and fourth elements AND-OR-NOT connected to the output of the first element NOT. FIG. 1 shows a diagram of the discharge of a reversible pulse knob; of figs. 2 - boom on the circuit of each counting trigger of the reversing pulse counter. The bit pattern of the reversible pulse counter contains counting triggers 1 and 2; tires {ravziuni. 3 and 4-, input buses 5 and 6. The installation input D of the counting trigger 2 is connected to the direct output of the counting trigger .4 the counting input C, the input of the T switch, and the input of the installation D of which is connected to the input bus 5, of the control board 3, etc. the output of the counting trigger 2, the Grounding input T and the counting input from which are connected respectively to the control 4 and the input is 6; the counting trigger (FIG. 2) contains elements 7-10 AND-OR-NOT and elements 11 and 12 NOT, the input element 12 is NOT connected to the counting input of the 13 counting trigger, with the first inputs of the first structures tour AND elements 10 and 9 AND-ILINE, input 14 of the installation of the counting trigger is connected to the first input of the first structure AND element 8 AND-OR-NOT and to the input of the il element NOT, the output of which is connected to the first input of the first structure AND element 7 AND- ORIN, the second input of the first structure of which is connected to the inputs of the second structures AND elements 9 and 10 AND-OR-NOT, with input 15 of the control of the counting trigger and with the second input, the first structure AND element 8 AND-OR-NOT, the output of which is connected to the input of the second structure AND element 7 AND-OR-NOT and with the second input of the first page of the structure AND ELE 9 AND-OR-NOT, the output of which is connected to the input of the third structure AND element 10 M-OR-NOT and to the first input of the third structure AND element 7 AND OR NOT. the output of which is connected to the input of the second structure AND element 8 th-OR-NOT and to the second input of the first structure AND element 10 AND-OR-NOT, the output of which is connected to the input of the third structure AND element 9 th-OR-NOT and to the first input: the third structure AND element 8 AND-OR-NOT, the second inputs of the third structure AND and the elements 8 and 7 AND-OR-NOT connect} 5Y with the BFJFXOAOM element 12 NOT. The device works as follows. Fu51ktsionirovakie countable flops 1 and 2 are not on; shchaets from fznktsi-oi-shrovani conventional schetn5H triggers two-stroke timing based on the main and comm pgatsio {shogo RS-TpKiTepoB on elements of AND-OR-NO element, if the input 15) Regents T of the flip-flop A control signal was supplied from the control bus 5 (3 or 4), which ensures that this trigger operates in the counting mode. In this case, the census of information entering the input 15 of installation D of this counting trigger into this trigger is blocked. Thus, this trigger works in counting mode. If a logical signal is sent to the input 15 of the control T from the bc-keys (3 or 4) of the discharge control, allowing the copying of information received at the input 14 of installation D of this counting trigger, the operation of this trigger in the counting mode is blocked and it appears in Record this information. Thus, if, for example, trigger 1 operates in a counting mode, then it performs counting mode for two and a counter containing successively connected bits, if logic 4 has logic signals that prohibit operation in counting mode, will work as a summation counter. If the control signal is inversely proportional, the device will operate as an output counter. In this case, due to the census of information in the trigger, which operates in the counting mode, the codes recorded in the forward counting triggers 1 and the additional counting triggers 2 will be the same. When changing control signals, the counter is reversed. In the present invention, other counting triggers can also be used, and the relationship between the bits to build the actual counter can be improved in accordance with known technical solutions. Thus, MorjT counters can be implemented as sequential binary, decimal counters with end-to-end transfers and counters with group transfer, etc., and the speed of such counters will be equal to the speed of summing or subtracting counters. This technical solution can be used for independently splitting and subtracting accounts, if, in this case, control signals are sent to shirkk 3 and 4, prohibiting the copying of information, and the initial setting of identical codes can be provided by enabling the sigals, which will wipe the functionality of the device. Claim 1. K13r d reversible counter of pulses containing two input strains, the first is countable trigger, characterized in that, in order to extend the functionality and improve performance, a control is entered and a second counting trigger, the input of which is connected to The first output of the first counting trigger, the counting input, the control input and the input of which are connected respectively with the first input, the first control bus and the direct input of the second counting trigger, the counting input and input d control are connected correspondingly with the second input schi-. Noah and second control. 2. The discharge according to claim 1, which means that each counting trigger contains four AND-OR-NOT elements and two NOT elements, the input of the first element is NOT connected to the counting input of the counting trigger, with the first inputs of the first structures and the first and second elements OR, NO, the installation input of the counting trigger is connected to the first input of the first structure AND the third element AND-OR-NOT and to the input of the second element NOT, the output of which is connected to the first input of the first structure AND the fourth element AND-OR-NOT, the second input of the first structure of which is connected to the input the second structures of the first and second elements AND-OR-NOT, with the control input of the counting trigger and the second input of the first structure AND the third element AND-OR-NOT, the output of which is connected to the input of the second structure AND the fourth element AND-OR-NOT and with the second input of the first structure AND of the second element AND-OR-NOT, the output of which is connected to the input of the third structure AND of the first element AND-OR-NOT and with the first input of the third structure of the fourth element AND-OR-NOT, whose LCHOD is connected to the input of the second structures of the third element AND-OR-NOT and from the second pmm input of the first structure AND the first element AND-OR-NOT, the output of which is connected to the input of the third structure AND the second-element AND-OR-NOT and with the first input of the third structure AND the third change AND-OR-NOT, the second inputs of the third structure And the third to the fourth EL-unions are AND-OR-NOT connected to the code of the first element NOT. Sources of information received during the examination 1.Shushkov EI and others. Multichannel counting impulse (. L., Energie, 1971, pp. 3, p. 19. 2, Bukrzev I.N. and others. Microelectronic Schemes of ball devices, M., Sovetskoye Rvdao, 1975, p, 117, Fig. 5, 14 (protot). Have