SU966913A1 - Checking device - Google Patents

Description

(DEVICE CONTROL

one

The invention relates to a pulse technique and can be used to control when a counter reaches a predetermined code state in digital measurement and computing systems.

A control device is known that contains a multiplexer with a number of inputs equal to the size of the counter being monitored, a trigger with set inputs, a delay element and a fl3 coincidence element. The disadvantage of this control device is its limited functionality.

It is also known that a counter / 1π device contains a counter, a multiplexer, a trigger, an inverter, and a coincidence element, the first of which is connected to the inverter output, and the first trigger input is connected to the control device input and the counter input, whose outputs are connected to the multiplexer information inputs, controlling the inputs of which are connected to the control inputs of the control device 2.

The disadvantage of such a control device is the relatively low control accuracy.

The purpose of the invention is to increase the reliability of the control.

The goal is achieved

To the fact that the control device contains a counter, a multiplexer, a trigger, an inverter and a coincidence element, the first input of which is connected to the inverter output, and the first input of the triangle is connected to the input of the control device and the counter input, the outputs of which are connected to the information ones. multiplexer inputs that control

Claims (1)

The 20 inputs of which are connected to the control inputs of the monitoring device, a delay element is inserted, the input of which is connected to the multiplex output and the input of the inverter, and the output of the delay element is connected to the BTQ input of the coincidence element, the output of which is connected to the second input of the trigger. FIG. 1 shows a block diagram of the control device; in fig. 2 timing diagrams explaining the operation of the device. The control device contains multiplexer 1, inverter 2, delay element 3, element, coincidence 4, trigger 5 and counter 6. The first input of the coincidence element 4 is connected to the output of inverter 2, and the first input of the ground 5 is connected to the input 7 of the control devices and the counter input 6, the information outputs of which are connected to the inputs of multiplexer 1, the control inputs of which are connected to the control inputs 8 of the control device, and the input of the delay element 3 are connected to the output of the multiplexer 1 and the input of the inverter 2, the output of the delay element 3 is connected to the second Odom matcher k element whose output is connected to the second input of flip-flop 5. Arrange a timing diagram of the control-OPERATION (FIG 2.) include account pulses of the inlet 9 7 6 controlled by the counter; pulses 10–12, which start from the first second and third bits of the controlled counter 6, respectively, 10 pulses 13 at the output of the multiplexer 1, with a code dialed on its control inputs, ensuring the passage of a pulse from the second discharge of the controlled counter 6; pulses 14 at the output of the inverter 2; pulses 15 at the output of the delay element 3; impulse 1b at the output of the element k; the pulses 17 at the output of the trigger 5. The control device operates as follows. Depending on the code at the control inputs of multiplexer 1, a signal from the output of one of the bits of the controlled counter 6, which is the oldest bit of the controlled ones, passes through its output. At the time when the controlled bits of the counter 6 are in the unit state at the output of the multiplexer there is a single logical signal. With the arrival of the next counting 3 pulse at the output of the corresponding bits of the controlled counter 6, a transition from single logical signals to zero occurs. The corresponding logical signal difference also appears at the output of multiplexer 1, with the most significant bit of the controlled counter 6 going from a single logical state to zero when all the least significant bits in relation to it also go from a single state to zero. The zero logical signal from the output and multiplexer 1 is fed to one input of match 1 element through inverter 2, and to another input of this element matches 4 through delay 3 element. As a result, at the moment of switching the output signal of multiplexer 1, coincidence k occurs at inputs logic signals, and at the output a pulse is formed, the duration of which is determined by the delay value specified by the delaying element 3. This pulse arrives at the setup input of the trigger 5 and switches this trigger , and from the output of the trigger 5, a signal is taken, indicating that the controlled bits of the counter, the number of which is registered by the code on the inputs 8, are -; c in the zero state. The trigger 5 returns to the initial state by a subsequent counting pulse arriving at the other set input of the trigger 5 when the zero of the monitored output code is violated. For example, for the case when the number of controlled; bits equal to two, as can be seen from the timing diagram 17 (figure 2), the pulse at the output of the trigger 5. is, when the output signal of these two bits controlled by the counter 6 is zero. Thus, the monitoring device allows you to accurately determine the moment when the output signals are equal to zero for a specified number of counter bits. Claims A control device comprising a counter, a multiplexer, a trigger, an inverter, and a match element, the first