SU744996A1 - Frequency divider by four, five - Google Patents

Description

(54) THE FREQUENCY DIVIDER ON THE NO. The invention relates to automation and computer technology and can be used in devices where it is necessary to divide a sequence of pulses into four, five. Known frequency dividers made on logic elements, which g & lt a sequence of pulses by four, five W, I. The first of the known devices contains bits, each of which is made on a memory trigger, a switching trigger and a SC element. However, it has A large number of equipment and has low reliability. The second of the known devices is selected as a prototype. It contains four bits, each of which consists of a memory trigger, a switching trigger and an NAND circuit, and in each of the first three bits a single memory trigger output is connected to a single switching trigger ncoflOM, the zero output of which is connected with a single input of the memory trigger of the given bit, with zero inputs of the memory triggers and switching triggers of all previous bits and with the input of the AND –– circuit of the previous bit, the single output of the switching trigger of the first bit is connected to the input of the AND circuit -NOT of this bit, the output of which is connected to both inputs of the switching second bit, and the single output of the switching trigger of the second bit — to the input of the AND-NOT circuit of this bit, whose output is connected to both inputs of the third-level switching Tpinrepa and - input A fourth-bit NAND circuit, the fourth-digit NAND circuit output is connected to a single memory trigger input of this bit, the zero input of which is connected to the fourth digit switching trigger output and the clock signal with zero inputs. The switching triggers of the first three bits, with the input of the NAND circuit, and with the single input of the switching trigger of the fourth bit.

However, the known device has been installed on a large amount of equipment, since the fourth bit contains an additional AND-NOT element, except for organizing the division of frequency into 4, 5, at least four more AND-NOT elements with a large number of inter-operative connections are required. This significantly reduces the overall reliability of the device.

The aim of the invention is to improve the reliability of the device.

This is achieved by the fact that in the frequency divider by four, it contains the output. the NAND element and four bits, each of which consists of a switching trigger, a memory trigger,: executed on 14-NO terminators connected non-wisely, and an NAND element, and in each of the first three bits a single trigger output of the memory This is connected to the single input of the switching trigger, the zero output of which is associated with the single input of the memory trigger of this bit, with the zero input of the memory trigger and with the zero switch of the previous bit, the single output of the switching trigger of the first time p Yes, it is connected to the input of an element of this bit, the output of which is connected to the zero and single switching switching trigger of the second discharge, the single switching output of the south trigger of the second discharge — to the input of the element

 of this bit, the output of which is connected to the zero and single inputs of the € 3 mutational trigger of the third bit and to the input of the AND-NO-4th element of the bit that is connected to

the single trigger input of this bit, the zero time of which is connected to the single output of the fourth switching bit, and the clock of the clock signal is connected to the zero inputs of the first three bit of the switching triggers, and the element I.NE and to the single input of the first three bits of the triggered the fourth bit trigger, the third bit NAND element inputs are connected to the NAND element outputs and the fourth bit memory trigger output, and the output to the NAND output element input, with zero memory trigger inputs first output bits and with a zero input of a fourth-stage trigger, a single output is connected to the zero start of a first-bit switching trigger, the third output of a third-order switching trigger is connected to the input of a fourth-bit I-HFZ element, the input of the output element is NAND and with zero memory trigger trigger and switching trigger of the first bit, and the single output of the memory trigger of the third digit is supplied to the input of the NAND element of the fourth bit.

The drawing shows a structural electrical frequency divider circuit by four, five.

The device contains a bus 1 clock. Pulses, elements AND-NOT 2 and 3, 4 and 5, 6 and 7, 8 and 9, forming, switching triggers of the first to fourth bits of the elements AND-NOT, 10, 11, 12, 13 of these times of rows, AND-HE elements 14 and 15, 16 and 17 18 and 19, 2О and 21, which form the memory triggers of these bits, output element 22, output bus 23.

The device works as follows.

In the initial position, the memory triggers of all bits are in the zero state, and the clock signal, which is thrown on bar 1, is absent (equal to the logical zero), in this case, at the output of the elements IT ™ HE 9, 11, S, 20, 18. 16,, 14 and on the bus 23 - a logical zero, at the outputs of the remaining elements AND IS NOT a logical one. With the arrival of the first clock pulse, the element I-liE 3s opens at its output by an on / off signal equal to a logical zero, which sets the bit memory trigger to a single state. After the clocking pulse expires, the signal that equals the logical zero appears at the output of the NAND 12 element, and the signal equal to the logical one is output at the output of the element 10. Therefore, with the arrival of the second test pulse, the AND-NE 5 element is opened, the Signal is equal to a logical zero, from the output of this element sets the second-bit memory trigger to the single state, and the first-bit memory trigger is set to zero . The presence of connections from the output of the NAND S element to the inputs of the i-Tape 4, 10, 3 elements prevents the appearance at the outputs of these elements of a logical zero in ms and a valid test signal when the memory triggers change. are their state

With the arrival of the third test pulse, a logical zero appears again at the output of element 3, set

memory trigger of the first discharge into single ones. After the clocking pulse expires, a signal equal to the pin unit appears at the output of the NAND element, therefore, the output of the NAND element 4 will be a signal equal to logical zero, and the output of the I4-HE 4 element will be a signal equal to unit. Therefore, with the arrival of the fourth clock pulse, a signal, increasing to a logical zero, appears at the output of the AND-HE element 7, which sets the memory triggers of the first and second bits to the zero state and which through the output element AND-NOT 22 enters to the busbar 23 .. The presence of connections from the output of the element AND-NOT 7 to the inputs of the elements AND-NOT 13, 16, 11, 5.3 again prevents the device from malfunctioning. With the arrival of the fifth clock pulse, only the AND element opens again. NOT 13, a first-bit memory trigger is set. Noe state.

Elements AND-NOT 8, 13, 7, 5 do not open, since the outputs of the elements AND-NOT 9, 11, 10 are logical zero. Similarly, with the arrival of the sixth tactic of the lean pulse, a logical zero appears at the output of the AND-NE element 5, sets the second-bit memory trigger to the single State, and the first-bit memory trigger to zero. With the arrival of the seventh clocking pulse, the first-bit memory trigger is again translated to a single state. After the termination of the action of the seventh clocking pulse and the output of the NAND 11 element, a signal equal to the logical one appears, and at the output of the NANDI element 6 a signal equal to the logical zero. Therefore, with the arrival of the eighth clocking pulse, a logical zero appears at the output of the NAND element 13, setting the fourth-bit memory trigger to one state.

After the expiration of the clocking impulse, a signal equal to a logical zero appears at the output of the NAND 12 element. which sets the triggers of the memory of the first three bits to the zero state and which through the output element IS-NOT 22 enters the output bus 23. With the arrival of the ninth clocking pulse, a logical zero is formed at the output of the element IS-NOT 8, translating the trigger of the fourth memory a discharge to the zero state, at the same time, at the output of the element IS-NOT 12, a signal equal to the logical one appears again and the device returns to its original position. The head connections from the output of the element AND-NE 8 to the input of the element AND-NOT 3 prevent the opening of this

element at the time of the action of the ninth clocking pulse.

Thus, on 9 input pulses, the device outputs two outputs, i.e. frequency is divided by 4, 5, and b) Ghodnye signals are formed at equal intervals of time.

Claims (1)

Invention Formula The frequency divider by four, five, containing the output element AND-NOT and four bits, each of which consists of a commutator trigger, memory trigger, performed on the cross-connect, the non-AND elements, and the AND-NOT element, and in each of the first three bits, the single output of the memory trigger is connected to the single input of the switching trigger, the zero output of which is connected to the single input of the memory trigger of this bit, to the zero input of the memory trigger and to the zero input of the previous trigger, e The switching output trigger of the first bit is connected to the input of the NAND element of this bit, the output of which is connected to the zero and single inputs of the switching trigger of the second bit, the single output of the switching trigger of the second bit is connected to the input of the NAND element of this bit The output of which is connected to the zero and single inputs of the switching trigger of the third discharge and to the input of the AND-NOT element of the fourfold discharge, the output of which is connected to the single input of the memory trigger of this discharge, zero in the stroke of which is connected to the unit output of the fourth-stage switching trigger, and the thickness of the signal T1 of the signal is connected to the zero inputs of the first three switching triggers, to the input of the NAND element and to the single input of the fourth-stage switching trigger, characterized in that increase the device operation, the inputs of the third-level NAND element are connected to the outputs of the NAND element and the single output of the fourth-bit memory trigger, and the output is connected to the axojaoM of the N-output element, with zero inputs of the trigger memory of the first three bits and zero input kc lmutatsio№