SU558405A1 - Divider by 5 - Google Patents

Description

the first trigger memory trigger house and the first commutation trigger trigger, the third discharge memory trigger output connected to the PI-NEM inputs of the first and second digits, zero output memory trigger of the second bit to the bullet input the first switching trigger, the other zero input of which is connected to the output of the NAND element of the third bit.

The drawing shows the electrical structure of the proposed divider.

The device contains elements 1–3 AND –NE, elements 4 and 5, 6 and 7, 8 and 9 AND –NE, which form, respectively, memory triggers of the first, second and third bits, elements 10 and AND, 12 and 13 AND – NE , forming switching triggers, input bus 14 and output bus 15.

The device works as follows.

In the initial state, the memory triggers of all bits are in the zero state, and the timing signal arriving at the input bus 14 is absent (equal to logical zero). In this case, the outputs of elements 2, 3, b, 8, 10, And 12, 13 will be a signal equal to the logical unit, the outputs of the remaining elements will be a signal equal to a logical zero. With the arrival of the first clock pulse, element 12 is opened and, at its output, a signal equal to a logical zero is set, which sets the first-bit memory trigger to one state. The presence of a connection from the output of element 12 to the input of element 13 prevents the output of element 13 of a signal that is equal to a logical zero in the moment of a clock signal. At the end of the clocking sigal, at the output of element 13, a signal equal to logical zero appears, and at the output of element 10, a signal equal to logical one. Therefore, with the arrival of the second clocking and. A pulse, a logical zero appears at the output of element 2, which sets the second-bit memory trigger to the one state, and the nerve-trigger trigger to the zero state. The presence of connections from the output of element 2 to the inputs of elements 10 and 3 prevents the appearance at the outputs of these elements of a signal equal to a logical zero at the instant of the clock signal. After the end of the second clock pulse, at the output of element 10 a sigal appears equal to a logical zero, and therefore, with the arrival of the third clock pulse, logic zero is at the output of element 3, setting the third bit trigger to a single state. A signal equal to a logical zero from the zero output of the third-bit memory trigger (element 8) sets to the zero state the second-bit us trigger. The presence of a connection from the output of element 3 to the inputs of elements 7 and 12 prevents the appearance of the logical zero at the outputs of these circuits at the instant of operation of the clocked signal. With the arrival of the fourth clock pulse, element 12 opens, setting the first bit memory trigger to one state. Upon termination of the clocking imiuls, the element 11, which is prepared to operate, appears, and since the outputs of elements 1 and 10 are a logical unit. Consequently, with the arrival of that clock pulse at the output

element And there is a signal equal to a logical zero, which arrives at the output spindle 15 and returns the circuit to the initial state, setting the triggers of the nerve and the third bit to the zero state.

Thus, for five input pulses, the circuit outputs one output pulse, i.e., divides by 5.

Claims (1)

Invention Formula The divisor by 5, containing three bits, each of which contains a memory trigger and the NAND element, and switching triggers, with the input input of the first switching trigger, the zero input of the second switching trigger, and the inputs of the NAND elements of the second and the third bit, the unit output of the first switching trigger is connected to the zero input of the memory trigger of the first bit and to the zero input of the second switching trigger, the unit output of which is connected with a zero input of a nerve switching trigger, and a zero output with a single input trigger of the memory of the first bit, whose single output is connected to the single input of the second switching trigger, with In this case, the output of the second-level NAND element is connected to the input of the third-level NAND element and to the single trigger input of the second bit, the single output of which is connected to the input of the NAND element the third bit, the output of which is connected to the single inputs of the trigger us and the second and third bits, and the zero output of the memory trigger of the third bit is connected to the zero output of the second memory trigger, characterized in that in order to improve the reliability of the device , the output of the first-stage NAND cell is connected to the single input of the first switching trigger, whose single output connected to the inputs of the AND-NOT elements of the first and second bits and to the zero input of the trigger for us of the third discharge, and the zero output to the second AND-NOT element of the second discharge, the output of which is connected to zero the memory trigger input of the first bit and the hinge input of the first switching rigger, while the zero memory trigger output of the third bit is connected to the inputs of the NAND elements of the first and second bits, the second output trigger memory trigger is set to the zero input of the first switching trigger, the other zero input is connected to the output of the third-level AND-NO element.