SU621092A1 - Decoder for boaz-czoadhuri-hockwingem codes - Google Patents

Description

(54) DECODING DEVICE OF CODES OF BOUS - CHOWDHURY - HOKWINGHEM

The invention relates to radio engineering and can be used in amplifiers for determining and correcting errors.

Known decoding device

The Bousa-Chaudhuri-Hokvingema (BCH) codec contains the memory input register, the bit outputs of which are connected to the inputs of the corresponding blocks of calibration combinations, as well as ft of the signal conditioners about the impossibility of making a reliable decision and W memory blocks (P-number of the input bits memory register) LlJ.

However, the known device is characterized by a limited b {1 action and a large number of elements for the circuit implementation, as well as the impossibility of applying codes with a large number of bits.

The purpose of the invention is to increase speed.

To do this, the decoding device of the BCH codes contains the input memory register, the bits of which are

connected to the inputs of the corresponding blocks of calibration combinations, as well as H signal conditioners about the impossibility of making a reliable decision AND AND memory blocks (AND the number of bits of the input memory register $ 1), a summing matrix and two comparators are entered for each bit The output of the block of calibration combinations of each discharge is connected via a summed matrix to the direct input of the first comparator and to the inverse input of the second comparator, and the outputs of the first and second comparators are connected to the corresponding inputs of the pa block ti shaper and the impossibility signal is received five authenticity decision, and on the other inputs of the first and second comparators filed iapr51zhenie reference.

The drawing shows the structural electrical circuit of the proposed device.

The decoding device of the BCH codes contains the input register of the 1 memory, the outputs of the bits of which are connected to the inputs of the corresponding blocks of 2 calibration kits, and also the tt form and TV signals about the impossibility of making a reliable decision and I of 4 memory blocks (H is the number of bits Dov input register memory 1). The device also contains, for each bit, a summing matrix 5 and two comparators 6 and 7, while the output of block 2 of each bit through the summing matrix 5 is connected to the direct input of the first comparator b and to the inverse input of the second comparator 7, and the outputs of the first and second comparators 6 and 7 are connected to the corresponding inputs of the memory block 4 and the imaging unit 3, and a voltage reference is applied to the other inputs of the first and second comparators 6 И7.

The device works as follows.

From the output of each, the bit of the input register 1 of the memory, through the block 2 of the calibration combination, the information parcel arrives at the summing matrix 5, from the output of which the voltage is applied to the inputs of two comparators 6 and 7, to the other inputs of which the reference voltage is applied.

At the outputs of Comparators 6 and 7, a signal corresponding to 1 or O of the transmitted information bit appears, if the number of the corresponding calibration combinations prevails or the signal is absent with an equal number of calibration combinations corresponding to 1 or O of the transmitted information bit. If there is no signal at the outputs of the comparators 6 and 7, the previous value of the transmitted command is saved in the memory block 4, and the shaper 3 generates a signal that it is impossible to make a reliable (with a given probability of error) decision on the information being transmitted.

A pre-ordered masterwork allows you to increase speed by eliminating intermediate degrees of conversion {reducing the total number of required insert operations, and consequently, a significant reduction in the element base).

F

the invention

about rmu l and

The Bousa Choudhury-Hokvingem (BCH) code decoder containing the memory input register, the bit outputs of which are connected, to the inputs of the corresponding blocks of calibration combinations, as well as the C formers of the signal about the impossibility of making a reliable solution and the P memory blocks (And bits of the input memory register), characterized in that, in order to increase. For each bit, a summing matrix and two comparators are introduced, the output of the block of calibration combinations of each bit is connected to the forward input of the first comparator and the inverse input of the second comparator through the summing matrix, and the outputs of the first and second comparator are connected to the corresponding inputs of the block the memory and the signal conditioner about the impossibility of making a reliable decision, and a voltage reference is applied to the other inputs of the first and second comparators.

Sources of information taken into account in the examination:

1. ABT opcTft6fc USSR certificate № 273516, cl. N OZ K 13/32, 1968.