SU598258A1 - Arrangement for correcting for errors in discrete information transmission systems - Google Patents

Description

The image-8 is related to the technology of information processing and can be used in the field of technology and systems for transmitting information from the backward LINK; & also in one-way systems with erasing messages ,,.

A device for correcting errors in discrete information transfer systems is known, which contains an analysis node, a buffer memory node, a register, and a shift ij. In this device, the detection of errors in one code word causes the erasure of this and a fixed number of preceding code words,

The closest technical solution to this invention is a device for correcting errors in discrete information transmission systems, comprising an analysis node whose input is an input

device, a buffer memory node, the code of which is connected to the first input of the AND element, the first shift register, the bit outputs of which are connected to the inputs of the element or, the output of the OR element is connected

with the second input of the AND element whose output is the output of device 2,

In known devices, they analyze for compliance with the test conditions / tl of preceding and subsequent codewords, the reliability of which determines the reliability of the JU + 1th code word.

A disadvantage of the known devices is false false-guards (i.e., erasing correctly received code words, or erasing code words received with detected errors to correct which the coding redundancy is sufficient) resulting from the lack of correction of detected errors and the fact that that regardless of the channel condition, the detection of an error in one codeword automatically leads to the sequential erasure of the preceding and / J of the subsequent codewords. This ultimately leads to under utilization of the capacity of the communication channel, which is in a state with a relatively low error rate. The chain of the invention is to increase the throughput efficiency by reducing the likelihood of spurious. erasures in the process of receiving code words. The response is achieved by introducing a correction node into the proposed device V, a second shift register and a threshold node, with the information and control outputs of the analysis node connected to the inputs of the correction node, the KOTopord output connected to the output of the buffer memory node, control outputs The analysis node is connected to the input of the second shift register, the bit outputs of which are connected to the inputs of the threshold node, which is connected to the input of the first shift register. The proposed device uses the fact that in non-uniform channels (channels with memory) the efficiency of using the channel capacity can be increased without significantly reducing the reliability by correcting single errors occurring in channel states with a relatively low error rate and erasing code words only in states with an increased error rate. In this case, the diagnostics of the channel conditions can be carried out according to the results of the analysis of the number of adjacent corrected code words, the code layer is output to the information receiver only under the condition that for any of Е the adjacent code words among the given, given and V consecutive code words are the corrected code SLO does not exceed the threshold value K. The drawing shows a block diagram of a device for correcting errors in discrete information transmission systems. The device contains analysis node 1, the input of which is simultaneously the input of the device, and the information output through correction node 2 and the buffer memory node 3 and tti of the bit words are connected to the input of the AND 4 element whose output is the output of the device. The control output of analysis node 1 is connected to the second (6-bit) shift register 5, the parallel output of which is connected to the multi-pass threshold node 6, and during the threshold node serves as the input of the first (J + V - 64-1) shift register 7, the parallel output of which is connected to the multi-input element IL 8, and its output is connected N to the input of the element And 4. The device operates as follows. The received L-bit code layer V is fed to the input of the analysis node 1, where it is analyzed for compliance with the test conditions. The code word from the output of the analysis node 1 is input character to the input of the correction node 2, while the information about the analysis result is in the form of a signal, if the code word does not match the test conditions, or the signal O, if the code word is satisfied with the test conditions, for a time not exceeding the half-cycle of the advancing frequency, it is entered from the control output of analysis node 1 into the second shift register 5 and on the correct input of the correction node 2. The information part of the code word entered into the correction node 2, and subjected to correction only in the case of a signal 1 coming from the control input, from the progress of the correction node 2 in the form of an m-bit word is sequentially (symbolically) written to the node of the buffer memory 3. The set of signals recorded in the second shift register 5, forming a set of potentials corresponding to the signals O and 1, determines the input state of the threshold node 6, the output of which produces signal 1 provided that 0 of its inputs more than K inputs have a potential of 1, or a signal of 0 is produced - otherwise. The signal generated at the output of the threshold node 6 is entered in the first shift register 7. The set of signals recorded in register 7, forming a set of potentials O and 1, determines the input state of the OR element. This t1-bit information word is spiked symbolically from the node of the buffer memory 3 under the advancing influence of the L-th subsequent information word, written to the node in the buffer memory 3, while this word enters through the element 4 and the output devices only if at its input, which is the output of the element OR 5, the potential O is present. Thus, this information word is output to the device output only when the number of corrected code words in all adjacent code layers wah among jU preceding, given and v subsequent coding words does not exceed the threshold value K. The proposed device allows to significantly increase the efficiency of loading non-uniform communication channels. Claims An apparatus for correcting errors in discrete information transmission systems.

containing the analysis node whose input is the input of the device, the buffer memory node whose output is connected to the first input of the AND element, the first shift register, the bit outputs of which are connected to the inputs of the OR element, the output of the OR element, and the output which is the output of the device, characterized in that, with a chain for improving the efficiency of the throughput, a correction node, a second register shifts and a threshold node are entered into the device, with the information and control inputs of the analysis node oedineny from the input correction unit, whose output is connected to the input node of the buffer memory zshravl yuschy analysis output node connected to the input of shift register sec, The discharge outputs of which are connected to the threshold input node, kotorog output coupled to an input of the first shift register.

Sources of Information taken into account in the examination;

1. USSR author's certificate NO 462296, cl, H 04 I. 1/10, 1972.

2. USSR author's certificate number 478447, cl. H O4 L 1710, 1973.