JPS61232726A - Error correcting device - Google Patents

Abstract

PURPOSE:To execute the rapid data transmission by providing a means to select the constitution of plural error correcting codes at the coder and the decoder respectively and having the means to inform the decoder of the quality of the communicating line. CONSTITUTION:When a selecting switch 5 is made into a mode 1, the address to output from an address generating circuit II of an input control part 1, an address generating circuit III of a coding processing part 2 and an address generating circuit VI of an output control part 3 which generate the higher order bit out of addresses from respective parts go to be effective, and the error correcting code is constituted on a buffer memory part 4. When the selecting switch 5 is made into a mode 2, address circuits II-VI go to be reset, and the error correcting code is constituted on the memory part 4. Even in the decoder, a selecting switch 10 is made into the mode 1 or the mode 2, the error correcting code is constituted on a buffer memory part 9, and the decoding processing is executed. Thus, the error correcting code to match with the quality of the communicating line can be selected and the rapid data are transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error correction device that uses an error correction code to correct code errors occurring on a digital code communication path.

2. Description of the Related Art Recently, with the development of digital signal communication technology, error correction devices have been widely used in fields such as digital VTRs and satellite communications. This error correction device includes the encoder shown in FIG. 5 and the decoder shown in FIG. 6, and uses the encoder and decoder as shown in FIG. Correct. below,
Figure 5.

A conventional error correction device will be explained using FIGS. 6 and 7.

FIG. 6 is a block diagram of an encoder, which is a device that adds an error correction code to input data and outputs the data.

In FIG. 6, 11 is an input control unit that writes input data sent from the transmitter into the buffer 7/memory 14;
Reference numeral 13 denotes an encoding processing unit that adds a correction code to the data on the backup memory 14, and an output control unit 13 that reads the encoded data from the buffer memory 14 and outputs the encoded data.

The buffer memory 14 stores input data until it is encoded and output.

For example, the code shown in FIG. 3 is constructed by the encoder constructed in this manner.

On the other hand, FIG. 6 is a block diagram of a decoder, which corrects errors occurring on the communication path based on the multiplication code formed by the encoder, and outputs data before being encoded.

In FIG. 6, 15 is an input control unit that writes input data to the buffer memory 18, and 16 is the buffer memory 18.
1 for correcting the code in Figure 3 constructed with the above encoder.
A decoding processing section 17 performs decoding processing as a unit, and numeral 17 is an output control section that reads the decoded data from the buffer memory 18 and outputs the data. In addition, the buffer
The memory 18 stores the input data until it is decoded and output.

Next, the structure of the error correction code shown in FIG. 3 will be explained. For example, this code structure is
Volume No. 7 (1981), “Digital VTR Error Correction,”
The configuration described in "Modification method" is known. In this configuration, the outer code is configured at two inner code rows per row,
Both inner code and outer code check points are given by simple parity.

For example, the check point SB6° of the inner code is SB +SB +...+SB, :5B32
Also, if the outer code check points SB2, 3 are SB +SB +...+SB =SB9
93. Error correction in this code is performed by first detecting code errors in subblock units using the error detection code added to each subblock SBn. If the number of subblocks in which code errors are detected is one per row or column, correction is performed by adding error pattern E to the erroneous subblock. Here, the incorrect turn E is, for example, E = SB + SB +...+5B3
2. After correction using the inner code, correction using the outer code is performed. When this code configuration is used, burst errors over 91 lines can be corrected by correction using the outer code.

Problems to be Solved by the Invention However, the error correction device using the above code structure has its own problems. In other words, increasing the number of bits constituting an error correction code increases the length that can be corrected as a burst error, but the encoding process in the encoder and decoding in the decoder per configuration of one error correction code increases. Since the time required for the conversion process increases, the delay time in transmission due to the use of the error correction device increases, and prompt data transmission cannot be performed. Further, if the number of bits constituting the error correction code is reduced, the transmission delay time is reduced, but long burst errors cannot be corrected. Therefore, if only one type of error correction code is fixed, if the quality of the communication line changes, uncorrectable errors will occur frequently, or the transmission time will be long even though the transmission delay time can be shortened. In either case, rapid data transmission cannot be performed.

The present invention solves the above problem by making it possible to select the type of error correction code according to changes in the quality of the communication line, thereby minimizing transmission delays that occur when using an error correction device. This allows for rapid data transmission.

Means for Solving the Problems The present invention provides means for selecting a plurality of error correction code configurations in each of the encoder and decoder, and also provides means for informing the decoder of the quality of the communication line. This is intended to achieve the above objectives.

Operation The present invention is configured with an encoder according to the above configuration, and the type of error correction code to be decoded by the decoder is selected in accordance with the quality of the communication line.

Embodiment FIG. 1 is a block diagram of an encoder of an error correction apparatus in an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an input control section that writes input data to a buffer memory section 4. As shown in FIG. Reference numeral 2 denotes an encoding processing unit that encodes the data on the buffer memory unit 4, and 3 represents an output control unit that reads the encoded data from the buffer memory unit 4 and outputs the data. Note that the buffer memory unit 4 stores the data until it encodes the input data and outputs it. 5 is a selection switch for selecting an error correction code.

The operation of the above configuration will be explained below.

The address generation circuit ■ of the input control section 1, the address generation circuit ■ of the encoding processing section 2, and the address generation circuit ■ of the output control section 3 each generate the upper 2 bits of the 17-bit address from each section. I am doing it. therefore,
When the selection switch 6 is set to mode 1, the addresses output from the address generation circuit ■ of the input control section 1, the address generation circuit ■ of the encoding processing section 2, and the address generation circuit ■ of the output control section 3 are in a valid state. An error correction code can be constructed on the buffer memory section 4 as shown in FIG. Also, when the selection switch 5 is set to mode 2,
Address circuit ■, address circuit ■, and address circuit ■ are each in a reset state, and the address from each part is 15.
Since only the pit changes, as a result, an error correction code as shown in FIG. 4 is constructed on the buffer memory section 4.

FIG. 2 is a block diagram of a decoder of an error correction device in one embodiment of the present invention. In FIG. 2, reference numeral 6 denotes an input control section for writing input data into the buffer memory section 9.

7 is a decoding processing unit that decodes the data on the buffer memory unit 9; 8 is an output control unit that reads out the data on the buffer memory unit 9 adjacent to the decoding north and outputs the data.

The buffer memory unit 9 stores the input data until it is decoded and output. 1o is a selection switch for selecting the configuration of the error correction code.

7-b' is an alarm lamp that lights up when an error that cannot be corrected by the decoder occurs, and is used to notify the quality of the communication line.

In the above decoder, similarly to the above encoder, if the selection switch 10 is set to mode 1, the error correction code shown in FIG. 9, and decoding processing is performed. Therefore, when the encoder and decoder selection switches are set to mode 1X, the number of bits constituting the error correction code is large, so the transmission delay is large, but the burst error length that can be corrected becomes long. On the other hand, in mode 2, the number of pits constituting the error correction code is reduced to %, so the transmission delay is reduced to columns, but the correctable burst error length is reduced to μ. As a result, if long burst errors that cause the alarm lamp to light up often occur in mode 2, set the selection switch 4 to mode 1, and in mode 1, long burst errors that cause the alarm lamp to not light up for a while will hardly occur. In the communication path, by setting the selection switch to mode 2, rapid data transmission with little transmission delay can be performed. Note that a counter may be provided in place of the alarm lamp 7-1, and the selection switch 10 may be automatically switched in accordance with the number of counts of the counter within a certain period of time. However, if the count of the counter does not satisfy the threshold within a certain period of time, the selection switch 10 is switched again.

Effects of the Invention As described above, the present invention provides an encoder having means for configuring a plurality of error correction codes and selecting the type of the error correction code;
A decoder that can decode a plurality of error correction codes configured by the encoder, has a means for selecting the type of error correction code, and also has a means for knowing the quality of the communication line. , it is possible to select an error correction code that matches the quality of the communication line, and as a result, compared to an error correction device that can only configure one error correction code, data can be transmitted more quickly, which is highly effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encoder of an error correction device in an embodiment of the present invention, FIG. 2 is a block diagram of a decoder of an error correction device in an embodiment of the present invention, and FIG. 3 is a block diagram of a decoder of an error correction device in an embodiment of the present invention. 4 is a diagram showing the second error correction code of the present invention, FIG. 5 is a block diagram of the encoder of the conventional error correction device, and FIG. 6 is the conventional error correction code. Block diagram of a decoder of the apparatus. FIG. 7 is a block diagram of an error correction apparatus consisting of an encoder and a decoder. 16. , . . . input control section, 2 . . . encoding processing section, 3 . . . 00. Output control section, 4...Buffer memory section, 5...Selection switch, 6...
...Input control section, 7...Decoding processing section, 7-
1... Alarm lamp, 8... Output control section, 9... Buffer memory section, 1o...
... Selection switch, 11 ... Input control section, 1
2... Encoding processing unit, 13... Output control unit, 14... Buffer memory, 15...
...Input control section, 16...Decoding processing section, 1
7... Output control unit, 18... Buffer memory. Name of agent: Patent attorney Toshio Nakao 3rd person
figure

Claims (2)

[Claims] (1) Encoding means on the transmission side that generates a plurality of error correction codes, selects the error correction codes, and adds them to the transmission information; and An error correction device comprising a receiving side decoding means for decoding transmission information sent via a communication line. (2) The error correction device according to claim 1, wherein the type of error correction code to be decoded by the decoding means is selected depending on the quality of the communication line.