SU1580559A1 - Device for coding and decoding information - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the speed of the device. The device multiplies the input code signal (vector) by the signal (matrix) stored in memory block 4, which allows using the device in information transmission systems to record the error signal. The device for encoding and decoding information contains a program-time block 1, performed on a clock synchronization element 2, a frame synchronization element 3 and a pulse distributor 4, a permanent memory block 5, blocks 6, 8, 10 AND elements, shift registers 7, 11 and block 9 triggers. 1 il.

Description

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The invention relates to telecommunications and can be used in discrete information transmission systems to decorrelate an interfering signal.

The aim of the invention is to improve the speed of the device.

The drawing shows a block diagram of the proposed device.

The device contains a software-time unit 1, performed on a clock synchronization element 2, a frame synchronization element 3 and a pulse distributor 4, a permanent memory block 5, a second block 6 of And elements, a first shift register 7, a first block of 8 And elements, a block 9 flip-flops, the third block of 10 And elements and the shift register 11.

The device works as follows.

When an n-bit codeword arrives at the device input by a signal at the beginning of a word, a parallel transfer of the master vector code from block 5 through block b to register 7 is allowed. At the control input of register 7, a shifting sync pulse starts to arrive at the control input of register 7 the clock shift of the contents of register 7 by one bit to the right and parallel rewriting of the contents of register 7 through block 8 to block 9 only for a single value of the next character of the code word. In block 9, bitwise modulo 2 is added to the register register 7 and block 9, i.e. the code word vector is multiplied by the matrix, the rows of which are the successive states of register 7 on each clock cycle. When a signal arrives The end of the code word to the second input of block 10 is allowed to parallel rewrite the contents of block 9 through block 10

register 11, from which the transformed code is fed to the output of the device using read sync pulses.

Since the conversion is carried out in the process of downloading the code word to the input of the device, there is no delay in the conversion, which improves the speed of the device.

Claims (1)

Invention Formula 5 A device for encoding and decoding information, comprising a software / time block, the input of which is the input of the device, a memory block, first, second registers, 0, the outputs of the first register are connected to the corresponding first inputs of the first block of elements AND, characterized in that, in order to increase the speed of the device, 5 he entered the second, third blocks And elements and a block of triggers, the outputs of the memory block are connected to the corresponding first inputs of the second block of elements And whose outputs are connected to the corresponding information inputs of the first register, the second input of the first block of elements And connected to the input of the device, the outputs of the first block of elements And are connected 5 through the trigger block with the corresponding first inputs of the third block of elements And whose outputs are connected to the corresponding information inputs of the second register, the first Q the fourth outputs of the program-time block are connected respectively to the second inputs of the second and third blocks of the elements And and the control inputs of the first and second registers , 5, the output of the second register is the output of the device.