SU1399894A1 - Coder - Google Patents

Abstract

The invention relates to telecommunications and can be used in information transmission systems for encoding an inverse code. The invention makes it possible to increase the speed of the encoder by parallelly forming the information and check bits of a code combination. The encoder contains a drive 1, drivers 2, 8 pulses, elements AND 3.6, element OR 4, distributors 5, 12 pulses, trigger 7, adder 9 and registers 10, 11. 1 Il.

Description

WITH

with so

00

from 4

The invention relates to telecommunications and can be used in data transmission systems for encoding an inverse code.

The aim of the invention is to increase the speed of the encoder.

The drawing shows the functional diagram of the encoder.

The encoder contains a drive 1, the first driver 2 pulses, the first element AND 3, the element OR 4, the first distributor 5 pulses, the second element AND 6, the counting trigger 7, the second driver 8 pulses, adder 9 modulo two, the second buffer register 10, the first ring register 11 shift and the second distributor 12 pulses.

The encoder works as follows.

I

Information consisting of k symbols is simultaneously entered in parallel code into the drive 1 and the ring shift register 11. From accumulator 1, information is fed to the inputs of the driver of 2 pulses, respectively, from the k two-input AND elements and the k-input OR element. The other inputs of the imaging unit 2 alternately receive pulses from the corresponding outputs of the distributor 5. Under the action of the first k pulses of the distributor 5, the information symbols of the code combination from the output of the imager 2 arrive at the output of the device through the elements AND 3 and OR 4. At the same time, the second input element And 3 with the second output of the distributor 5 receives the enable signal, and the second input element And 6 with the third output of the distributor 5 receives the inhibit signal.

The check matrix of the inverse code has the following form:

011 ... 1100 ... About

1 o 1

. 1 about 1 about ... about

n

()

eleven

1 o o o o ... o 1 50

It is obvious that the i-th checking symbol of an inverse code combination is equal to the modulo sum of all two information symbols, except for i-ro.

When writing information consisting of k characters, in the register 11 the information bits of the code combination,,

.

g 5

0

5 Q

five

five

0

five

with the exception of the first one, they are received at the inputs of the adder 9 modulo two, at the output of which a signal appears that corresponds to the first verification symbol of the code. This signal at the zero step of the distributor 12 is recorded in the first memory cell of the buffer re-. gistra 10. Under the action of the first pulse from the output of the trigger 7 in the register 11, information is shifted by one bit to the right and at the same time the distributor 12 moves to the next position. Thus, due to the cyclic properties of the inverse code, the signal corresponding to the second check bit from the output of the adder 9 in the first step of the distributor 12 is recorded in the next register memory cell 10, etc.

At the end of the first k pulses of the distributor 5, a prohibitive signal is applied to the second input of the element And 3, and a second signal is given to the second input of the element 6. Under the action of the second k pulses of the distributor 5, the check symbols of the code combination recorded in register 10 through the driver 8, the elements AND 6 and OR 4 are output to the output of the encoder.

The performance of the proposed coder is achieved by the parallel formation of information and check bits of a code combination. By the time of the output of the 2k-1 element of the code combination at the output of the encoder, the last verification element of the code must be written in register 10.

Claims (1)

Invention Formula An encoder containing a drive whose inputs are encoder information inputs, a first pulse distributor whose first outputs and accumulator outputs are connected respectively to the same first and second inputs of the first pulse generator, a trigger and an OR element whose output is an encoder output that differs By the fact that, in order to increase the speed of the encoder, an adder, registers, a second pulse driver, a second pulse distributor, and AND elements are entered into it, and the output of the first pulse generator pulses connected to the first input of the first ele313998944 And, the output of which is connected with the same-named control inputs to the first input of the OR element of the second register, the outputs of which the trigger and the first distributor are connected to the same first input pulses are combined and are syndes of the second pulse driver that chronizes the input of the encoder, the output of the second inputs are connected A trigger is connected to a clock-input of the same name, the first outputs of the first first register and the input of the second pulse distributor, the output of the second pulse distributor, the information pho The pulse loudspeaker connectors of the first register are connected with the first input of the second element to the same name information input AND, the output of which is connected to the encoder's drones, the outputs of the first register-second input of the OR element, the second and connected to the same-named inputs of the third distributor of the totalizer , the outputs of the adder and second-pulses are connected to the second input pulse distributor connected to the first and second respectively to the information and elements I.