SU1651293A1 - Digital data link simulator - Google Patents

Abstract

The invention relates to computing and can be used for statistical modeling of discrete communication channels. The purpose of the invention is to expand the functionality by simulating a communication channel with quantization of the output signal. For this, a clock counter, a trigger, three AND elements, an NOT element, a clock generator and a delay line are entered into the simulator. With the input of the simulator symbols 0 or 1, these elements allow the method of statistical testing to bring about the appearance of symbols 07 on the simulator output, depending on the values of the transient probabilities stored in the intermediate memory block. 1 il.

Description

The invention relates to computing and can be used for statistical modeling of discrete communication channels.

The purpose of the invention is to extend the functionality by simulating a communication channel with quantization of the output signal.

The drawing shows a diagram of a discrete communication channel simulator.

The discrete communication channel simulator contains a synchronization unit 1, a Markov sequence generator 2, an intermediate memory block 3, a threshold adder 4, a random number generator 5, the first element And 6, a 7 clock counter, a trigger 8, the second element And 9, the third element And 10, the element is NOT 11, the delay line 12, the 13 clock pulse generator and the fourth And 14 element.

The discrete channel simulator operates as follows.

External sync pulses are supplied to the first input of the synchronization unit 1, which accompany the information symbols arriving at the first and second inputs of the trigger 8. Block 1 generates a signal that arrives at the simulator sync pulse input and triggers the random number generator, closes the 7 clock count, stops the 13 clock generator pulses and the trigger generator 2 Markov sequence. After the search for the state of the Markov circuit is completed, a signal appears at the second output of the generator 2, stopping the random number generator 5 and arriving at the input of the delay line 12, and from the generator 5 random number output, the second input of the adder 4 receives a random, evenly spaced out range from 0 to 1 number.

Intermediate memory block 3 is a 1x8 matrix of probabilities, where I is the number of chain states

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Yo

Os

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N Yu 00

Markov, and in each cell of the i-th row, where, l, the probability Pik is stored, where is the column number, and

 P (/ o)

is the sum of the probabilities of the transition of the symbol O into the symbols 0,1..k. From the first output of the Markov sequence generator 2, the first address input of block 3 receives the code I corresponding to the state number of the Markov circuit and the row number of the probability matrix of block 3, and the second address input of block 3 from counter 7 receives the code k of the probability matrix column number . At the first cycle, and from block 3 of the intermediate memory, the probability of equaling the symbol O to the symbol enters the first input of the adder 4.

0dl 1st state Markov chain.

The threshold adder 4 is an adder, the first output of which is a high-order carry signal, and the second output is its inverse. At the first output of adder 4, a signal appears when the sum of the numbers at the inputs of the adder is not less than one. Otherwise, from the second output of the threshold adder to the first input element And 14 receives the potential that allows the passage of clock pulses from the output of the generator 13 to the input of the counter 7 cycles. The clock generator 13 is triggered by a signal from the second generator output 3 of the Markov sequence and delayed by one clock in the delay line. The period of the clock pulses is equal to the time of selecting the probability value from block 3 and adding it to the value of a random number from generator 5.

Thus, on each clock cycle, the content of the clock counter increases by one, the next probability value is selected in block 3. its summation with a random number in block 4. This process continues until their sum is not less than one, and counter 7 it will store the code of the number k. From the second output of the adder 4, the resolving potential on the element And A ceases to flow, and on the first output of the adder 4 a signal appears that prepares the block

1 synchronization to the next cycle of the simulator and allowing the passage of code k from the output of the counter 7 cycles through the element 6 and the first inputs of the elements 9 and 10.

If the symbol O comes to the simulator input, the go potential from the second output of trigger 8 to the second input of element 10 enters and the code k passes through the element t / l 10 to the output of simulator. If the symbol 1 arrives at the information input of the simulator, then from the first trigger output 8

the resolving potential is fed to the second input of the element AND 9 and the code k through the element AND 9 is fed to the element HE 11, where each bit of the code is inverted and fed to the output of the simulator. So each

0, the information symbol 0 or 1, depending on the state of the Markov chain, the transition probabilities corresponding to the given state, and the value of the random number is matched by the number k or

5 k, corresponding to the number of probabilities search cycles from the row of the probability matrix such that the sum of this probability and a random number is not less than one. Here, k and k take integer values from 0 to 7.

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Claims (1)

Invention The discrete communication channel simulator containing a Markov sequence generator, an intermediate memory block, 5 threshold adder, random number generator, the first element I, and the simulator clock input is connected to the start input of the Markov sequence generator, the first output of which is connected to the first address input of the intermediate memory block, the output of which is connected to the input of the first term of the adder threshold, the first output which is connected to the first input of the first element and then, and the input of the second term of the threshold adder is connected to the output of a random number generator, the stop input of which is connected to the second This is the output of the Markov sequence generator, which means that. In order to extend the functionality by simulating a communication channel with quantization of the output signal, a clock counter, a trigger, a second, third and fourth are entered into it. 5 And elements, delay lines, oscillator-to-pulses and the NO element, with the zero clock input input and the clock pulse stop input combined with the generator start input 0 random numbers and are connected to the input of the simulator clock, the second output of the threshold adder is connected to the first input of the fourth element And, the second input of which is connected to the output of the generator 5 clock pulses, the start input of which is connected to the output of the delay line, the input of which is connected to the second generator output of the Markov sequence, the output of the fourth element I is connected to the counting input of the clock counter, the output of which is connected to the second address input of the intermediate memory block and the second input of the first element And, the output of which is connected to the first inputs of the second and third elements I, the single output of the trigger is connected to the second input of the second element I, the output of which is connected to the information input of the element NOT, the output of which is connected to the output of the third element AND, is the output of the simulator, the second input of the third element AND is connected to the zero output of the trigger, the zero and single inputs of which are the information inputs of the simulator.