SU741322A1 - Shifting memory - Google Patents

Description

I

The invention relates to the field of automation and computer technology and can be used in arithmetic devices, control units, information control and processing devices.

There is an idle shifter 1 containing the main and auxiliary registers that are connected via recording gates, with the inverse output of each trigger of the auxiliary register connected to the control input of the recording trigger of the corresponding bit of each main register.

The closest in technical essence and structural diagram is device 2, which contains input and output registers, groups of input and output elements AND, a control unit. At the same time, the inputs of the shift unit are connected through the input register and the group of input elements I to the device inputs. The other inputs of the shift block are connected via the shift register to the external input device of the shift constants. The outputs of the shift block are connected through the output register and a group of output elements AND to the outputs of the device. Control inputs of the input and output groups 2

And are connected respectively to the first and second outputs of the control unit.

This device shifts only all initial information by a specified number of bits, while in a number of cases (for example, with full control of the transmission of multi-bit information in microprogramming control devices) it is necessary to shift only units (excluding zeros) information represented in binary code

10 that cannot be done in such a device and that is its disadvantage In addition, this device requires a number of clock cycles equal to the width (or double the size) of the initial information, which limits its speed.

15

The aim of the invention is to increase speed by allowing only units of the input binary code to be shifted.

The goal is achieved by the fact that in a shifting device containing an input register 20, one of the inputs of which is connected to the outputs of the first elements AND, one of the inputs of the first elements AND is connected to the inputs of the device, the other inputs of the first

elements And are connected to the first output of the control unit, the second output of which is connected to one of the inputs of the second elements And, the outputs of the second elements And connected to the outputs of the device, the other inputs of the second elements And connected to the outputs of the output register, the inputs of which are connected to the first outputs of the control unit information shifter, the first input of which is connected to the third output of the control unit, the second inputs of the information shift control unit are connected to the outputs of the input register, a bit code generator is introduced the input and the element ILINE, the inputs of which are connected to the outputs of the input register, the other inputs of the input register are connected to the outputs of the random reset code generator, the first inputs of which are connected to the second outputs of the information shift control unit, the second inputs of the random reset code generator are connected to the fourth output of the block control, the output of the element OR is NOT connected to one of the inputs of the second elements AND, the other inputs of which are connected to the third inputs of the information shift control unit.

The drawing shows a block diagram of the proposed shifting device. It contains the input register 1, the output register 2, the first elements AND 3, the second elements AND 4, the information shift control unit 5, the reset bit code generator 6, the control unit 7, the element OR-NE 8.

The control unit shift information 5 is made on the switches 9 and the elements OR 10, and the control unit 7 on the element And 11, the delay element 12 and the trigger 13. The shifter operates as follows.

Before starting work, an external device (not shown in the drawing) supplies a code (for example, a five-bit code 11001) to the inputs of the first And 3 elements that need to be converted (for example, all units to the right). Further, when an external pulse is applied, the Trigger Code 11001 through the And 3 elements is rewritten into the input register 1. At the same time, the outputs of the bit reset code generator 6 and the switches 9 are disabled. And the output register 2 is zeroed. After the impulse "Run through the delay element 12" triggers the trigger 13, which disables the element 11 and thus limits the impulse "Start on duration. After that, the outputs of the switches 9 are connected, which are all set to transfer information from the most senior to the next least significant bit, and only the zero-bit zeroing circuit of the bit-reset 6 code generator is connected, since the unit recorded for the first bit of the input register 1, closes all zero-bit patterns of the higher bits of the former 6. In this case, the signal recorded in the first, fourth and fifth bits of the input register 1, passed through one of the elements OR 10, is written to the low-order trigger of the output Registers 2, which connects through one of the switches 9 output of the second OR gate 10 to the input of the second trigger discharge output register 2. At the same time the first trigger discharge input register 1 is reset to zero, thereby providing a connection circuit

resetting the fourth bit of the driver 6. Then the signal recorded in the fourth and fifth bits of the input register 1 passes through the second element OR 10 and the corresponding switch 9 is written to the second bit trigger of the output register 2, which connects through the corresponding switch 9 output the third element OR 10 to the trigger input of the third bit of the output register 2. At the same time, the fourth bit trigger of the input register 1 is zeroed, thus connecting the zero bit circuit of the fifth bit worldr 6. Next, the signal recorded in the fifth digit of the input register I, passed through the third element OR 10 and the corresponding switch 9, is written into the third discharge trigger of the output register 2 and at the same time the trigger of that discharge of the input register 1 is zeroed In this case, all outputs of the input register 1 are formed with zeros, which characterizes the end of the information shift process. Null information from the outputs of the input register 1, passed through the element OR NOT 8, connects the elements AND 4, thereby ensuring the transmission to the output of the device of the transformed information: code 00111 instead of code 11001. In addition, the signal from the output of the element OR NOT 8 provides the operation trigger 13, thereby connecting the input “Starting to the input of elements I 3.

d The proposed shifter, in contrast to the known one, additionally introduces a bit reset code generator, the OR-NOT element and a number of new connections, as well as the shift register is excluded from it, which allowed only

5 units (without taking into account the zeros) of the code without external synchronization of the shear cycles, and which in turn allowed to increase the device performance, since the multi-cycle shear operation, which requires the number of cycles of equal width (or doubled bit) of the source code, is replaced by one-cycle (for external clock pulses).

Claims (1)

55 Formula of Invention A shifter containing an input register, one of the inputs of which