SU1208566A1 - Analog multiplier - Google Patents

Description

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The invention relates to electrical computing devices and can be used in analogue computing machines.

The purpose of the invention is to improve the accuracy of work.

The drawing shows a functional diagram of an analog blade driver.

The analog multiplier contains the first 1 and second 2 operational amplifiers, the first and second elements with controlled conductivity, made on field-effect transistors 3 and 4, the source 5 of the bias voltage, the first 6, the second 7, the third 8, the fourth 9, the fifth 10, sixth; And, the seventh 12, the eighth 13 and the ninth 14 scale resistors, the bus 15 of zero potential, the first 16 and the second 17 inputs and output 18.

Analog multiplier works as follows.

The multiplier signal from input 17 is applied to the gate of the second field-effect transistor 4. An additional bias voltage is applied to the gate of this same transistor, designed to ensure operation at both positive and negative values of the signal multiplier from input 17.

When the voltage across the gate of the second field-effect transistor 4 changes, the conductivity of its channel changes, as a result of which the transmission coefficient of the second operational amplifier 2 changes. Since the law of change in conductivity is close to the internal voltage, the transmission coefficient of the second operational amplifier also changes 2 Therefore, the output signal 18 is proportional to the signal of the multiplier from the input 17 and the signal from the output of the first operational S silitel 1, i.e. multiply output operation 085662 is performed

the first operational amplifier 1 to the signal multiplier from the input 17. When the ambient temperature changes, the conductivity of the second field-effect transistor 4 changes proportionally 5, which leads to a temperature error in the multiplication operation. To reduce the influence of temperature signal multiplier

 O from the input 16 passes through the first operational amplifier 1 and a divider with the first field-effect transistor 3, which performs compensating functions, which allows, in accordance with the change in conductivity of the first field-effect transistor 3, respectively (in the opposite direction) to change the voltage at the output of the first operational one amplifier I, while maintaining the value of the signal at output 18, regardless of temperature. In the analog multiplier, the temperature error is compensated for when the ratio of the resistance values of the fifth scale resistor 10 and the resistance value of the second field-effect transistor 4, i.e., you can enter a sufficient feedback depth and, therefore,

30 to reduce the influence of the drift of the second operational amplifier 2 while maintaining sufficient temperature compensation.

The output voltage 18 is:

35

 - f-l UBx, U ,,,

where M is the proportionality coefficient;

Ugx, H Uexg are the voltage of the signal multipliers at inputs 17 and 16, respectively.

The proposed analog multiplier as compared to the prototype device has a higher accuracy of operation due to the compensation of temperature error.

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Editor A.Renin

Compiled by O.Otradnov

Tehred 3.Paly, Proofreader S.Shekmar

Order 289/58 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Branch PIP Patent, Uzhgorod, st. Project, 4

Claims (1)

ANALOG MULTIPLIERRON, containing the first and second operational amplifiers, the first and second elements with controlled conductivity, made respectively on the first and second field effect transistors, a bias voltage source, the first terminals of the first and second scale resistors are connected to the inverting input of the first operational amplifier, the second terminal of the second large-scale the resistor is connected to the zero potential bus, between the non-inverting input and the output of the first operational amplifier, a third large-scale resistor is turned on OP, the first output of the fourth scale resistor is connected to the non-inverting input of the first operational amplifier, the fifth scale resistor is connected between the inverting input and the output of the second operational amplifier, the first output of the sixth scale resistor is connected to the inverting input of the second operational amplifier, the non-inverting input of the second operational amplifier is connected to the first output seventh scale resistor, and through the eighth scale resistor connected to the zero potential bus, the sources of the first and orogo FETs connected to a bus ground potential, the ninth resistor scale of l and m chayuschiys I that, in order to increase the accuracy peremnozheniyal-drain of the first FET is connected to _a noninverting input of a first one- ® istration amplifier to the gate of the first transistor fawn the bias voltage source output is connected, the output of the first operational amplifier is connected to the second terminals of the first, sixth, and seventh scale resistors, the second terminal of the fourth scale resistor is the input of the multiplier multiplier signal and through the ninth scale resistor is connected to the inverting input of the second operational amplifier and to the drain of the second field effect transistor, the gate of which is the input of the second multiplier multiplier signal, the output of the second operational amplifier is the output of the multiplier. SU, „. 1208566> 208566