SU1497625A1 - Analog multiplier - Google Patents

Abstract

This invention relates to electrical computing devices and can be used in analogue computing machines. The aim of the invention is to improve the accuracy. The analog multiplying device contains bias voltage source 1, first to fourth controlled field-effect transistors 2 ... 5, operational amplifier 6, bias resistor 7, zero potential bus 8, scale resistor 9, input 10 of the first signal multiplier, differential cascade 11, multiplying block 12, reference voltage source 13, adder 14, input 15 of the second signal multiplier, output 16. The operation of the device is based on the transmission of the first signal multiplier controlled by field-effect transistors 2 ... 5, and the conductivity of the channels the drain-source is controlled by a second signal multiplier. Partial compensation of the multiplication error is performed by summing with the signal of the multiplying block 12. 1 sludge.

Description

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This invention relates to; : 1 computational computational facilities and can be used on analogue computations}.

The aim of the invention is noBbii.

The drawing shows the functional-} 1a diagram of the analog multiplying device.

The device contains a bias voltage source 1, first to fourth controllable field-effect transistors 2-5, operational amplifier 6, bias transistor 7, zero potential bus 8, scale resistor 9, input 10 of the first signal multiplier, differential cascade 1 multiplying the unit 12, the source 13 of the reference voltage, the adder 14, the input 15 of the second signal-somiojitol 15 and the output 16.

Analog duplicating device works as follows.

The gates of the controlled field-effect transistors 2-5 through the differential cascade 11 are supplied with linear combinations of the second signal-multiplier from the input 15 and the bias voltage from the source 1 of the bias voltage. The voltage of the first signal multiplier from the input 10 is applied to the sources of the third and fourth controlled field-effect transistors 4 and 5, which are formed together with the first and second controlled field-effect transistors 2 and 3 and are controlled by a voltage divider. The voltages from the drain of the first and second controlled field-effect transistors 2 and 3 are applied to the inverting and non-inverting inputs of the operational amplifier 6. The magnitudes of these voltages depend on both the magnitude of the first signal factor from input 10 and the ratio of the conductivities of the drain-source channels adjustable field-effect transistors. The conductivities of the drain - source channels are determined by the following factors: the input signal multiplier from input 15 and the output signal of operational amplifier 6.

The voltage at the output of the operational amplifier 6 under the condition that the parameters of controlled field-effect transistors 2-5 are identical, is proportional to the product of the first and second sets of multipliers from inputs 10 and 15. The proportionality factor depends on the specific slope of the controlled factors.

left transistors, which changes under the action of destabilizing factors. Consequently, the result of the product depends on the stability of the number of proportional factors.

The multiplying unit 12 performs a proportional multiplication of the signal from the output 16 and a negative value of the signal from the output of the source 13 of the reference voltage with a certain coefficient. Controlled field-effect transistors 2-5, operational amplifier 6, and differential stage I1 form a multiplying node.

The adder 14 performs the summation of the signals at its inputs. As a result, a signal is generated at the output 16, which, taking into account the selection of the same parameters of the multiplying node and the multiplying block 12, can be written as

one ..

V

its

V

(1 +

on

-))

0

five

0

five

0

five

where V is the voltage source 13 reference signal;

and - the relative error of the transmission coefficient of the multiplying block 12 (multiplying node);

P, and - voltage of the first and second signal-factors c, inputs 10 and 15;

K - transfer coefficient of the multiplying block 12 (multiplying node),

Nz expression (1) it follows that the relative error of multiplication is reduced by a factor of 1, which improves the accuracy of the device.

Claims (1)

Invention Formula Analogue multiplying device containing the first, second, third and fourth elements with controlled conductivity, each of which is made on a field-effect transistor, operational amplifier, between the inverting input and the output of which a large-scale resistor is turned on, the non-inverting input of the operational amplifier is connected to the zero bus through a bias resistor potential, the sources of the first and second field-effect transistors are connected to the zero potential bus, the sources of the third and fourth field-effect transistors are connected between and are the input of the first signal factor of the device, the drains of the first and third field-effect transistors are connected to the inverting input of the operational amplifier, to the non-inverting input of which are connected to the currents of the second and fourth field-effect transistors, the differential stage, the first output of which is connected to the first and third the fourth field-effect transistors; the second output of the differential stage is connected to the gates of the second and third field-effect transistors; the first signal input of the differential stage is with the input of the second signal factor of the device, the bias voltage source, characterized in that, in order to increase the accuracy, he introduced multiplying slo. 1: discharger and reference voltage source, -: P1- and: the output of the reference voltage source is connected to the first input of the multiplying block, to the Bropot-iy input of which the output of the adder is connected, the output of the bias voltage source is connected the cascade and the control input of the conversion ratio of the multiplying block, the output of which is connected to the first input of the adder, the output of the operational amplifier is connected to the second input of the adder, the output of which is the output of the device, the second signal The input of the differential stage is connected to the zero potential bus.