SU1429134A1 - Device for multiplying analog signals - Google Patents

Abstract

The invention relates to electrical computing devices and can be used in analog computers. The aim of the invention is to improve the accuracy. A device for multiplying analog signals contains the first and second controlled conductances performed on the first and second MOS transistors: -: 1 and 2, the first and second stages with 3-phase outputs 3 and 4, the first and second adders 5 and 6, the source of the bias voltage 7, the inputs of the first and second sirnal-multipliers 8 and 9, the output 10. The device is based on regulating the conduction of the channel of the second signal-multiplier using the first signal-multiplier. 1 il. / g S

Description

(L

with

four

Yu

00 4ik

I The invention relates to electrical computing devices and can be used in analog computers, I The purpose of the invention is to improve accuracy.

The drawing shows a functional diagram of a device for multiplying analog signals,

; The device contains the first 1 and the second 2 MOS transistors, the first 3

the second 4 stages with paraphase leads, the first 5 and second b sums, the source 7 of the bias voltage, the inputs of the first 8 and second 9 signals of the multipliers, the output 10.

The device works as follows, I First C and second U input multiplier signals are split by the first 3 and second 4 stages with paraphase outputs into pairs of antiphase Delivery iU and tU respectively

For an explanation of the principle of operation, the gains of the first and second stages 3 and 4 with paraphase outputs are taken to be equal to one. The voltages -fU and -Uj are fed to the drains of the first and second MOSFET transistors 1 and 2 and to the fourth inputs. second and first adders 6 and 5 o. respectively. On the gates of the first and second MOS transistors 1 and 2 on. "

| give, respectively, the voltage C

 IH Ujjj, which are linear combinations of the antiphase components of the second iporo multiplier signal, the voltage, the bias U. of the output voltage of the device, and the voltages from the drain of the second and first MOS transistors. 2 and 1 respectively

 + UtM + К-, с Hi} ие ") г -Ktc and,, (1); Where, У. (., К, 1ц, Kjc - coefficients of proportionality.

According to the nodal voltage method, the output voltage of the device

and.

oats SuTfc

50

(2)

  gc ", where gcK, gcMt are the conductances of the first 1 and second 2 MOS transistors, respectively .55

Substituting in the expression (2) the value of the conductivities of the transistors, which depend both on the parameters of the transistors and on the voltages

on their electrodes, given the identity of the transistors, you can get

, t and x -

(3)

0

five

0 5

about

five

0

five

0

five

Thus, from the expression (3) for the output voltage of the device it can be seen that there is no coefficient depending on the parameters of the MOS transistors. This increases the stability of its gain regardless of external conditions.

Increased accuracy of operation is provided by compensating the harmonics of the second order from the first input and from the output signals in the output signal of the device. Compensation is provided by linearizing the conductances of the channels of the first 1 and second 2 MOS transistors by eliminating the dependence of the conductivity of the channels on the first input and output signals by applying these signals to the gates of the MOS transistors.

. Improving the multiplication accuracy is also achieved by increasing the stability of the gain of the device when the external conditions change. The increase in stability is achieved by eliminating the dependence of the gain on the material of the first 1 and second 2 MOS transistors, which becomes possible by eliminating the connection of the point where the sources of the first and second MOS transistors are combined with the zero potential bus.

Claims (1)

Invention Formula A device for multiplying analog signals containing the first and second controlled conductances made respectively on the first and second MOS transistors, whose sources are combined, the first adder, the first stage with the paraphase outputs, the input of which is the input of the first signal of the device multiplier, the voltage source bias, characterized in that, in order to improve accuracy, a second adder and a second stage with paraphase outputs are introduced into it, with the first and second outputs of the first stage with paraphase outputs are connected to first inputs of the first and second adders, the outputs of which are connected to the gates of the first and second MOS transistors, output is314291344 the bias voltage point the second-cascade connection from the paraphase height to the second inputs of the first and second passages is connected to the drain of the second adders, to the third inputs of which the MOSFET and with the fourth input the sources are connected, respectively, to the first adder, the input to the second power and the second MOS transistor, the power supply with paraphase outputs is output of the second stage with a parafae input of the second signal multiplier These outputs are connected to the drain of the pen device, the output of which is first MOS transistor and with the fourth united sources of the first and second the input of the first adder, the second you QMOS transistors.