SU1160396A1 - Computing device with variable length of operands - Google Patents

Abstract

COMPUTATIONAL DEVICE WITH A VARIABLE OPERAND LENGTH containing the registers of the first and second operands, the setup register, the operation coder, the arithmetic logic unit, the mask unit, the first multiplexer and the correction unit, the outputs of the registers of the first and second operands are connected to the first and second information blocks the inputs of the arithmetic logic unit, the outputs of the sum and transfers of which are connected respectively with the first and second information inputs of the correction unit, the first and second controls to the moves of which connect 1, respectively, with the output of the tuning register mode and the first output of the operation encoder, the output of the sum of the arithmetic logic unit is connected to the information input of the first multiplexer, the control input of which is connected to the first control input of the masking unit and the output of the length of the setting register mask, the second and the third outputs of the operation encoder are respectively connected with the second control input of the masking unit and the operation code input of the arithmetic logic unit, the mode and transfer inputs of the cat Which is connected respectively to the outputs of the mode and transfer of the tuning register, the output of the masking block is the output of the result of the device, the input of the operation encoder is the input of the type of operations by the device. VA, which, in order to reduce the number (A of the equipment, it contains the second and third multiplexers and the transfer matrix, the output of the correction unit connected to the information input of the masking unit, the outputs of the first and second operand registers are connected to the information inputs of the second and third multiplexers, the control inputs of which are connected to the outputs of the length of the mask of the register of adjustment, the outputs from the first, second and third multi; about plexors, are connected to the corresponding cipherto inputs ra transfer, the output of which is the code: the transfer of the device, the outputs of the second and third multiplexers are respectively the outputs of the higher variable bits of the first and second operands of the device.

Description

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The invention relates to computing technology and can be used in the construction of operating devices of high-performance computers.

A computing device is known that performs operations on variable-length fields and contains operand registers, adder, switches, result register 0}

The disadvantage of the computing device is the low fast speed, Bie, since the execution of operations on variable length fields is carried out by-byte.

A computing device is known that contains operand registers, a result register, an adder, switches, a mask register, and converters. In this device, the operation is performed simultaneously for the entire word {53.

The disadvantage of the device is significant hardware costs.

The closest in technical essence to the invention is a computing device comprising registers of the first and second operands, an adder, a correction unit, a setup register, an encoder, a logic operation unit, a multiplexer, a masking unit, and a switch, the first and second adders codes connected to the inputs correction block and multiplexer, the outputs of the registers of the first and second; horny operands are connected to the first and second inputs of the adder, the first and second inputs of the block of logical operations and the first and second The third information input inputs of the switch, the third and fourth information inputs, the output and control input of which are connected respectively to the outputs of the adder, the correction unit, the first input of the masking unit and the first output of the encoder, the first output of the setting register is connected to the first input of the correction unit, the second output of the register settings - with the control input of the multiplexer and the second input of the masking unit, the first output of the encoder is connected to the second input of the correction unit, the second output of the encoder is connected to the third input Lok masking, whose output is the first output device control registers gatsie operand inputs, the first.

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The second, third, and fourth inputs of the tuning register and the input of the encoder are the control inputs of the {3j device.

5 A disadvantage of the known device is a significant hardware cost and a narrow field of application due to the lack of possibility of obtaining higher variables 0 bits of operands.

The purpose of the invention is a reduction. quantities of equipment.

The goal is achieved

. the fact that the computing device with the variable-length operands, containing the registers of the first and second operands, the register settings, the encoder operations, arithmetic logic

 block, mask, first

a multiplexer and a correction unit, with the outputs of the registers of the first and second operands connected to the first and second information respectively. arithmetic logic unit, the sum and transfer outputs of which are connected respectively to the first and second information inputs of the correction unit, the first and second control inputs of which are connected respectively to the output of the tuning register mode and the first output of the operation encoder, the output of the sum of the arithmetic logic unit with information entry

5 of the first multiplexer, the control input of which is connected to the first control input of the masking unit and the output of the length of the setup register mask; the second and third outputs

the operation encoder is connected respectively to the second control input of the masking unit and the operation code input of the arithmetic logic unit, the mode and transfer inputs of which are connected respectively to the mode and transfer registers of the setting register, the output of the masking unit is the output of the device, the input of the operation encoder is the input of the type of operations of the device contains the second and third multiplexers and the transfer encoder, with the output of the correction unit connected to the information input of the masking unit, output The registers of the first and second operands are connected respectively to the information inputs of the second and third multiplexers, the control inputs of which are connected to the outputs of the mask length of the tuning register, the outputs of the first, second and third multiplexers are connected to the corresponding inputs of the transfer encoder, the output of which is the transfer output of the device The outputs of the second center of the third multiplexer are, respectively, the outputs of the higher-order bits of the first and second operandos of the device. FIG. 1 is a diagram of a computing device with variable length operands j in FIG. 2 is an example of an arithmetic logic unit circuit. The device contains the registrar 1 of the first operand, the register 2 of the second operand, the arithmetic logic unit 3, the correction unit 4, the setting register 5, the encoder 6 operations, the masking block 7, the first multiplexer 8, the second multiplexer 9, the third multiplexer 1Oj transfer encoder 11, output 12 results, output 13 higher variable bits of the first operand, output 14 of the higher variable bits of the second operand, transfer output 15, mode input 16, inputs of mask length 17, transfer input 18, inputs 19-21 of the second cipher 11 inputs 22-24 operation mode and transfer code Lok summing 3, the output unit 25 inputs 26-36 masking type operations. Arithmetic logic unit 3 (Fig. 2) contains arithmetic logic four-bit units 37 implemented on chips 100 PI 181, AND-OR 38 elements, AND 3 element inputs 40 and 41 operands, sum outputs 42 and 43 transfers. The transfer coder 11 generates the transfer from the higher variable bit of the result:: Input 20 О О 1 1 О 1 О 1 Input 21 О 1 О 1 О О .1 1 Input 19 00001111 Output 15 О 1 1 О О О О 1 Block 7 masking is similar to the known. The input information arriving at the input of block 7 of the mask is passed to exit 25 without changing with a full mask or only those bits that are matched with the unit field. 64 Seven-bit setting register 5 contains the data necessary for the operation of the computing device of variable length. The first bit (input 16 and the first output of register 5 settings) is binary or arithmetic, In the first case, the information from the output of block 3 of the program is corrected without correction. In the second case, the result is corrected in accordance with the values of the tetrad transfers. The second - the sixth bit (input 17 and the second output of the register 5 settings) - the mask length parameter. The seventh bit (input 18 and the third output of register 5 settings) is the transfer to the lower bit of the device. The encoder 6 of the operations converts the signals of the type of operation into the control signals of the arithmetic unit and the masking unit according to the table. The device works as follows. Registers 1 and 2 accept operands. The setting register 5 contains the code defining strong binary or binary decimal operations, the length of the operands and the transfer to the low-order bit. The encoder 6 operations, one of the inputs 26-36, receives information about the type of operation that should be performed, Operands arrive at the input of the unit, where the operation code at input 22, the operation mode at inputs 23 and the transfer operation at input 24 are performed with the specified operation. The result from block 3 goes to correction block 4, where in the case of binary-decimal arithmetic, the necessary correction is made depending on whether the addition or subtraction was performed in the device. In binary arithmetic, the result is transmitted through correction unit 4 without changing to the input of masking unit 7. According to the length of the mask, it comes from the output of the length of the mask register 5 real-. and the masking resolution from the output of the encoder 6 operations, we obtain at output 25 of the block .7 masking a result that will have zeroes in bits with numbers larger than the code length code of the mask. From output 25 of the beacon unit 7 it goes to output 12 the result of the device.

The values of the operands from the outputs of registers 1 and 2 and the value of the sum from the output of block 3 arrive at the inputs of multiplexers 9, 10 and 8, where the value of the high-order variable bits of the operands and the sum are selected according to the code length of the mask. The receipt; -. ™ --- enters encoder 11

the transfer, at the output of which a signal appears equal to one, if there was a transfer from the variable high bit of block 3, and zero.

When working with Binary Arithmetic, the transfer value from. high alternation, as in a known device ignores c.

The positive effect of the invention is to reduce the number of equipment required for the realization of the device (consisting of device operations, the amount of equipment of which is substantially larger than the two multiplexers introduced, and the transfer coder). In addition, in the proposed device, the high-order bits of the operands are also determined. the state eliminates the switch and the unit

Note. X, Y - the first and second operands. So, S, 5, Sj, M position control code arithmetic logic unit.

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Claims (1)

COMPUTER DEVICE WITH VARIABLE LENGTH OF OPERANDS, containing the registers of the first and second operands, the setup register, the operation encoder, the arithmetic-logical unit, the masking unit, the first multiplexer and the correction unit, and the outputs of the registers of the first and second operands are connected respectively—; with the first and second information inputs of the arithmetic-logical unit, the outputs of the sums and transfers of which are connected respectively to the first and second information inputs of the correction unit, the first and second control inputs of which are connected respectively to the output of the setting register mode and the first output of the operation encoder, the output the sum of the arithmetic-logical unit is connected to the information input of the first multiplexer, the control input of which is connected to the first control input of the masking unit and the output of lengths masks of the setup register, the second and third outputs of the operation encoder are connected respectively to the second control input of the masking unit and the input of the operation code of the arithmetic-logical unit, the inputs of the mode and transfer of which are connected respectively to the outputs of the mode and transfer of the settings register, the output of the masking unit is the output of the result of the device The input of the operation encoder is the input of the type of operation of the device, characterized in that, in order to reduce the amount of equipment, it contains a second and third multiplier exporters and transfer encoder, the output of the correction unit being connected to the information input of the masking unit, the outputs of the registers of the first and second operands are connected respectively to the information inputs of the second and third multiplexers, the control inputs of which are connected to the outputs of the mask length of the setup register, the outputs of the first, second, and third multiplexers connected to the corresponding inputs of the transfer encoder, the output of which is the output of: ', the transfer device. The outputs of the second and third multiplexers are respectively, the outputs of the senior variable bits of the first and second operands of the device. 1 11